JPH0365748A - Interface circuit for integrated circuit - Google Patents

Abstract

PURPOSE:To prevent a latch miss from being generated by passing a data signal during the low-level period of a clock signal and temporarily holding the data signal in rising to a high level by a second memory cell group. CONSTITUTION:The interface circuit is provided with a buffer 8 for the clock signal to be led into a clock signal terminal 7, and a buffer 3 for the data signal to be led into a data signal terminal 2 and timing signal distributing means 10-13 to hierarchically distribute the clock signals, and a first memory cell group 5 to store the data signal according to the clock signal, which is distributed by the distributing means 10-13, at the first timing and to execute digital processing. Further, the second memory cell group 4 is provided to be connected respectively between the data buffer 3 and a first memory cell group 5, to temporarily hold the data signal from the data buffer 3 according to the clock signal 14 at a second timing, which is earlier than the first timing in a phase, and to deliver the data to the first memory cell 5. Thus, a data proba bility period can be prolonged to the first memory cell group in the next step and the mis latch can be prevented.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Field of Application) This invention is aimed at solving problems such as variations in wiring length and input capacitance within the integrated circuit when a system is configured by connecting a plurality of digital integrated circuits. The present invention is directed to an integrated circuit interface circuit that minimizes variations in signal delay time due to signal delay and ensures data reception between integrated circuits.

(Prior Art) FIG. 9 shows a conventional interface circuit that stores data signals in seven lip-flops in an integrated circuit by inputting a clock.

In FIG. 9, 1 is a digital integrated circuit constructed by laying out standard cells, gate arrays, etc.

This integrated circuit 1 is configured to store a data signal from a data signal terminal 2 in a flip-flop 5 via a series connection of an input buffer 3 and a delay element 18, and perform internal processing. The clock signal from the clock signal generator 6 is
A clock signal is input to the buffer 8 via the terminal 7 and driven. The output clock signal is input to the flip-flop 5 via the even-numbered stages of inverter elements 10 to 13.

The inverter elements 10 to 13 are actually one of the selection branches connected in a dendritic manner, and each selection branch forms a hierarchical lock signal to control internal storage cells such as flip-flops. It is meant to be controlled. The flip 70 tube 5 stores data at the timing when the clock rises from low level to high level, and outputs the stored data until the clock changes from low level to high level again.

The delay element 18 delays the data signal input to the flip-flop 5 so that racing does not occur between the flip-flop 5 and the flip-flop 5 when data is transferred to a subsequent flip-flop (not shown). In addition, the clock signal is normally delivered using an in-phase clock because it is necessary to take into account duty variations (±15%) with an inverted clock.The inverter elements 10 to 13 are arranged in even stages (four). This is because of this reason.

In the above, the clock rate of the clock signal is several Ml
- If the frequency is high (12 to several tens of MHz), and if there is a difference in delay time due to differences in power supply voltage, temperature, manufacturing variations, etc. between ICs, variations in the time from clock input to data output may occur. In general, the amount of time that data is available is shortened.

Now, taking into consideration the wiring layout, variations in input capacitance, etc., the timing relationship between the data determination period of the data signal guided to the data signal terminal 2 and the clock signal guided to the clock signal terminal 7 is shown in FIG. As shown in FIG. 2, let us consider a condition in which the data determination period is as short as ±7 nsec with respect to the clock rate of the clock signal 7 Q n5ec. In such a case, when the data signal is transferred to the flip-flop 5, the data determination period becomes shorter than the clock signal, as shown in FIG.

FIG. 11 shows a timing chart of the data signal and clock signal before being input into the integrated circuit, and the data signal and clock signal after being input. (a) is the clock signal before input, that is, at the clock signal terminal 7; (b) is the data signal at the data signal terminal 2; (C) is the clock signal output from the inverter element 13; (d) is the clock signal at the delay element 1.
represents the data signal output from 8. According to this, the data signal and clock signal input to the flip-flop 5 have a setup time margin of 2.5 mm, as shown in the timing charts (C) and (d). l 3 n
5ec, the hold time margin is 1.66nsec.

The above set-up and hold time margins are as follows:
It was determined from Figure 2. Figure 12 shows each element shown in Figure 9 (
Iruka buff? 3. The delay amount (unit: n5ec) of the delay element 18 and input buffer 8) is calculated using the virtual wiring length. Here, LH indicates a change from low level to high level, and HL indicates a change from high level to low level. In addition, k is a constant representing the variation width of delay time due to power supply voltage, ambient temperature, manufacturing variation, etc., and in the case of standard cells and gate arrays, it is 0.4
It takes a value of ~2.23. Usually when designing an IC, k
The value of is constant inside the IC. In addition, the standard is expressed as 1 for the variation width.

In the case of the circuit shown in Figure 9, when k=2.23, LH and IIL are respectively 12.91 n5ec,
ML is 15.32nsec, and setup time is 7-(15,32-14,45)-6,13ns
ec.

Hold time is 7-(14,45-12,91)=5
．． It becomes 46 nsec. Here, the set-up time and hold time of the low level L regarding the flip-flop 5 are 1 and 8 n, respectively, based on predetermined input characteristics.
5ec, 1, 7 n5ec, and when k = 2°23, approximately 4.0nsec and 3.8nsec, respectively.
becomes. Therefore, the setup time margin is 6.13
-4.0=2.13, hold time margin is 5.64
-3.8-1.66.

Furthermore, when the internal layout of the IC is actually performed, there is a difference between the virtual wiring length used at the time of design and the actual wiring length after layout, resulting in a delay time different from that at the time of design. Differences tend to occur especially when automatic placement is performed, such as standard hills and gate arrays.

For example, in the delay element 18, the actual wire length is often shorter than the virtual wire length, and the delay time of the virtual wire length when k=1 is 4.
．． 21 (Lll), 4.20 (HL) nsec, the delay time when the wiring is the shortest is approximately 2
(LH/HL) nsec. Therefore, hold time cannot be obtained and latch errors occur.

In order to eliminate such problems, some standard cells and gate arrays are equipped with dedicated delay elements.
The circuit scale is large, and 20 grids are required for each 1-bit signal due to a delay of approximately 3 nsec, for example.

Further, with the recent development of IC microfabrication technology, the delay element 18 tends to have a shorter delay per element, and the circuit scale becomes larger. The circuit scale is represented by a grid representing the size on the wiring. The number of grids for each element used in FIG. 9 is expressed as η.The clock distribution inverter has 3 grids, the delay inverter has 2 grids, and the flip-flop has 7 grids. The delay element 18 is composed of six inverters, but in this case, 12 grids are required. Therefore, when there are many data signals, the delay element 18 increases the size of the circuit and is disadvantageous in terms of power consumption.

(Problem to be Solved by the Invention) In general, when data is transferred between ICs, there are differences in the delay time of each signal due to power supply voltage differences, ambient temperature differences, manufacturing variations, etc. The period becomes shorter. In particular, systems that are constructed by laying out basic cells such as standard cells or gate arrays,
Since there is a difference between the virtual wiring length used at the time of design and the actual wiring length, the delay time of delay elements etc. will change. In such a case, there is a problem in that the hold time of a flip-flop or the like inside the IC cannot be obtained, resulting in a latch error.

SUMMARY OF THE INVENTION An object of the present invention is to provide an interface circuit for an integrated circuit which eliminates the above-mentioned problems and stores data in memory cells within an IC without mislatching.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a buffer for a clock signal introduced into a clock signal terminal, a buffer for a data signal introduced into a data signal terminal, and a hierarchical structure for the clock signal. a first storage cell group for storing and digitally processing the data signal according to the first timing clock signal distributed by the distribution means; the data buffer; A clock signal having a second timing that is earlier in phase than the first timing is used to hold the data signal from the data buffer for one period and store the data in the first memory cell group. It is characterized by comprising a second memory cell group for passing the receiver to the cell group.

(Operation) The second memory cell group according to the present invention passes the data signal of the data signal terminal during the low level period of the clock signal,
Since it is held for a period of time when it rises to a high level, the data probability period can be made longer for the first storage cell group in the next stage, and mislatches are eliminated.

(Example> Hereinafter, it will be explained in detail using examples.

FIG. 1 is a block diagram showing an embodiment of an interface circuit of an integrated circuit according to the present invention.

In FIG. 1, the same elements as in FIG. 9 are given the same reference numerals. The digital integrated circuit 1 of this embodiment has a data signal 2
is buffer-amplified by an input buffer 3, and the amplified data signal is stored in a flip-flop 5 via a transparent latch 4. Transparent latch 4 is
It passes through the input when the clock is at low level, and stores the input at the rising timing when the clock goes from low level to high level. Data is output while the clock storing data is at a high level.

A clock signal is supplied from a clock signal generator 6 to a clock signal terminal 7. The clock signal from terminal 7 is buffered and amplified by input buffer 8, and then sent to inverter element 10.
.about.13 to the flip-flop 5.

The clock signal to the transparent latch 4 is
A clock signal (second timing) from the input buffer 8 is input.

Incidentally, the inverter elements 10 to 13 are actually connected in a dendritic manner as shown in FIG. 2, and supply clock signals to memory cells such as the flip-flop 5 in a stepwise manner.

According to this configuration, the data signal input from the data signal terminal 2 is input to the transparent latch 4 via the buffer 3. The transparent latch 4 stores the data signal input at the rising edge of the clock signal from the buffer 8, and outputs the data signal while the clock is at a high level. The flip 70 tube 5 stores the output of the transparent latch 4 at the timing of the rising edge of the clock signal.

Now, the operation of the transparent latch 4 and the flip-flop 5 will be described when the relationship between the clock signal and the data signal is supplied to each terminal 2.7 at the timing shown in FIG.

Figure 3 shows the delay amount (unit: n) of each element in the configuration of Figure 1.
5ec) is shown using virtual wiring length. In this figure, the output period delay amount of the transparent latch 4 is the delay in the end of the period during which the transparent latch 4 outputs the data signal, and is related to the 81 delay time of the clock signal.

When the delay amount of each element is as shown in FIG. 3, the timing at which the data signal is stored in the transparent latch 4 and flip-flop 5 is as shown in FIGS. 4 and 5.

Figure 4 shows the case where the variation width k is 0.4, and (a)
, (b) shows the clock and data signals at each terminal 3.2. (C) is transparent latch 4
(d) shows the data signal input to the latch 4, and (e) shows the clock signal input to the latch 4.
(f) shows a clock signal input to the flip-flop (FF) 5, and (f) shows a data signal input to the flip-flop (FF) 5, respectively. In addition, Fig. 5 shows the case where k is 2.23, and each signal (
a) to (f) are the same as in FIG.

For example, when k is 0.4, the data input to the transparent latch 4 is determined by the delay amount of the buffer 3 (Fig. 4 d).
In this case, the data determination period is shortened by a maximum of 0.92+0.64. On the other hand, the clock signal (FIG. 4C) is delayed by 0.78 by the buffer 8. The timing between the data confirmation period and the clock signal is such that the setup time margin is 5,9 Q n5ec, the hold time is The margin is 6.18 nSeC, and the delay time error 2 (LH/HL) n due to the difference between the virtual wire length and the actual wire length
Even when compared with 5ec, the data signal is reliably latched in the transparent latch 4.

Therefore, the transparent latch 4 passes the input when the clock signal is at a low level. Therefore, the flip-flop 5 can input a data signal delayed by 0.92+0.66, and can store the data signal before the transparent latch 4 stores and outputs the data. Now, flip flop 5
stores the output of the transparent latch 4 (FIG. 4f) as a clock signal delayed by the inverter elements 10 to 13 (FIG. 4e). The delay time of the clock signal in this case is 0.78+1.82. From these values, the margin for the setup time of the flip-flop 5 is determined to be 7.46.

In addition, since the period during which the transparent latch 4 outputs the data signal is the high level period of the clock signal, the hold time margin is the same high level period, the duty variation is 10.5, and the output period of the transparent latch 4 is delayed. Calculated from the minimum hold time when the amount is 0°94 and -0.4, 22.1
It becomes 6.

Even when k is 2.23, the delay time of the clock input to the transparent latch 4 (Fig. 5 C) is 4.37, and the delay time of the data input (Fig. 5 d) is 5°11.3.57. The setup time margin of latch 4 is 0.91, and the hold time margin is 2.41.
become. Also, the clock input to flip-flop 5 (
The delay time in Figure 5e) is 4.37+10.17,
The delay time of data manual input (FIG. 5f) is 3.66.

From these values, the setup time margin for flip-flop 5 is 13.87. In addition, the hold time margin is 11 from the minimum hold time when the high level period of the clock signal takes into account the duty variation of 10.5, the delay amount of the output period of the transparent latch 4 is 5°22, and 2.23. It becomes .17.

FIG. 6 shows the above-mentioned set-up time and hold time margins together. When k is 2.23, the margin of set-up time and hold time of the transparent latch 4 is 0.91°2.41, which is small compared to the delay time error caused by the difference between the virtual wire length and the actual wire length. However, since the delay time of the clock input and data input of the transparent latch 4 is determined only by the wiring lines 14 and 15, the delay time error is smaller than in the circuit of FIG. 9.

As described above, inverter elements 10 to 1 for clock distribution
It can be seen that a latch error of the flip-flop 5 does not occur even if the length of the wiring connecting between the two is different from the virtual wiring length depending on the IC internal layout and an error occurs in the delay time.

In addition, as for the circuit scale, transparent latch 4
The number of grids is five, which is approximately half the number of grids of the delay element 18.

Next, another embodiment will be described.

FIG. 7 shows another embodiment of the interface circuit according to the invention. Incidentally, elements common to those in the embodiment shown in FIG. 1 are given the same reference numerals.

In FIG. 7, the data signal is composed of N bits, and data signals introduced from data signal terminals 2N-21 are stored in flip-flops 5N-51, respectively. Correspondingly, a clock signal for driving the transparent latches 4N to 41 from the buffer 8 is inputted to each of the transparent latches 4N to 41 via the drive buffer 17. data buffer 3
The buffers 16N-161 connected between the transparent latches 4N-41 and the buffers 17
This is a delay element for matching the data signal to the delay time of the clock signal delayed by the clock signal.

The interface circuit with such a configuration uses a transparent latch 4N using a buffer 17 with a large driving capacity.
By providing a clock signal to 41, even if the number of bits of the data signal increases, the effect on the output waveform of the buffer 8 is reduced. Also, transparent latch 4N
~41 is input with a clock signal that is earlier in phase than the clock signal that controls the flip-flops 5N~51,
Similar to the circuit shown in Figure 1, even if a delay time error occurs due to the difference between the virtual wiring length and the actual wiring length, the flip-flops 5N~
51, data signals can be stored without latch errors. Furthermore, even if we assume that 8-bit data is input, the buffer 17 will have a grid size of 7. buffer 16
is 3, which does not increase compared to FIG.

FIG. 8 shows yet another embodiment.

In this embodiment, the clock signal from the buffer 8 is supplied to the transparent latches 4N to 41 via the inverter 19.

Even with this configuration, the output waveform of the buffer 8 is not affected when the input data is multi-bit. In addition, since the inverter cable 19 has a shorter delay time than a non-inverter type buffer, the data buffers 3N to 3
There is no need to insert a delay buffer between 1 and the transparent latches 4N to 41.

[Effects of the Invention] As explained above, according to the present invention, in an IC in which basic cells such as standard cells and gate arrays are configured by layout, delay time errors due to the difference between virtual wiring length and actual wiring length can be suppressed, Accurate input data can be memorized.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of an interface circuit of an integrated circuit according to the present invention, Fig. 2 is a circuit diagram detailing the above embodiment, and Fig. 3 is a diagram for explaining the amount of delay of each element. FIGS. 4 and 5 are time charts showing the operation of the above embodiment, and FIG. 6 is an explanatory diagram showing margins of set-up time and hold time improved by the above embodiment. , FIG. 7 is a block diagram showing another embodiment of the present invention, FIG. 8 is a block diagram showing still another embodiment, FIG. 9 is a block diagram showing a conventional interface circuit, and FIG. 10 is a block diagram showing the above-mentioned interface circuit. FIG. 11 is a time chart showing the timing of input lock and data to the conventional circuit, FIG. 11 is a time chart showing the operation of the conventional circuit, and FIG. 12 is an explanatory diagram showing the amount of delay of each element in the conventional circuit. 1... Digital integrated circuit, 2... Data signal terminal,
3... Data buffer, 4... Transparent latch, 5... Flip 70 tube, 6... Clock signal generator, 7... Clock signal terminal, 8, 9...
10 to 13.19... Inverter element. Figure 1 Figure 2

Claims (1)

[Claims] A buffer for driving a clock signal introduced into a clock signal terminal, a buffer for driving a data signal introduced into a data signal terminal, and a timing signal distribution means for hierarchically distributing the clock signal. , a first storage cell group for storing and digitally processing the data signal according to the clock signal of the first timing distributed by the distribution means, the data buffer and the first storage cell group; a clock signal having a second timing that is earlier in phase than the first timing to hold the data signal from the data buffer for one period and transfer the data to the first memory cell group; 1. An interface circuit for an integrated circuit, comprising: two memory cell groups.