JPH06177730A - Reset circuit and integrated circuit including same - Google Patents

Abstract

PURPOSE:To output a reset signal independently of a waveform of a power supply voltage by outputting a dissidence signal as the reset signal when one of plural registers is set to a value different from a predetermined logic value after application of power. CONSTITUTION:The reset circuit is designed so that registers R1-R4 are liable to set to logical 0 and registers R5-R8 are liable to set to logical 1 at application of power respectively. The registers R1-R4 are to set to logical 0 and the registers R5-R8 are set to logical 1 at application of power respectively as the initial setting. In this state, a reset signal RST is outputted from an OR circuit. Even if seven registers at maximum among the eight registers R1-R8 are set to an opposite logic level to the initial setting at application of power, an OR circuit 5 outputs a reset signal RST. That is, when at least one register is set to the prescribed expected value at application of power, the reset signal RST is outputted and the reset signal is generated independently of the waveform of the power supply voltage at application of power.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset circuit, and more particularly to a reset circuit used for resetting an integrated circuit integrated on a semiconductor substrate when power is turned on. The invention also relates to an integrated circuit including this reset circuit.

[0002]

2. Description of the Related Art Conventionally, resetting of an integrated circuit formed on a semiconductor substrate at the time of power-on is required by providing a reset circuit inside or outside the integrated circuit for generating a reset signal when the power is turned on. It was common to perform a reset operation.

5 and 6 are block diagrams showing an example of a conventional reset circuit. In the circuit shown in FIG. 5, the reset terminal of the integrated circuit 10 is connected to the output terminal of the reset circuit 20, which is formed by connecting the resistor R and the capacitor C in which diodes are connected in parallel to each other in series. It is configured to apply a reset signal.

Further, in the circuit shown in FIG. 6, a reset circuit 20a is constituted by a constant voltage power supply circuit, and its output signal VOU
T is supplied to the reset terminal of the integrated circuit 10.

[0005]

However, in the conventional reset circuit, when the power is turned on depending on the conditions such as the magnitude of the power supply voltage used by the integrated circuit receiving the reset signal and the rising slope of the power supply voltage when the power is turned on. The ability to generate a reset signal was limited. For example, the CR reset circuit shown in FIG. 5 has a problem that the slope of the rising edge of the power supply voltage at power-on is limited due to the characteristics of the circuit and cannot be used for a slope smaller than a certain level.

Further, in the reset circuit for generating a reset signal by using the constant voltage power supply circuit shown in FIG. 6, there is a limit to the magnitude of the power supply voltage used by the integrated circuit which receives the reset signal due to the characteristics of the circuit. There is a problem that it cannot be used for power supply voltage lower than the level.

The present invention has been made to solve the above-mentioned problems, and is not limited to the waveform of the power supply voltage when the power is turned on, and a reset circuit capable of issuing a reset signal even at a low power supply voltage, and An object of the present invention is to provide an integrated circuit in which included circuits can be reset without limitation.

[0008]

In a reset circuit according to the present invention, a plurality of registers each set to a predetermined logical value after a lapse of a predetermined time from power-on, and each of the plurality of registers are respectively set to the predetermined values. A logic circuit that outputs a coincidence signal while being set to a logic value, and outputs a non-coincidence signal as a reset signal while at least one register has a value different from the predetermined logic value. It is characterized by

It is preferable that the at least one register has a logical value at power-on different from the predetermined logical value depending on design conditions of a process or a circuit.

It is preferable that the plurality of registers are connected in series to form a shift register, and that a logical value thereof becomes a predetermined logical value when a clock signal is inputted a predetermined number of times.

This shift register is "0" when the power is turned on.
It is preferable to have a first register string consisting of a plurality of registers that are easily set to "1" and a second register string consisting of a plurality of registers that are easily set to "1".

It is preferable that the registers that are easily set to "0" and the registers that are easily set to "1" when the power is turned on are alternately arranged.

Further, in the integrated circuit according to the present invention, a plurality of registers which are set to a predetermined logical value after a lapse of a predetermined time from power-on, and each of the plurality of registers are set to the predetermined logical value respectively. A reset circuit having a logic circuit that outputs a match signal while the reset signal is present and outputs a mismatch signal as a reset signal while at least one register has a value different from the predetermined logic value. It is characterized in that a circuit controlled by a reset signal of a reset circuit is integrated on the same semiconductor substrate.

[0014]

The plurality of registers are configured to be set to a predetermined logical value after a lapse of a predetermined time after the power is turned on. However, when the power is turned on, the logical value of these registers is different from the predetermined logical value. It is designed according to the process or circuit design conditions so that it will have a different value.

The logic circuit of the reset circuit outputs a coincidence signal when a plurality of registers have a predetermined logical value, and outputs a non-coincidence signal when only one register has a different logical value from the predetermined logical value. It is configured to output. Therefore, when the power is turned on, at least one of the plurality of registers has a value different from a predetermined logical value, so that a mismatch signal is output from the logic circuit, and this mismatch signal is output as a reset signal.

By forming this reset circuit and another circuit controlled by this reset circuit on the same substrate, a dedicated terminal for receiving a reset signal from the outside is not required.

[0017]

EXAMPLES The present invention will be described in detail below based on examples. FIG. 1 is a circuit diagram showing a reset circuit according to an embodiment of the present invention. This reset circuit is composed of a plurality of registers and a logic circuit which outputs a match signal or a mismatch signal from the combination of the logical values of the registers. In the embodiment shown in FIG. 1, the case of an 8-bit register will be described. The number of registers is not limited to 8 bits, and the larger the number of registers is, the more preferable it is to achieve the object of the present invention.

In FIG. 1, R1 to R8 indicate registers. The logic circuit 1 has outputs d1 to R1 of the registers R1 to R8.
It receives d8 as an input and outputs a reset signal RST according to the contents of the logical value of the register. Here, registers R1 to R
4 is designed in a circuit or process manner so that the logical value is easily set to "0" when the power is turned on, and the registers R5 to R8 are easily set to the logical value "1" when the power is turned on. That is, to this end, register R1
The ion implantation conditions are slightly changed so that VTH is set differently within the allowable limit between the transistors forming .about.R4 and the transistors forming the resistors R5 to R8.

The outputs d1 to d4 of the registers R1 to R4 are N
The inputs of the AND circuit 2 are connected to each other, and the outputs d5 to d8 of the registers R5 to R8 are connected to the inputs of the NOR circuit 3, respectively. The output of the NAND circuit 2 is connected to one input of the OR circuit 5, and the output of the NOR circuit 3 is connected to the other input of the OR circuit 5 via the inverter 4. The output of the OR circuit 5 is the reset signal RS
It becomes T. The registers R1 to R4 and R5 to R8
In each of the above, the Q output of the previous stage is the D input of the next stage. The reference voltage is connected to the D input terminal of the register R1 and the D input terminal of the register R5 is grounded.

FIG. 2 is a circuit diagram showing a detailed circuit configuration of the registers R1 to R8 shown in FIG. 1. The data input terminal D, the clock input terminal CLK, and the output terminal Q shown in the figure are respectively assigned the same reference numerals as shown in FIG. It corresponds.

In this circuit, an inverter I1, cyclically connected inverters I2 and I5, inverter I3, and cyclically connected inverters I4 and I6 are connected in series between the D input and the Q output.
, I3, I5, I6 are clocked inverters. The two-stage inverters I7 and I8 are connected in series, and the clock signal CLK is supplied to the inverter I7. The output of the inverter I7 is the inverters I1 and I6.
And the output of inverter I8 is provided to inverters I3 and I5.

The OR circuit 5 in the circuit shown in FIG.
The condition that the reset signal RST which is the output of the register R1 is not output, that is, the condition that the logical value 0 is output, the outputs d1 to d4 of the registers R1 to R4 are all set to “1” and the output d5 of the registers R5 to R8 is set. This is a case where all of d7 are set to "0". As described above, the logical values of the registers R1 to R4 are easily set to "0" when the power is turned on, and the registers R5 to R8 are set to "1".
Since it is designed so that the reset signal RST is not easily output, the probability that the reset signal RST is not output as described above is extremely low.

In the embodiment shown in FIG. 1, four registers R1
~ R4 constitutes a first shift register, and register R5
˜R8 form a second shift register. This 2
One shift register uses the clock signal CLK as a shift clock. The clock CLOCK may be, but is not limited to, the clock used for normal operation of the integrated circuit driven by the reset circuit.

Next, the circuit operation of the reset circuit of FIG. 1 when the power is turned on will be described. When the power is turned on, the registers R1 to R4 are set to "0", and the registers R5 to R4
8 is initially set to "1". In this state, the OR circuit 5
Outputs a reset signal RST. Even if a maximum of seven of the eight registers R1 to R8 are set to a logical value opposite to the initial set value described above when the power is turned on, the OR circuit 5 outputs the reset signal RST. . That is, if at least one register is set to the above-mentioned expected value when the power is turned on, the reset signal RST will be output.

The reset signal RST output from the OR circuit 5 initializes or resets the integrated circuit driven by the reset signal RST. Subsequently, the clock CLOCK used for the normal operation of the integrated circuit driven by the reset circuit operates, and the shift register composed of the registers R1 to R4 and the data in the shift register composed of the registers R5 to R8 are shifted. Shift is performed. The register R1 is forcibly set to "1" and the register R5 is forcibly set to "0", and these are transferred.
In four clocks, the logical values of the registers R1 to R4 are all set to 1, and the logical values of the registers R5 to R8 are all set to 0. Then, the reset signal RST of the OR circuit 5 or the like is released, that is, the logical value becomes "0", and the normal operation of the integrated circuit becomes possible.

In the embodiment shown in FIG. 1, when the power is turned on, two shift registers are constructed by using a register that is easily set to "0" and a register that is easily set to "1", and the reset signal is generated by the logic circuit 1. Although it is configured to output RST, it is not always necessary to configure in this way, and for example, a shift register may be configured using only the registers R1 to R4 that are easily set to "0" at the time of power-on, or The reset circuit of the present invention can be configured by using only the registers R5 to R8 that are easily set to "1" when the power is turned on.

If both the register which is easily set to "0" and the register which is easily set to "1" are provided as in the embodiment of FIG. Even if there is a tendency that it is easy to set to either "0" or "1", either the register that is easily set to "0" or the register that is easily set to "1" may be their expected value. Therefore, the reset circuit of the present invention can be reliably constructed.

FIG. 3 is a circuit diagram showing another embodiment of the present invention. This diagram shows not only simple connections but also the register arrangement in an actual integrated circuit.

In this embodiment, the circuit is exactly the same as that of the embodiment of FIG. 1, but the registers (R5, R7, R6, R8) and "0" which are easily set to "1" when the power is turned on are set to "0". Registers that are easy to set (R2, R4, R1,
R3) and R3) are alternately arranged. By performing such an arrangement, it is possible to reduce the influence of the process variation on the position, and even if the variation occurs in the semiconductor device manufacturing process, one of the registers surely differs from the predetermined logical value. It has a value. Therefore, the influence on the manufacturing process can be reduced.

FIG. 4 is a schematic configuration diagram of the integrated circuit 100 according to the present invention. The integrated circuit 100 is, for example, a memory circuit. A reset circuit 20 according to the present invention, a memory control circuit 50 controlled by a reset signal RST supplied from the reset circuit, an input / output circuit 60,
The address register 70 and the data register 80 are formed on the same semiconductor substrate. Further, in this embodiment, the clock signal CLK for each circuit is also used as the clock signal for the reset circuit. This integrated circuit does not require a dedicated terminal for receiving the reset signal RST from the outside.

[0031]

As described above in detail with reference to the embodiments, according to the present invention, a reset circuit capable of generating a reset signal without being limited to the waveform of the power supply voltage at power-on is constructed. Therefore, the reset signal can be supplied even when the operating power supply voltage of the integrated circuit is low.

Further, since the reset circuit of the present invention can be integrally formed on the semiconductor substrate together with the integrated circuit driven by the same, there is no need for a dedicated terminal for inputting a reset signal outside the driven integrated circuit. .

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a reset circuit of the present invention.

FIG. 2 is a detailed circuit diagram of a register used in the circuit of FIG.

FIG. 3 is a circuit diagram showing another embodiment of the reset circuit of the present invention.

FIG. 4 is a schematic configuration diagram of an integrated circuit according to the present invention.

FIG. 5 is a circuit diagram showing an example of a conventional reset circuit.

FIG. 6 is a circuit diagram showing an example of another conventional reset circuit.

[Explanation of symbols]

 1 logic circuit 2 NAND circuit 3 NOR circuit 4 inverter 5 OR circuit 20 reset circuit 50 memory control circuit 60 input / output circuit 70 address register 80 data register 100 integrated circuit

Claims (8)

[Claims] 1. A plurality of registers that are set to a predetermined logical value after a lapse of a predetermined time from power-on, and a coincidence signal while each of the plurality of registers is set to the predetermined logical value. A reset circuit including a logic circuit which outputs and outputs a mismatch signal as a reset signal while at least one register has a value different from the predetermined logic value. 2. The logic value at power-on has a value different from the predetermined logic value depending on design conditions of a process or a circuit, wherein the at least one register has a value different from the predetermined logic value. Reset circuit. 3. A shift register is configured by connecting the plurality of registers in series, and a logical value thereof becomes a predetermined logical value when a clock signal is input a predetermined number of times. The reset circuit according to claim 2. 4. The shift register is "0" when the power is turned on.
4. The reset circuit according to claim 3, further comprising a first register group including a plurality of registers that are easily set to "1" and a second register group including a plurality of registers that are easily set to "1". 5. The reset according to claim 4, wherein a register that is easily set to “0” and a register that is easily set to “1” when the power is turned on are alternately arranged on the semiconductor substrate. circuit. 6. A plurality of registers that are set to a predetermined logical value after a lapse of a predetermined time after the power is turned on, and a match signal while each of the plurality of registers is set to the predetermined logical value. A reset circuit having a logic circuit which outputs and outputs a mismatch signal as a reset signal while at least one register has a value different from the predetermined logic value, and is controlled by the reset signal of the reset circuit. An integrated circuit that integrates a circuit with a circuit on the same semiconductor substrate. 7. The reset circuit is composed of a shift register in which the plurality of registers are connected in series, and when a clock signal for operating the integrated circuit is input a predetermined number of times, a logical value is the predetermined logical value. The integrated circuit according to claim 6, wherein the integrated circuit is configured to have a value. 8. The shift register is "0" when power is turned on.
A first register group consisting of a plurality of registers easily set to “1” and a second register group consisting of a plurality of registers easily set to “1”, and a register easily set to “0” when the power is turned on, 8. Each of the registers easily set to "1" is alternately arranged.
The integrated circuit according to.