JPS61180995A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable a user to change optionally the chip selection information by using a programmable memory circuit which can set the optional information and deciding the chip selection signal based on the set information. CONSTITUTION:Nonvolatile semiconductor memory elements 11-13 which supply the signals S0, S1 and S2 to a gate from an input terminal for chip selec tion information are connected in series to load MISFETs 14-16 to which a reference power supply VDD is applied. Then the memory outputs T0, T1 and T2 extracted from contacts X1-X3 and those information S0-S2 are sup plied to exclusive OR circuits 17-10 respectively. A selection signal S is delivered from a NOR circuit 20. The states of elements 11-13 can be changed to optional forms in response to chip selection information. Thus it is possible to change the device selecting information without changing all semiconductor devices.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and more particularly to a mechanism for determining a chip select signal for selecting a device.

Conventionally, an information identification circuit has been provided which can identify a desired signal by using a fixed chip selection signal to select a device among a plurality of semiconductor integrated circuit devices constituting a microcomputer system. It is common practice to either specially order the integrated circuit device, or to add a data conversion circuit such as an inverter circuit to the outside of the information identification circuit of the standard or conventional device, as will be explained in more detail later. Ta. Therefore, the production cost increases due to the production of a wide variety of integrated circuit devices, or the cost increases due to the addition of additional circuits, resulting in an increase in the cost of the system.

In view of the above, the present invention was made based on the idea that the above drawbacks could be alleviated by allowing the user to freely set or change the device (chip) selection information of the integrated circuit device. It is.

That is, an object of the present invention is to provide a chip selection determination function in a semiconductor integrated circuit device that allows a user to arbitrarily change the chip selection information.

Another object of the present invention is to provide a semiconductor integrated circuit device capable of identifying various types of chip selection information with a single configuration. It is characterized in that the chip select signal is determined.

Next, the present invention will be explained with reference to ff.

FIG. 1 shows a circuit diagram of a conventional semiconductor integrated circuit having a random access function, and the number of input chip selection information is three. In the figure, address information persons are ranked from the lowest to the highest. ,A1,person,...
An address buffer 1 which inputs An and outputs row information &, R,, R, . . . Rr and column information L0, L2, . . . LL, and row information R0, R,, R, . Row decoder 2 which receives R' as input and generates row decode output DGL.
, a memory cell array 3 that connects one row selected by inputting the row decode output DGL to the wiring group CLG, and a column information mechanism. , Step 1, . . . In order to connect Ix and a part of the wiring group CLG equal to the number of column information lines, the column information lines are connected. , L
The column decoder 5 controlled by LtK, the selection signal S indicating whether a device has been selected, and the control signal RW controlling input/output control the information D0, D l
s...Dx is a column information engineer. ,■1,... Ix or column information engineering. , engineering,... Ix as information D0, D8,
. . . A selection signal S is obtained by inputting the input/output control circuit 5 that controls the Dx output and chip selection information s0, sl, and S consisting of system address information higher than the highest address information function as input signals. The information determining circuit 8 includes a NOR circuit 6i and an inverter 7. The inverter 7 converts the chip selection information s0 to 80' with the opposite phase.
It is for the purpose of

In the information identification circuit having the above configuration, the chip selection signal S
is 11" and an integrated circuit device is selected, and the signal S is 11".
Therefore, each of the inputs s, ', Sl, and S of the NOR circuit 6 are 0, that is, the chip selection information @S0, S3, and S is set to ``loo J, and the selection signal S is 1'', which means that the integrated circuit device has been selected. Chip selection information S0, s, and S are similarly Kl'
-010J and “001” also provide information s0 and Sl.
An integrated circuit device is selected by changing the input conditions of ,S.

And the specific code “100J, l-010J
When a device is selected by t or "001", the column decoder 5 converts the control signal KW, information D, , information stored in the Mori cell array 3 to information D+1, Dl, .・K is taken out as Dx so that the random access circuit can perform its function. Note that the chip selection information S0, S2,
S, combinations other than the above, i.e. "000", "111"
", "110J, [011J, "In 101J, the output selection signal S of the information determination circuit 8 is set to 10", indicating that no integrated circuit device is selected.

However, in the conventional circuit described above, the three types of chip selection information S0, Sl, S are "100", "010",
[If an integrated circuit is selected with a combination other than the 0QIJ combination, an additional inverter circuit must be added externally, or a random access circuit with a circuit configuration different from the information identification circuit shown in Figure 1 must be manufactured. I had to do it. However, in any case, such changes caused high costs for the system.

FIG. 2 is a circuit diagram of an embodiment of the integrated circuit device of the present invention. First, to mainly explain the configuration, three signals S, , S8, and S are sent from the chip selection information input terminal to the Mr8 field effect transistor (MI8 FF3T) 14.
．． 15. Memory outputs T6, T3 are connected in series to 16, respectively, and from contacts x, , x, , X8 to which both are connected.
,T! are taken out respectively. These memory outputs T6, Tt-'IL and the chip selection information 811.
81, S! Each corresponding pair of exclusive OR circuits 17 .
18.19 is input and outputs U,,U,.

U, is output. And these outputs are NOR circuit 2
It is output as a selection signal S from .

In the above, K for changing the state of the nonvolatile memory elements 11, 12, and 13 from on to off is also 1 on.
To return to , do the following: For example, the reference voltage VDD
In the example in which 5V is used as the reference voltage, applying approximately 15V to the gate and connection point (X,) to open, -I to substrate Y
OV, by removing the -40v1 source from the earth and applying approximately 35V to the gate, the element 11 returns from off to on.

Regardless of whether the selection information S0 or SI%S is set to "11" or "0" as a reference, it is retained as is.In addition, to change the state of a non-volatile element from off to on, there is also a method of exposing the element to ultraviolet light. However, in this case, it is necessary to form a part of the element container from a transparent material, such as a quartz plate.

If a heat-fuse type or junk-break type memory element used in bipolar integrated circuits is used as a nonvolatile memory element, the state can be changed only once for each element. In this case, when changing the combination of chip selection information sequentially changes the states of memory elements one by one, the combination can be changed multiple times.

As can be seen from the above, (1) in the present invention, the user can change the state of the nonvolatile memory elements 11, 12, 13 to any desired state with little effort in accordance with the chip selection information. Therefore, it is possible to change the device selection information without adding an external circuit or changing the entire semiconductor device as in the past, and it can be shared with the system, making it very suitable for IC implementation. It is.

In the above embodiment, three pieces of device (chip) selection information S0, S8, and S are used, but a larger number of pieces of information may be used, or only one piece of information may be used.

Using one piece of information means that by setting the nonvolatile memory element 11 on or off,
The purpose of this is to make the output U0 in the positive phase or in the negative phase, so that the U0 output can be supplied as a negative phase voltage source necessary for other circuits in the system. In addition, in the above embodiment, a NOR circuit was used for the gate indicated by 6, but
Instead of this, OR in relation to the input information S0, S3,...
It can be configured using a circuit or an AND circuit. Further, the circuit shown in FIG. 2 is merely an example, and the circuit is not limited thereto. For example, load MI8FET 1
4 may be replaced with a semiconductor resistor, and the logic circuit 17 may have various configurations, but in short, any logic circuit that can determine the chip select signal may be used. Furthermore, an n-channel MI8FET

[Brief explanation of drawings]

FIG. 1 is a block diagram of a semiconductor chip having a conventional random access circuit, and FIG. 2 is a circuit diagram of an information identification circuit according to an embodiment of the present invention. Explanation of symbols = 11-13 are nonvolatile memory elements, 14-
16 is a load MI8FET, 17 to 19 are exclusive OR circuits, and 20 is a NOR circuit.

Claims (1)

[Claims] A plurality of input terminals for inputting semiconductor chip select signals, a memory circuit provided corresponding to each input terminal and capable of setting arbitrary information, and input from the input terminal based on the information set in the memory circuit. 1. A semiconductor integrated circuit device comprising: a determination circuit that determines a chip select signal that is selected.