CN114462344A

CN114462344A - Analog signal repair circuit and repair method

Info

Publication number: CN114462344A
Application number: CN202210112286.7A
Authority: CN
Inventors: 韦韧; 江正忠
Original assignee: Shanghai Wuqi Microelectronics Co Ltd
Current assignee: Shanghai Wuqi Microelectronics Co Ltd
Priority date: 2022-01-29
Filing date: 2022-01-29
Publication date: 2022-05-10

Abstract

The application provides a repair circuit and a repair method of an analog signal, wherein the repair circuit comprises: a shift register; the first input ends of the patch units are connected with signal lines of a plurality of input signals in a one-to-one correspondence manner; the second input end of each patch unit is connected with the shift register, and the shift register is used for inputting an inverted signal into the corresponding patch unit according to a shift signal; the third input end of each patch unit is used for inputting an enabling signal; the patch unit is used for controlling whether to invert the input signal according to the enable signal and the inversion signal. Therefore, polarity correction of input and output signals between analog and digital in the digital-analog hybrid chip is realized.

Description

Analog signal repair circuit and repair method

Technical Field

The present disclosure relates to the field of integrated circuits, and in particular, to a repair circuit and a repair method for analog signals.

Background

In mixed signal integrated circuit designs, the connections of the digital-to-analog hybrid interface are very error prone. Especially during a digital-analog hybrid chip start (POR), power, clock, etc. on the chip may not start properly due to incorrect signal polarity.

Disclosure of Invention

The embodiment of the application provides a repair circuit of an analog signal, which is used for carrying out polarity correction on an input/output signal between analog and digital signals.

The embodiment of the application provides a repair circuit of analog signal, includes:

a shift register;

the first input ends of the patch units are connected with signal lines of a plurality of input signals in a one-to-one correspondence manner; the second input end of each patch unit is connected with the shift register, and the shift register is used for inputting an inverted signal into the corresponding patch unit according to a shift signal;

the third input end of each patch unit is used for inputting an enabling signal; the patch unit is used for controlling whether to invert the input signal according to the enable signal and the inversion signal.

In one embodiment, the patch unit includes:

one input end of the AND gate is used for inputting an enabling signal, and the other input end of the AND gate is connected with the shift register and is used for inputting an inverting signal;

one input end of the exclusive-or gate is connected with the output end of the and gate, and the other input end of the exclusive-or gate is connected with a signal line and used for receiving the input signal; and the output end of the exclusive-OR gate is used for outputting the output signal after the input signal is repaired.

In one embodiment, the shift register and the patch units form a patch module;

all signal lines of the input signal are divided into groups, and each group is connected with at least one patch module.

In one embodiment, the signal lines of the same functional module are distributed into a plurality of groups, and the patch modules corresponding to the groups modify the input signals of the signal lines of the same functional module.

In one embodiment, each group is connected with a plurality of patch modules, the patch modules are cascaded, and an input signal is input into a next patch module after one patch module is processed.

In an embodiment, the repair circuit further includes:

the first register is connected with the shift register and the patch unit;

and the reading circuit is connected with the first register and is used for loading the stored shift signal and the enable signal to the first register, providing the shift signal to the shift register through the first register and providing the enable signal to the patch unit.

In an embodiment, the repair circuit further includes:

a second register for storing an indication signal whether the patch unit is turned on in the sleep mode;

one input end of the second AND gate is used for inputting a sleep signal, and the other input end of the second AND gate is connected with the second register and is used for inputting the indication signal;

and one input end of the OR gate is used for inputting an enable signal, the other input end of the OR gate is connected with the output end of the second AND gate, the output end of the OR gate is connected with the third input end of the patch unit, and the updated enable signal is input to the third input end of the patch unit.

The embodiment of the application also provides a method for repairing the analog signal, which is applied to the circuit for repairing the analog signal, and the method comprises the following steps:

for each signal line, performing AND operation on an enable signal and an negation signal corresponding to the signal line to obtain a repair signal;

and carrying out exclusive OR operation on the input signal of the signal wire and the repair signal to obtain a repaired output signal.

In an embodiment, the method further comprises:

dividing all signal lines of input signals into a plurality of groups, and dispersing a plurality of signal lines of the same functional module into a plurality of groups; each group is connected with at least one patch module; the shift register and the patch units form a patch module;

and correcting input signals of a plurality of signal lines of the same functional module through a plurality of patch modules corresponding to a plurality of groups.

In one embodiment, the repair circuit further comprises: the first register is connected with the shift register and the patch unit; a read circuit coupled to the first register, the method further comprising:

loading the stored shift signal and the enable signal to a first register through a reading circuit;

and providing a shift signal to the shift register through the first register, and providing an enabling signal to the patch unit.

According to the technical scheme provided by the embodiment of the application, the patch unit can be connected to each signal line of the input signal, and the patch units can determine whether to invert the input signal or not under the control of the two signals based on the enable signal and the inversion signal passed by the shift register, so that the polarity correction of the input and output signals between analog signals and digital signals in the digital-analog hybrid chip is realized.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly described below.

Fig. 1 is a schematic diagram of a repair circuit for an analog signal according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram illustrating the principle of grouping and interleaving an input signal according to an embodiment of the present application;

fig. 3 is a schematic diagram of a cascade connection of a plurality of patch modules according to an embodiment of the present application;

fig. 4 is a schematic diagram of a repair circuit for an analog signal according to another embodiment of the present application;

fig. 5 is a schematic diagram of a repair circuit for an analog signal according to another embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

Like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined or explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

Fig. 1 is a schematic diagram of a repair circuit for an analog signal according to an embodiment of the present disclosure. As shown in fig. 1, the repair circuit includes: a shift register 10 and a plurality of patch units 20.

A plurality of signal lines for connecting a plurality of input signals to the first input ends of the patch units 20 in a one-to-one correspondence; a second input end of each patch unit 20 is connected to the shift register 10, and the shift register 10 is configured to input an inverted signal into the corresponding patch unit 20 according to the shift signal.

A third input of each of the patch units 20 is for inputting an enable signal. The patch unit 20 is configured to control whether to invert the input signal according to the enable signal and the invert signal.

For example, the input signal of one signal line may be 0 or 1, and the patch unit 20 may invert the input signal, change from original 1 to 0, and change from original 0 to 1 under the action of the enable signal and the invert signal, for example, when the enable signal and the invert signal are both 1. One signal line may be connected to one patch unit 20.

In one embodiment, as shown in fig. 1, each patch unit 20 includes: and gates and xor gates.

One input end of the and gate (i.e. the third input end of the patch unit 20) is used for inputting an enable signal, and the other input end of the and gate (i.e. the second input end of the patch unit 20) is connected to the shift register 10 and used for inputting an inverted signal. One input end of the exclusive or gate is connected to the output end of the and gate, and the other input end (i.e. the first input end of the patch unit 20) of the exclusive or gate is connected to a signal line for receiving the input signal; and the output end of the exclusive-OR gate is used for outputting the output signal after the input signal is repaired.

Specifically, for any input signal wire _ in, the output signal wire _ out can be expressed as follows: the Wire _ out is the Wire _ in ^ patch _ point. "^" indicates XOR if patch _ point is 1; then wire _ out equals the inverse of the wire _ in signal; otherwise, the wire _ out is the same as the wire _ in, thereby realizing the repair of the input signal. Therefore, the patch _ point (repair signal) can be generated by the patch unit 20, and the repair signal wire _ out can be outputted after the exclusive or operation with the input signal.

For example, when the Wire _ in is equal to 1, the patch _ point is equal to 1, the Wire _ out is equal to 0, when the Wire _ in is equal to 0, the patch _ point is equal to 1, and the Wire _ out is equal to 1, thereby implementing the signal inversion. when the Wire _ in is equal to 1, patch _ point is equal to 0, and Wire _ out is equal to 1; when the Wire _ in is equal to 0, the patch _ point is equal to 0, the Wire _ out is equal to 0, and the input signal and the output signal are the same.

As shown in fig. 1, taking a 32-bit wire _ in (input signal) as an example, assuming that one signal line in the wire _ in group needs to be inverted, and other inputs remain unchanged, one bit in the patch _ point is required to be 1; the other bits are 0. The embodiment of the present application uses a shift register 10 to achieve this:

the shift register 10 outputs the signal wire _ inv _ shift _ out [31:0] - {31 'h 0, 1' h1} <wire _ inv _ sel [4:0] so that only a 5-bit variable wire _ inv _ sel [4:0] (i.e., a shift signal) is required to shift 1 (the inverted signal) to any one of the 32 inputs.

Adding an enable signal to the output signal of each bit of the shift register 10, wherein a 32-bit repair signal Patch _ point [31:0] = path _ en [31:0] & wire _ inv _ shift _ out [31:0 ]; the final circuit implementation shown in fig. 1 may have the logic: wire _ out ═ Wire _ in ^ (path _ en [31:0] & ({31 'h 0, 1' h1} < < Wire _ inv _ sel [4:0 ])).

In one embodiment, the shift register 10 and the patch units 20 shown in fig. 1 form a patch module; since the actual input signal is often not only 32 bits, a grouping technique may be used to divide the signal lines of all input signals into several groups, each group being connected to at least one patch module. For example, an N-bit analog input signal may be formed into M groups, each group including N/M connections, typically to the power of 2, such as 16,32,64, etc. And completing independent polarity restoration inside each group of wires by inserting a patch module into each group of wires. If N is not an integer of M groups, N may be filled up.

In an embodiment, the plurality of signal lines of the same functional module may be distributed into a plurality of groups by an interleaving technique, and the plurality of patch modules corresponding to the plurality of groups modify the input signals of the plurality of signal lines of the same functional module.

It should be noted that, in the actual mixed signal design, the probability of polarity error is very small, and the polarity of one to several lines is often problematic, or the requirement of modification is needed later. And typically such signals are concentrated within one module. In this case, except that a larger N/M can be selected to reduce the number of patch modules, an interleaving technique can be adopted to group and scramble analog input signals according to functional modules, and signals of the same functional module are distributed to different groups by interleaving. Although only M patch modules are provided, when the signal of one functional module is concentrated and has errors or the polarity needs to be modified, the signals can be dispersed to a plurality of patch modules for processing, and the functions of the M patch modules can be fully utilized.

As shown in fig. 2, the functional modules may be USB (universal serial bus), DCDC (direct current converter), RF (radio frequency module), etc., the input signals of these functional modules may be N bits, N signal lines may be divided into M groups, the signal lines of the same functional module are dispersed in different groups, and each group is connected to one patch module. As shown in fig. 2, the patch modules may be repaired by N patches, the repaired output signal corresponding to the USB functional module is transmitted to the USB controller, the repaired output signal corresponding to the DCDC functional module is transmitted to the DCDC controller, and the repaired output signal corresponding to the RF functional module is transmitted to the DCDC controller.

In an embodiment, each group is connected with a plurality of patch modules, a plurality of patch modules are cascaded, and an input signal is input into a next patch module after one patch module is processed.

That is, one packet may not be limited to one patch module, and a plurality of patch modules are cascaded to support one packet to repair a plurality of signals. The signal delay caused by each patch module is an xor gate (exclusive or gate), which can be ignored. As shown in fig. 3, Wire _ out1 ═ Wire _ in ^ patch _ point 1; wire _ out2 is Wire _ out1 patch _ point 2. A packet may be a 31-bit input signal, the output signal processed by the first patch module being the input signal to the second patch module.

In an embodiment, as shown in fig. 4, the repair circuit provided in the embodiment of the present application may further include: a first register 40 and a read circuit 30. The first register 40 connects the shift register 10 and the patch unit 20; the read circuit 30 is connected to a first register 40. The reading circuit 30 is used for loading the stored shift signal and the enable signal to the first register 40, providing the shift signal to the shift register 10 through the first register 40, and providing the enable signal to the patch unit 20.

It should be noted that the most dangerous stage of the POR (start-up) stage of the chip is the start-up stage of the digital-analog hybrid circuit, most of the digital circuits are not operated, software cannot be intervened, or the execution cannot be modified in the romcode. Therefore, analog signal repair can be performed by using an on-chip OTP (OTP is a memory type of a single chip microcomputer), such as an efuse one-time programmable memory. During the POR stage, a POR read (read circuit 30) can be used to automatically load the efuse data (i.e., the data stored in the efuse) into a set of registers, referred to as the first register 40, for distinction. The set of registers is used directly to control the patch _ en signal (enable signal) and the wire _ inv _ sel signal (shift signal). Therefore, after the chip is started, the effect data can be automatically loaded to the first register 40, the shift signal is provided to the shift register 10 through the first register 40, the enable signal is provided to the patch unit 20, and the repair of the specified signal is completed. The read circuit 30 may be an existing data read circuit for reading data from the memory.

In an embodiment, as shown in fig. 5, the repair circuit provided in the embodiment of the present application may further include: a second register 50, an and gate 60 (referred to as the second and gate 60 for distinguishing from the and gate in the patch unit 20 above) and an or gate 70.

The second register 50 is used for storing an indication signal whether the patch unit 20 is turned on in the sleep mode; one input terminal of the second and gate 60 is used for inputting the sleep signal, and the other input terminal is connected to the second register 50 for inputting the indication signal. One input terminal of the or gate 70 is used for inputting an enable signal, the other input terminal is connected to the output terminal of the second and gate 60, the output terminal of the or gate 70 is connected to the third input terminal of the patch unit 20, and the updated enable signal is input to the third input terminal of the patch unit 20.

It should be noted that if the circuit can already support inverting the input signal of a certain signal line, the wire _ inv _ sel signal (shift signal) can be configured in advance, and the polarity of the output signal can be switched by switching the patch _ en (enable signal). For example, a low power chip often has a very low power "sleep" mode, which is indicated by a chip _ sleep mode (sleep mode), and the chip _ sleep signal may be used to switch the low power settings, so as to automatically turn off certain modules or make the modules enter the low power mode. However, the preset low power consumption mode configuration has the following disadvantages: it is possible that some considerations are insufficient and some signals do not have a corresponding low power configuration at low power consumption.

Therefore, the chip _ sleep signal can be used to control the patch _ en, so that the problem is solved universally: patch _ en _ all ═ Patch _ en | (chip _ sleep & chip _ sleep _ path _ en).

Where "&" represents an "and" operation and "|" represents an "or" operation. chip _ sleep _ path _ en is a pre-configured register (i.e., the second register 50) for indicating whether a certain patch element 20 is automatically turned on when chip _ sleep is equal to 1.

For example, for a 4-bit input signal, assuming that the enable signal Patch _ en is originally 1001, and chip _ sleep is equal to 1, that is, in the sleep mode, assuming that chip _ sleep _ path _ en is 1100, the Patch unit indicating the third bit and the fourth bit is turned on in the sleep mode, and based on the above calculation logic, the updated enable signal Patch _ en _ all is 1101, and the updated enable signal is input to the four Patch units 20 to repair the input signal.

In contrast, assuming that chip _ sleep is 0, i.e., not in the sleep mode, even if chip _ sleep _ path _ en is 1100, it is still 1001 based on the above logic formula Patch _ en _ all.

Therefore, based on the repair circuit shown in fig. 5, the output signal of each signal line can be specified to have a different configuration in the sleep mode.

The embodiment of the present application further provides a method for repairing an analog signal, where the method can be applied to a circuit for repairing the analog signal, and the method includes: for each signal line, performing AND operation on an enable signal and an negation signal corresponding to the signal line to obtain a repair signal; and carrying out exclusive OR operation on the input signal of the signal wire and the repair signal to obtain a repaired output signal.

Referring to fig. 1, the and operation and the xor operation may be performed by an and gate and an xor gate included in the patch unit 20. Reference is made in particular to the description of the corresponding embodiment of fig. 1.

In an embodiment, the method provided in the embodiment of the present application further includes: dividing all signal lines of input signals into a plurality of groups, and dispersing a plurality of signal lines of the same functional module into a plurality of groups; each group is connected with at least one patch module; the shift register 10 and the patch units 20 form a patch module; and correcting input signals of a plurality of signal lines of the same functional module through a plurality of patch modules corresponding to a plurality of groups.

Referring to fig. 2, according to the embodiment, input signals may be grouped by a grouping and interleaving technique, and input signals of the same functional module may be dispersed into different groups, so that when an input signal of a certain functional module is concentrated and abnormal, a plurality of patch modules may be dispersed to repair, thereby implementing load balancing.

In an embodiment, the method provided in the embodiment of the present application further includes: loading the stored shift signal and enable signal to the first register 40 through the read circuit 30; the shift register 10 is supplied with a shift signal through the first register 40, and the patch unit 20 is supplied with an enable signal.

Referring to fig. 4, according to the embodiment, the shift signal and the enable signal may be automatically loaded to the first register 40 in the chip start stage, so that the shift signal is directly provided to the shift register 10, and the enable signal is provided to the patch unit 20, thereby implementing power-on self-repair and improving efficiency.

Further, referring to fig. 5, in the corresponding embodiment, an updated enable signal may be generated in the sleep mode, and the patch unit 20 may be controlled, so that the output signal may have different configurations in the sleep mode, and the mode may be automatically switched.

In the embodiments provided in the present application, the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the methods according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

Claims

1. A repair circuit for an analog signal, comprising:

a shift register;

2. A repair circuit according to claim 1, wherein the patch unit comprises:

3. The repair circuit according to claim 1, wherein the shift register and the plurality of patch units constitute a patch module;

4. The repair circuit according to claim 3, wherein the plurality of signal lines of the same functional module are distributed into a plurality of groups, and the plurality of patch modules corresponding to the plurality of groups correct input signals of the plurality of signal lines of the same functional module.

5. A repair circuit according to claim 3, wherein a plurality of patch modules are connected to each group, a plurality of said patch modules being cascaded, the input signal being fed to one patch module after processing by the next patch module.

6. The repair circuit of claim 1, further comprising:

the first register is connected with the shift register and the patch unit;

7. The repair circuit of claim 1, further comprising:

8. A method for repairing an analog signal, the method being applied to a circuit for repairing an analog signal according to any one of claims 1 to 7, the method comprising:

9. The method of claim 8, further comprising:

10. The method of claim 8, wherein the repair circuit further comprises: the first register is connected with the shift register and the patch unit; a read circuit coupled to the first register, the method further comprising: