CN117149510A - Processing system and processing method for cyclic redundancy check - Google Patents
Processing system and processing method for cyclic redundancy check Download PDFInfo
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Abstract
The invention provides a processing system and a processing method for cyclic redundancy check, comprising the following steps: the bus module is configured to acquire data to be tested of the external equipment, wherein the data to be tested comprises a data stream to be checked and set parameters; the cyclic redundancy check channel selection module comprises a plurality of cyclic redundancy check interface channels, wherein the cyclic redundancy check interface channels are configured to be in communication connection with the bus module, and the cyclic redundancy check interface channels corresponding to the cyclic redundancy check interface channels are selected according to the set parameters to receive data to be tested; and the computing module is configured to be in communication connection between the cyclic redundancy check channel selection module and the bus module, processes the data to be tested, generates a corresponding cyclic redundancy check code, and transmits the cyclic redundancy check code to external equipment through the bus module. The processing system and the processing method for cyclic redundancy check provided by the invention are used for improving the problem of high hardware resource consumption in the process of calculating the CRC code.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a processing system and a processing method for cyclic redundancy check.
Background
Cyclic redundancy check (Cyclic Redundancy Check, CRC) is a fast algorithm that generates a short fixed-bit check code from data such as network packets or computer files. CRC is used primarily to detect or check errors that may occur after data transmission or storage. The existing integrated circuit has the problems of high hardware resource consumption and the like in the process of calculating the CRC code. Therefore, there is a need for improvement.
Disclosure of Invention
The invention aims to provide a processing system and a processing method for cyclic redundancy check, which are used for solving the problem of high hardware resource consumption in the process of calculating CRC (cyclic redundancy check) codes.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides a processing system for cyclic redundancy check, which comprises:
the bus module is configured to acquire data to be tested of the external equipment, wherein the data to be tested comprises a data stream to be checked and set parameters;
the cyclic redundancy check channel selection module comprises a plurality of cyclic redundancy check interface channels, wherein the cyclic redundancy check interface channels are configured to be in communication connection with the bus module, and the cyclic redundancy check interface channels are selected to correspond to the setting parameters to receive the data to be tested; and
the computing module is configured to be in communication connection between the cyclic redundancy check channel selection module and the bus module, processes the data to be tested, generates a corresponding cyclic redundancy check code, and transmits the cyclic redundancy check code to the external equipment through the bus module.
In an embodiment of the present invention, the crc interface channels are configured to independently configure configuration parameters thereof, and the configuration parameters of different crc interface channels are independent of each other.
In an embodiment of the present invention, the calculation module is configured to process the data stream to be checked according to the configuration parameter in the crc interface channel, so as to generate a corresponding crc.
In an embodiment of the present invention, the calculation module is configured to reorder the data stream to be checked according to the configuration parameter to generate a byte sequence to be checked.
In an embodiment of the present invention, the calculation module is further configured to perform bitwise exclusive-or processing on the byte sequence to be checked according to a historical result or a cyclic redundancy initial value, generate an exclusive-or byte sequence, and perform remainder calculation processing on the exclusive-or byte sequence to generate a remainder calculation result.
In an embodiment of the present invention, the computing module is further configured to select a corresponding stage number according to the number of bytes of the data stream to be checked, so as to generate a stage number result.
In an embodiment of the present invention, the calculation module is further configured to process the number of levels according to a historical processing result or a cyclic redundancy initial value to generate a cyclic redundancy sequence.
In an embodiment of the invention, the calculation module is further configured to reorder the cyclic redundancy sequence according to the configuration parameters to generate an intermediate cyclic redundancy sequence.
In an embodiment of the invention, the calculation module is further configured to process the intermediate cyclic redundancy sequence according to the configuration parameters to generate a cyclic redundancy check code.
The invention also provides a processing method of cyclic redundancy check, which comprises the following steps:
the bus module acquires data to be tested of external equipment, wherein the data to be tested comprises a data stream to be checked and set parameters;
the cyclic redundancy check channel selection module selects a corresponding cyclic redundancy check interface channel according to the setting parameters so as to transmit the data to be tested to the calculation module;
the computing module processes the data to be tested to generate a corresponding cyclic redundancy check code;
the computing module transmits the cyclic redundancy check code to the external device through the bus module.
As described above, the processing system and the processing method for cyclic redundancy check provided by the invention can realize independent computation of cyclic redundancy check codes in multiple channels by adopting a mode of multiplexing computation modules in multiple channels, effectively save the cost of hardware circuit resources, support configuration parameters of cyclic redundancy in any combination, and have strong universality. Meanwhile, different configuration parameters are pre-configured in the bus module, so that the calculation efficiency can be effectively improved.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a cyclic redundancy check processing system according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for processing cyclic redundancy check according to an embodiment of the present invention;
fig. 3 is a flowchart of step S30 in fig. 2.
In the figure: 100. a bus module; 200. a cyclic redundancy check channel selection module; 300. a computing module; 400. an external device; 210. cyclic redundancy check interface channels; 310. an integrated circuit board; 320. and calculating a chip.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, the present invention provides a processing system for cyclic redundancy check, which can be applied to a scenario in which a check code generated after data transmission or storage has a problem, namely, a cyclic redundancy check (Cyclic Redundancy Check, CRC) scenario. The processing system for cyclic redundancy check may include a bus module 100, a cyclic redundancy check channel selection module 200, and a calculation module 300. The bus module 100 may be configured to be communicatively connected to the external device 400 to obtain a data stream to be verified that needs to be verified. The external device 400 may include, but is not limited to, a host or a main processor (CPU), etc. The crc interface channel selection module 200 may be configured to be communicatively coupled to the bus module 100 to select a corresponding crc interface channel 210 based on the data stream to be checked. The calculation module 300 may be configured to be communicatively connected to the bus module 100 and the crc channel selection module 200, and the calculation module 300 may be configured to receive the data stream to be checked from the crc interface channel 210, process the data stream to generate a corresponding processing result, and send the processing result to the external device 400 through the bus module 100.
Referring to fig. 1, in one embodiment of the present invention, a bus module 100 is configured to receive/transmit data with a bus of an external device 400. The bus of the external device 400 may be a data transmission bus (Advanced Peripheral Bus, APB). APBs are mainly used for connections between low bandwidth peripheral peripherals, such as UART, 1284, etc. The bus architecture of the APB is an APB bridge, and the characteristics of the APB bridge comprise two clock period transmission, and the control logic is simple. The bus module 100 may be configured to receive data to be measured of the external device 400.
In one embodiment of the present invention, the data to be tested may include a data stream to be checked and set parameters. The data stream to be checked may be data from the external device 400 that requires CRC checking. The setting parameter may be a preset setting parameter of the external device 400 when the data stream to be checked needs to be subjected to CRC check. The setting parameters may include a CRC polynomial expression (POLY), a width of the polynomial expression, a cyclic redundancy initial value, a cyclic redundancy exclusive or value, whether the data stream to be checked is flipped by bit, whether the cyclic redundancy check code is flipped by bit, and whether the data stream to be checked is flipped in byte order.
In one embodiment of the invention, the CRC polynomial expression may be a CRC-generated polynomial. For example, a full polynomial corresponding to a 32-bit cyclic redundancy check (CRC 32) code may be expressed as CRC 32=x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x+1. The expression corresponding to CRC32 is 0x04C11DB7. Since the CRC polynomial highest order bits are all 1, the highest order bits are uniformly ignored, and POLY of CRC32 can be represented as 0x04C11DB7. The width of the polynomial expression may be the highest order bits of the polynomial expression, which corresponds to the bit width of the cyclic redundancy check code. The cyclic redundancy initial value may be an initial value when the CRC is calculated. The crc exclusive-or value may be a final value that is output after the crc check code is exclusive-ored with the initial value. Whether the data stream to be checked is flipped in bits may be whether each byte in the input data stream to be checked is flipped in bit order. Whether the cyclic redundancy check code is turned over according to the bits may be whether the data of the whole calculation result is turned over according to the bits before the calculation result of the cyclic redundancy check code is subjected to exclusive or processing. Whether the data stream to be checked is byte-order flipped may be whether the incoming data stream to be checked is byte-order flipped within a word (4 bytes).
In an embodiment of the present invention, the bus module 100 may be further configured to preset different configuration parameters of the cyclic redundancy, so as to achieve the purpose of enabling the cyclic redundancy calculation quickly, and save the configuration time. In this embodiment, the configuration parameters may include, but are not limited to, CRC32-autosar, CRC16-ccitt, CRC16-xmodem, CRC16-modbus, CRC16_dnp, CRC16_x25, CRC16_usb, CRC16_maxim, CRC16_ibm, CRC8_maxim, CRC8_rohc, CRC8_itu, CRC8, CRC5_usb, and the like. For example, the polynomial expression POLY of CRC8 may be expressed as crc8=x 8 +x 5 +x 4 +1. The polynomial expression POLY of CRC16 may be expressed as crc8=x 16 +x 15 +x 2 +1。
Referring to FIG. 1, in one embodiment of the present invention, the cyclic redundancy check channel selection module 200 may be mounted on an integrated circuit board 310 of the computing module 300 and configured to be communicatively coupled to the computing module 300. The cyclic redundancy check channel selection module 200 may include a plurality of cyclic redundancy check interface channels 210. Each crc interface channel 210 may be configured to be communicatively coupled between the bus module 100 and the computing module 300. The configuration parameters within the different crc interface channels 210 may be independent of each other. The configuration parameters in the different crc interface channels 210 may be the same or different, so as to be independent. For example, a user may configure configuration parameters in different crc interface channels 210 to be the same parameters to support verification of multiple identical data paths, so as to satisfy the redundancy design. The different crc interface channels 210 may operate independently and not affect each other. The crc lane selection module 200 may be configured to select a corresponding crc interface lane 210 to receive data under test according to a set parameter of the data under test. The crc interface channel 210 may automatically transmit its internal configuration parameters to the computing module 300 for processing. When one crc interface channel 210 communicates with the computing module 300, the remaining crc interface channels 210 cannot communicate with the computing module 300. In the process of performing CRC calculation by the calculation module 300, it is ensured that the calculation module 300 only communicates with a single CRC interface channel 210, so as to prevent the remaining CRC interface channels 210 from affecting the same.
Referring to FIG. 1, in one embodiment of the invention, the calculation module 300 may be configured to be communicatively coupled between the cyclic redundancy check channel selection module 200 and the bus module 100. The calculation module 300 may process the data to be tested according to the configuration parameters to generate a corresponding cyclic redundancy check code. The computing module 300 may transmit the cyclic redundancy check code to the external device 400 through the bus module 100. The computing module 300 may include an integrated circuit board 310 and a computing chip 320. The computing chip 320 may be configured to be communicatively coupled to the integrated circuit board 310. The integrated circuit board 310 may be configured to communicatively couple with the cyclic redundancy check interface channel 210, the bus module 100, respectively.
In one embodiment of the present invention, the calculation module 300 may be specifically configured to reorder the data stream to be verified according to the configuration parameters to generate the byte sequence to be verified. For example, the calculation module 300 may reorder the data stream to be verified according to the parameter of whether the data stream to be verified is Byte-order flipped in the configuration parameters, so as to generate the reordered Byte sequence byte_pre to be verified. For 32-bit high and low byte data, byte order flipping may be to swap the high 16-bit bytes with the low 16-bit bytes.
In one embodiment of the present invention, the calculation module 300 may be further specifically configured to perform bitwise exclusive-or processing on the byte sequence to be verified according to a historical result or a cyclic redundancy initial value, generate an exclusive-or byte sequence, and perform remainder calculation processing on the exclusive-or byte sequence to generate a remainder calculation result. For example, the calculation module 300 may be configured to determine whether a history processing RESULT (CRC_LAST_RESULT) exists. When the calculation module 300 determines that there is a history result, the action performed may be to bitwise exclusive-or the history result with the byte sequence to be checked to generate an exclusive-or byte sequence (crc_data_pre). When the calculation module 300 determines that there is no history processing result, the action performed may be performing bitwise exclusive-or processing on the cyclic redundancy initial value and the byte sequence to be checked to generate an exclusive-or byte sequence.
In one embodiment of the invention, the bitwise exclusive OR process may be represented as computing the corresponding bits of the two operational components bitwise in accordance with certain rules. For example, 0^0 =0, 0 ζ1=1, 1 ζ0=1, 1 ζ1=0. I.e. the corresponding bits have the same value, resulting in 0, and the different result is 1.2≡6=4, because 2 is represented as binary 0010,6 as binary 0110, and the two are only the third bit, the end result is 0100, i.e. 4. The a may be expressed as a bitwise exclusive or processed symbol. The history processing RESULT may be a cyclic redundancy check code generated by the calculation module 300 after processing the LAST data stream to be checked up to the present time, denoted as crc_last_result, where the crc_last_result may be bitwise xored with the byte sequence to be checked. Of course, if the data stream to be checked to be processed at this time is the first data, the calculation module 300 does not process the corresponding data stream to be checked before that, that is, there is no history processing RESULT at this time, then the cyclic redundancy initial value needs to be used as crc_last_result, and bitwise exclusive-or processing is performed on the cyclic redundancy initial value and the byte sequence to be checked.
In one embodiment of the invention, the calculation module 300 may be further specifically configured to perform a remainder calculation process on the exclusive-or byte sequence to generate a remainder calculation result. For example, the input definition of the remainder matrix of the remainder calculation process may be expressed as a remain_in, the output definition may be expressed as a remain_out, and the input and output are 32-bit data. remain_out= {1' b0, remain_in [31:1] } ({ 32{ remain_in [0] }) POLY }. The maximum number of stages of the remainder matrix is 32 stages. The first stage input is an exclusive-or byte sequence (crc_data_pre), the output of the first stage may be referred to as the input of the second stage, the output of the second stage may be referred to as the input of the third stage, and so on, and finally a corresponding remainder calculation result is generated.
In one embodiment of the invention, 1' b0 may be represented as a 1bit 0 signal. Both the remain_in and the remain_out are 32-bit (binary data) data, the most significant bit being bit31 and the least significant bit being bit0. The remain_in [31:1] may be represented as bit31, bit30, bit29, and..bit 1 of remain_in for a total of 31 bits. The remaining_in [0] may be represented as the least significant bit0 of the remaining_in. { } may be expressed as stitching new data, for example, {1'b0, remain_in [31:1] } may be expressed as stitching a 32-bit new data, the highest bit (bit 31) of this new data being 1' b0, bit30 being remain_in [31], bit29 being remain_in [30], and so on, bit0 being bit30 being remain_in [1]. {32{ remain_in [0] } can be expressed as a 32-bit copy of the one bit of remain_in [0] and concatenated into a 32-bit data.
In one embodiment of the present invention, the calculation module 300 may be further specifically configured to select a corresponding number of stages according to the number of bytes of the data stream to be checked, so as to generate a stage result. For example, the remainder of the corresponding number of stages (number of stages=n×8) may be selected according to the number of bytes n, n=1, 2, 4 of the data stream to be checked, and output from the calculation module 300 is used as the number of stages result (remaining_final).
In one embodiment of the present invention, the calculation module 300 may be further specifically configured to process the series result to generate a cyclic redundancy sequence according to the historical processing result or the cyclic redundancy initial value. For example, when the history RESULT or the cyclic redundancy initial value is acquired, the history RESULT or the cyclic redundancy initial value may be regarded as crc_last_result, and the crc_last_result may be bitwise xored with the number of levels RESULT to generate a cyclic redundancy sequence (crc_pre), which may be expressed as crc_pre=remain_final.
In one embodiment of the present invention, the calculation module 300 may be further specifically configured to reorder the cyclic redundancy sequence according to the configuration parameters to generate an intermediate cyclic redundancy sequence (crc_pre_o). For example, the calculation module 300 may reorder the cyclic redundancy sequence according to the parameter of whether the data stream to be checked is flipped by bit in the configuration parameter to generate the reordered intermediate cyclic redundancy sequence.
In one embodiment of the present invention, the calculation module 300 may be further specifically configured to process the intermediate cyclic redundancy sequence according to the configuration parameters to generate a cyclic redundancy check code (crc_result). For example, the computation module 300 may perform a bitwise exclusive-or process on the intermediate cyclic redundancy sequence according to a cyclic redundancy exclusive-or value (CRC_XOR) in the configuration parameters to generate the latest cyclic redundancy check code, which may be expressed as
^
CRC_RESULT＝CRC_Pre_O CRC_XOR。
Referring to fig. 2, the present invention further provides a processing method for cyclic redundancy check, which can be applied to the processing system in the above embodiment. The processing method can comprise the following steps:
step S10, a bus module acquires data to be tested of external equipment, wherein the data to be tested comprises a data stream to be tested and setting parameters, and the setting parameters comprise a polynomial expression, the width of the polynomial expression, a cyclic redundancy initial value, a cyclic redundancy exclusive-or value, whether the data stream to be tested is turned over according to bits, whether a cyclic redundancy output value is turned over according to bits and whether the data stream to be tested is turned over in byte order;
step S20, a cyclic redundancy check channel selection module selects a corresponding cyclic redundancy check interface channel according to the set parameters so as to transmit data to be tested to a calculation module for processing;
step S30, a calculation module processes the data to be tested to generate a corresponding cyclic redundancy check code;
and S40, the calculation module returns the cyclic redundancy check code to the external equipment through the bus module.
In one embodiment of the present invention, when step S10 is performed, specifically, the bus module 100 is configured to receive/transmit data with the bus of the external device 400, thereby receiving the data to be measured of the external device 400. The data to be tested may include the data stream to be checked and the set parameters. The data stream to be checked may be data from the external device 400 that requires CRC checking. The setting parameter may be a preset setting parameter of the external device 400 when the data stream to be checked needs to be subjected to CRC check. The setting parameters may include a CRC polynomial expression (POLY), a width of the polynomial expression, a cyclic redundancy initial value, a cyclic redundancy exclusive or value, whether the data stream to be checked is flipped by bit, whether the cyclic redundancy check code is flipped by bit, and whether the data stream to be checked is flipped in byte order.
In one embodiment of the present invention, when performing step S20, in particular, the cyclic redundancy check channel selection module 200 may be mounted on the integrated circuit board 310 of the computing module 300 and configured to be communicatively connected to the computing module 300. The cyclic redundancy check channel selection module 200 may include a plurality of cyclic redundancy check interface channels 210. Each crc interface channel 210 may be configured to be communicatively coupled between the bus module 100 and the computing module 300. The configuration parameters within the different crc interface channels 210 may be independent of each other. The configuration parameters in the different crc interface channels 210 may be the same or different, so as to be independent. For example, a user may configure configuration parameters in different crc interface channels 210 to be the same parameters to support verification of multiple identical data paths, so as to satisfy the redundancy design. The different crc interface channels 210 may operate independently and not affect each other. The crc lane selection module 200 may be configured to select a corresponding crc interface lane 210 to receive data under test according to a set parameter of the data under test. The crc interface channel 210 may automatically transmit its internal configuration parameters to the computing module 300 for processing.
Referring to fig. 3, in one embodiment of the present invention, when step S30 is performed, specifically, step S30 may include the following steps:
step S31, reordering the byte order of the data stream to be checked according to whether the byte order is overturned or not so as to generate a byte sequence to be checked;
step S32, judging whether a history processing result exists, if so, performing bitwise exclusive OR processing on the history processing result and the byte sequence to be checked to generate an exclusive OR byte sequence, and if not, performing bitwise exclusive OR processing on the cyclic redundancy initial value and the byte sequence to be checked to generate an exclusive OR byte sequence;
step S33, performing remainder calculation processing on the exclusive-or byte sequence to generate a remainder calculation result;
step S34, selecting a corresponding series according to the number of bytes of the data stream to be checked to generate a series result;
step S35, processing the series result according to the history processing result or the cyclic redundancy initial value to generate a cyclic redundancy sequence;
step S36, according to whether the cyclic redundancy output value is turned over according to the bit, the cyclic redundancy sequence is reordered to generate an intermediate cyclic redundancy sequence;
and step S37, processing the intermediate cyclic redundancy sequence according to the cyclic redundancy exclusive OR value to generate a cyclic redundancy check code.
In one embodiment of the present invention, when performing step S31, in particular, the calculation module 300 may be specifically configured to reorder the data stream to be verified according to the configuration parameters to generate the byte sequence to be verified. For example, the calculation module 300 may reorder the data stream to be verified according to the parameter of whether the data stream to be verified is Byte-order flipped in the configuration parameters, so as to generate the reordered Byte sequence byte_pre to be verified.
In one embodiment of the present invention, when step S32 is performed, in particular, the calculation module 300 may be further specifically configured to perform bitwise exclusive-or processing on the byte sequence to be checked according to a history result or a cyclic redundancy initial value, generate an exclusive-or byte sequence, and perform remainder calculation processing on the exclusive-or byte sequence to generate a remainder calculation result. For example, the calculation module 300 may be configured to determine whether a history processing RESULT (CRC_LAST_RESULT) exists. When the calculation module 300 determines that there is a history result, the action performed may be to bitwise exclusive-or the history result with the byte sequence to be checked to generate an exclusive-or byte sequence (crc_data_pre). When the calculation module 300 determines that there is no history processing result, the action performed may be performing bitwise exclusive-or processing on the cyclic redundancy initial value and the byte sequence to be checked to generate an exclusive-or byte sequence.
In one embodiment of the present invention, when step S33 is performed, in particular, the calculation module 300 may be further specifically configured to perform a remainder calculation process on the exclusive or byte sequence to generate a remainder calculation result. For example, the input definition of the remainder matrix of the remainder calculation process may be expressed as a remain_in, the output definition may be expressed as a remain_out, and the input and output are 32-bit data. remain_out= {1' b0, remain_in [31:1] } ({ 32{ remain_in [0] }) POLY }.
In one embodiment of the present invention, when performing step S34, the calculation module 300 may be further specifically configured to select a corresponding number of stages according to the number of bytes of the data stream to be checked, so as to generate a stage result. For example, the remainder of the corresponding number of stages (number of stages=n×8) may be selected according to the number of bytes n, n=1, 2, 4 of the data stream to be checked, and output from the calculation module 300 is used as the number of stages result (remaining_final).
In one embodiment of the present invention, when performing step S35, in particular, the calculation module 300 may be further configured to process the number of stages according to the historical processing result or the cyclic redundancy initial value to generate the cyclic redundancy sequence. For example, when the history RESULT or the cyclic redundancy initial value is acquired, the history RESULT or the cyclic redundancy initial value may be regarded as crc_last_result, and the crc_last_result may be bitwise xored with the number of levels RESULT to generate a cyclic redundancy sequence (crc_pre), which may be expressed as crc_pre=remain_final.
In one embodiment of the present invention, when performing step S36, in particular, the calculation module 300 may be further configured to reorder the cyclic redundancy sequence according to the configuration parameters to generate an intermediate cyclic redundancy sequence (crc_pre_o). For example, the calculation module 300 may reorder the cyclic redundancy sequence according to the parameter of whether the data stream to be checked is flipped by bit in the configuration parameter to generate the reordered intermediate cyclic redundancy sequence.
In one embodiment of the present invention, when performing step S37, in particular, the calculation module 300 may be further configured to process the intermediate cyclic redundancy sequence according to the configuration parameters to generate a cyclic redundancy check code (crc_result). For example, the calculation module 300 may perform a bitwise exclusive-or process on the intermediate cyclic redundancy sequence according to a cyclic redundancy exclusive-or value (crc_xor) in the configuration parameter to generate the latest cyclic redundancy check code, which may be expressed as crc_result=crc_pre_o Σr.
In one embodiment of the present invention, when performing step S40, the calculation module 300 may be configured to be communicatively connected between the cyclic redundancy check channel selection module 200 and the bus module 100. The calculation module 300 may process the data to be tested according to the configuration parameters to generate a corresponding cyclic redundancy check code. The computing module 300 may transmit the cyclic redundancy check code to the external device 400 through the bus module 100.
Therefore, in the scheme, by adopting a mode of a multi-channel multiplexing calculation module, the multi-channel independent calculation of the cyclic redundancy check code can be realized, the cost of hardware circuit resources is effectively saved, the configuration parameters of cyclic redundancy in any combination can be supported, and the universality is strong. Meanwhile, different configuration parameters are pre-configured in the bus module, so that the calculation efficiency can be effectively improved.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (10)
1. A processing system for cyclic redundancy check, comprising:
the bus module is configured to acquire data to be tested of the external equipment, wherein the data to be tested comprises a data stream to be checked and set parameters;
the cyclic redundancy check channel selection module comprises a plurality of cyclic redundancy check interface channels, wherein the cyclic redundancy check interface channels are configured to be in communication connection with the bus module, and the cyclic redundancy check interface channels are selected to correspond to the setting parameters to receive the data to be tested; and
the computing module is configured to be in communication connection between the cyclic redundancy check channel selection module and the bus module, processes the data to be tested, generates a corresponding cyclic redundancy check code, and transmits the cyclic redundancy check code to the external equipment through the bus module.
2. The processing system for cyclic redundancy check as claimed in claim 1, wherein the cyclic redundancy check interface channels are configured to independently configure their configuration parameters, and wherein the configuration parameters of different ones of the cyclic redundancy check interface channels are independent of each other.
3. The processing system of claim 1, wherein the computing module is configured to process the data stream to be checked according to configuration parameters within the crc interface channel to generate a corresponding crc code.
4. A processing system for cyclic redundancy check as claimed in claim 3, wherein the calculation module is configured to reorder the data stream to be checked according to the configuration parameters to generate a byte sequence to be checked.
5. The processing system of cyclic redundancy check as claimed in claim 4, wherein the calculation module is further configured to perform bitwise exclusive-or processing on the byte sequence to be checked according to a history result or a cyclic redundancy initial value, generate an exclusive-or byte sequence, and perform remainder calculation processing on the exclusive-or byte sequence to generate a remainder calculation result.
6. The cyclic redundancy check processing system of claim 5, wherein the computing module is further configured to select a corresponding number of stages based on the number of bytes of the data stream to be checked to generate a result of the number of stages.
7. The cyclic redundancy check processing system of claim 6, wherein the computing module is further configured to process the progression results based on historical processing results or cyclic redundancy initial values to generate a cyclic redundancy sequence.
8. The processing system for cyclic redundancy check of claim 7, wherein the computing module is further configured to reorder the cyclic redundancy sequences according to the configuration parameters to generate intermediate cyclic redundancy sequences.
9. The system of claim 8, wherein the computing module is further configured to process the intermediate cyclic redundancy sequence according to the configuration parameters to generate a cyclic redundancy check code.
10. A method for processing cyclic redundancy check, comprising:
the bus module acquires data to be tested of external equipment, wherein the data to be tested comprises a data stream to be checked and set parameters;
the cyclic redundancy check channel selection module selects a corresponding cyclic redundancy check interface channel according to the setting parameters so as to transmit the data to be tested to the calculation module;
the computing module processes the data to be tested to generate a corresponding cyclic redundancy check code;
the computing module transmits the cyclic redundancy check code to the external device through the bus module.
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| CN111897674A (en) * | 2020-08-07 | 2020-11-06 | 上海富瀚微电子股份有限公司 | Cyclic redundancy check circuit IP (Internet protocol) check verification system and method |
| CN114443348A (en) * | 2021-12-23 | 2022-05-06 | 湖南毂梁微电子有限公司 | Configurable CRC code calculation system |
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| CN111247516A (en) * | 2019-03-11 | 2020-06-05 | 深圳市大疆创新科技有限公司 | Circuit structure, system-on-chip (SoC) and data processing method |
| CN111897674A (en) * | 2020-08-07 | 2020-11-06 | 上海富瀚微电子股份有限公司 | Cyclic redundancy check circuit IP (Internet protocol) check verification system and method |
| CN114443348A (en) * | 2021-12-23 | 2022-05-06 | 湖南毂梁微电子有限公司 | Configurable CRC code calculation system |
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