JPH0365663A - Signal pulse width measuring circuit - Google Patents

Abstract

PURPOSE:To enable measurement without use of a high frequency clock exceeding a signal to be measured by delaying the signal to be measured with a delay circuit to alter a delay value of the delay circuit by an AND signal between an output signal of the delay circuit and the signal to be measured. CONSTITUTION:A signal 6 to be measured is branched off at a point D and one part thereof is inputted into a delay circuit 2 having a delay data 13 '0' and a delay signal 10 delayed by time X is outputted. A signal 10 and a signal 6 are inputted into an AND gate 1 and an AND signal 11 is outputted. Counts 12 '1' is outputted by counting the signal 11 with a counting circuit 4. This value 12 '1' is converted with a decoder 3 into a delay data 13 'D1' of the circuit 2. Then, when the signal 6 is inputted into the circuit 2, a signal 10 delayed by time 2X is outputted. After repeating this operation, the signal 11 is no longer outputted and thus, a measuring pulse width can be determined as product of counts 9 at the end of counting and a delay value of the circuit 2 per one counting.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal pulse width measuring circuit that measures the pulse width of a fixed periodic oscillation signal.

[Conventional technology]

FIG. 3 is a block diagram of a conventional signal pulse width measuring circuit. In the figure, (5) is an oscillator, (4> is an oscillator (
5) is a counting circuit that measures the number of count pulses that can be counted within the pulse width of the oscillation signal under test using the signal output from 1 as a count pulse; (6) is the signal under test;
) is the clock pulse output from the oscillator (5), (8
) is the count value of the counting circuit (4), and (9) is the count value at the end of counting.

FIG. 4 is a timing chart showing the signal under test (6), clock pulse (7), and count value (8) of the circuit of FIG.

Next, the operation will be explained using FIG. 4. The signal under test (6) is input to the count circuit (4) as a count enable signal, and the clock pulse (7) output from the oscillator (5) is input to the count circuit (4) as a clock signal.
The count circuit (4) calculates the number of pulses of the oscillator (5) or rano clock pulse (7) that are input to the count circuit (4) within the pulse width of the signal under test (6) by inputting the signal to the count circuit (4). Output as value (8). The measurement pulse width is obtained as the product of the count value (9) at the end of counting and the period of the clock pulse (7). [Problem to be solved by the invention] The conventional signal pulse width measurement circuit is configured as described above. Therefore, there was a problem in that the pulse width could not be measured without using a high frequency clock higher than the signal under test.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a signal pulse width measuring circuit that can measure pulse width without using a higher frequency clock than the signal under test.

[Means to solve the problem]

The signal pulse width measuring circuit according to the present invention includes a delay circuit that delays a signal under test based on delay data, and an AND signal that generates an AND signal of the output signal of the delay circuit and the signal under test.
a circuit, a count circuit that counts its output signal,
It is equipped with a data conversion circuit that converts the count value into delayed data.

[Effect]

The signal pulse width measuring circuit of the present invention delays the signal under test using a delay circuit, and changes the delay value of the delay circuit using an AND signal between the output signal of the delay circuit and the signal under test, thereby determining the pulse width of the signal under test. The pulse width of the measurement signal is obtained from the cumulative delay value at the time of delay by the width.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram of a signal pulse width measuring circuit. In the figure, (4>, (6), (7), and (9)) are the same as those shown in the conventional example in Figure 3, so their explanations are omitted. (2)
is a delay circuit that delays the signal under test (6) based on delay data, OO is a delay signal, (1> is an AND gate that generates an AND signal of the signal under test (6) and delay signal αQ, and (3) is Delay data 0 inputting the count value 0 of the count circuit (4) to the delay circuit (2)
The decoder that converts αυ to αυ is an AND signal.

FIG. 2 is a timing chart of the signal under test (6), the delayed signal QO1AND signal (b), the count value (6), and the delay data 0 of the circuit shown in FIG.

Next, the operation will be explained with reference to the timing chart in FIG. 2 and the table below.

The signal under test (6〉) branches at point D shown in Figure 1, and one side is a delay circuit (2) with delay data (to) 0'''.
, and a delayed signal QO delayed by time X is output. The delay signal 00 and the signal under test (6) are input to the AND gate (1), and an AND signal 0υ is output. By counting this AND signal 0 in a count circuit (4), a count value @゛1'' is output.

This count value υ'''1'' is converted into delay data Qi''''D1'' of the delay circuit (2) by the decoder (3).Next, when the signal under test (6) is input to the delay circuit (2), A delay signal QO delayed by time 2X is output. By repeating this operation, AND signal a is no longer output, and the measurement pulse width is the count value at the end of counting (9) and the delay circuit (2) per count.
It is obtained as the product of the delay value of

〔Effect of the invention〕

As described above, the present invention includes a delay circuit that delays a signal under test based on delay data, an AND circuit that generates an AND signal of its output signal, the signal under test, and the signal under test, and the AND circuit. A output from
Equipped with a count circuit that counts ND signals and a data conversion circuit that converts the count value into delay data that is input to the delay circuit, it has the effect of being able to measure pulse width without using a higher frequency than the signal under test. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a signal pulse width measuring circuit according to an embodiment of the present invention, FIG. 2 is a timing chart showing various signals of FIG. 1, and FIG. 3 is a block diagram of a conventional signal pulse width measuring circuit. FIG. 4 is a timing chart showing signals of each part in FIG. 3. In the figure, (1) is an AND gate, (2) is a delay circuit, (3) is a decoder, (4) is a count circuit, (
6) is the signal to be measured, (9) is the count value at the end of counting, 00 is the delay signal, 0 is the AND signal, (2) is the count value, and (to) is the delay data. In addition, in FIG. 1, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A signal pulse width measuring circuit that measures the pulse width of a fixed period oscillation signal includes a delay circuit that delays the signal under test based on delay data, and an AND circuit that generates an AND signal of the output signal of the signal under test and the signal under test. , a count circuit that counts the AND signal, and a data conversion circuit that converts the count value into delay data to be input to the delay circuit; 1. A signal pulse width measuring circuit, characterized in that the pulse width of a signal under test is measured based on a corresponding delay value.