JPH0364960A - Semiconductor device - Google Patents

Abstract

PURPOSE:To shorten a semiconductor device of this design in delay time of signal transmission by a method wherein the source and the drain of a MOS transistor and the base of a bipolar transistor are formed of a diffusion layer and a silicide layer. CONSTITUTION:N<->-type source and drain regions 109 and a P-type base region 112 are formed. The emitter region of a bipolar transistor is opened. Then, N<+>-type source and drain regions 111, an N-type collector diffusion layer 113, and the P-type source and drain regions of a P-type MOS transistor are provided. Then, a silicide layer 117 is deposited on the surfaces of the N<+>-type source and drain regions 111, the P-type base region 112, the N-type collector diffusion layer 113, a gate electrode 108, and an emitter electrode 115, and a high melting point metal film which does not react with silicon is removed through a wet etching method. The width of the emitter electrode 115 is so determined as not to enable a short circuit to occur between the silicide layer 117 of the P-type base region 112 and an N-type emitter region 116. Thereafter, an interlaminar insulating film, a wiring metal film, and the like are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor layer, and particularly to the structure of a Bi-CMOS type semiconductor device in which a bipolar transistor and a CMO3MOS type transistor are formed on one substrate.

[Conventional technology]

An example of a conventional B1-CMOS type semiconductor device will be explained in the order of manufacturing steps with reference to the drawings.

First, as shown in FIG. 3 (a), a P-type semiconductor substrate 301
After forming an N-type buried layer 302 and a P-type buried layer 303, an epitaxial layer with a thickness of about 2.0 μm is provided, and an N-type well 304 and a P-type well 3 are formed by ion implantation.
A field oxide film 306 is formed by a zero-order selective oxidation method to form a gate oxide film 30 with a thickness of 10 to 30 nm.
7. A polycrystalline silicon gate electrode 308, an N- type source/drain region 309, and a P-type base region 312 are provided. Thereafter, a side wall 310 using a silicon oxide film is formed on the side surface of the gate electrode 308, and an N+ type source/drain region 311, an N type collector diffusion layer 313, and a P layer (not shown in the figure) are formed by ion implantation. Type source/
Form a drain region.

Next, as shown in FIG. 3(b), an oxide film 3 for insulation between the eyebrows is shown.
14, the emitter region is opened, an emitter electrode 315 of polycrystalline silicon is provided, and N is further formed by diffusion.
A mold emitter region 316 is provided, and then a glabella insulating film,
A metal wiring film and the like are formed to complete the Bi-CMOS type semiconductor device.

[Problem to be solved by the invention]

The conventional Bi-CMOS semiconductor device described above is CM
The purpose of this is to shorten the signal transmission delay time compared to an OS type semiconductor device. However, in recent years, with the progress in miniaturization of devices, the source/drain regions of MOS transistors and the base regions of bipolar transistors have become shallower, and the delay time has decreased due to an increase in parasitic resistance components generated in these parts. It is becoming increasingly difficult to shorten the length.

[Means to solve the problem]

A semiconductor device of the present invention includes a MOS transistor having a source train consisting of a diffusion layer and a silicide layer;
A bipolar transistor having a base made of a diffusion layer and a silicide layer is provided on the same substrate.

〔Example〕

The present invention will be explained with reference to the drawings.

FIGS. 1A to 1C are cross-sectional views of a semiconductor chip for explaining a first embodiment of the present invention. The manufacturing steps will be explained below in order.

First, as shown in FIG. 1(a), impurities are introduced onto the entire surface of a P-type semiconductor substrate 101 made of silicon and having a resistivity of 10 to 14 Ω·0, forming a highly doped N-type buried layer 102 and a highly doped N-type buried layer 102. A P-type buried layer 103 is provided. Next, an N-type epitaxial layer with a resistivity of about 1 Ω·0 is formed to a thickness of 1 to 2 μm, and after an N-type well 104 and a P-type well 105 are provided, a field oxide film 106 is formed by selective oxidation. Next, a gate oxide film 107 is formed to a thickness of 10 to 30 nm, and a gate electrode 108 is provided in a desired region using a polycrystalline silicon film doped with impurities and having a thickness of 300 to 400 nm. Next, impurities are introduced by ion implantation,
N-type source/drain region 109 and P-type base region 1
form 12.

Next, as shown in FIG. 1(b), a silicon oxide film 110 was deposited to a thickness of 150 to 300 nm using the CVD method, and then arsenic was introduced into the entire surface in a zero-order manner to open the emitter region of the bipolar transistor. After forming a polycrystalline silicon film with a thickness of ~300 nm, dry etching is performed using a patterned photoresist film 120 to form an emitter electrode 115. At this time, by making the etching of the polycrystalline silicon film somewhat isotropic, no etching residue of the polycrystalline silicon film is left on the side surfaces of the gate electrode 108, etc.

Next, as shown in FIG. 1(C), the photoresist film 12
0 on the emitter electrode 115, the oxide film 110 is removed.
By performing dry etching anisotropically until the silicon surface is exposed, the oxide film 110 is left only on the side surfaces of the gate electrode 108 and the lower part of the emitter electrode.
The photoresist film on the emitter electrode 115 is removed, and impurities are introduced by ion implantation to form an N4'' type source.
Drain region 111. An N-type collector diffusion layer 113, a P-type MO3 (not shown) and a P-type source/drain region of the transistor section are formed.

After this, a high melting point metal film such as titanium is applied by sputtering.
By stacking the layers to a thickness of 0 to 1100 nm and performing high-temperature heat treatment, the exposed portions of the silicon surface, namely the N''' type source/drain region 111, the P type base region 112, the N type collector diffusion M113, and Gate electrode 1
08, silicide layer 11 on the surface of the emitter electrode 115
7 is formed, and the high melting point metal film that has not reacted with silicon is removed by wet etching.

Since an N-type emitter region 116 is formed under the emitter electrode 115 by thermal diffusion of arsenic, the P-type base region 1
It is necessary to determine the width of the emitter electrode 115 so that the 12 silicide layers 117 and the N-type emitter region 116 are not short-circuited. Thereafter, a Bi-CMOS type semiconductor device is completed by forming an interlayer insulating film, a metal film for wiring, etc.

As described above, according to the first embodiment, the source/drain of a MOS type transistor and the base of a bipolar transistor having the silicide layer 117 on the diffusion layer are obtained, so that the parasitic resistance component can be reduced.

FIGS. 2(a) and 2(b) are cross-sectional views of a semiconductor chip for explaining a second embodiment of the present invention.

In FIG. 2(a), 201 is a P-type semiconductor substrate, 20
2 is an N-type buried layer, 203 is a P-type buried layer, 204
205 is an N type well, 205 is a P type well, 206 is a field oxide film, 207 is a gate oxide film, and 212 is a P type base region. A portion of the gate oxide film 207 corresponding to the emitter region is removed by etching, and the polycrystalline silicon film is removed by etching.
The layers are laminated to a thickness of 0 to 200 nm using the CVD method. Arsenic was added by ion implantation to I x 1016~3 x 10”a
After introducing a titanium silicide film into the polycrystalline silicon film at a concentration of toms/c112, a titanium silicide film is deposited to a thickness of 150 to 200 nm by sputtering to form a gate electrode 20 with a polycide structure.
8 and an emitter electrode 215 are formed. After that, N+ type source/drain regions 211, N type collector diffusion M21
3. Introduce impurities into P-type source/drain regions (not shown). An N-type emitter region 216 is formed under the emitter electrode 215 by thermal diffusion of arsenic.

Next, as shown in FIG. 2(b), 150
The oxide film stacked to a thickness of ~300 nm is removed by anisotropic etching to leave the oxide film 210 only on the side surfaces of the gate electrode 208 and emitter electrode 215, and then the same process as in the first embodiment described above is carried out. A silicide layer 217 is formed on the exposed silicon surface.

In this second embodiment, in addition to being able to reduce the parasitic resistance components of the source/drain and base as in the first embodiment, it is also possible to reduce the parasitic resistance components of the collector of the bipolar transistor, so that the delay time can be further reduced. It has the advantage of being short.

〔Effect of the invention〕

As explained above, according to the present invention, by forming the source/drain of a Mos transistor and the base of a bipolar transistor from a diffusion layer and a silicide layer, parasitic resistance components are reduced, so that signal transmission delay time can be shortened. effective.

[Brief explanation of drawings]

FIGS. 1(a) to (c) and FIGS. 2(a) and (b) are cross-sectional views of a semiconductor chip for explaining the first and second embodiments of the present invention, and FIG. 3(a) , (b) are cross-sectional views of a semiconductor chip for explaining a conventional example. 101.201,301...P-type semiconductor substrate, 102
．． 202,302-N type buried layer, 103.203,
303-P type buried layer, 104°204.304-N
Type well, 105,205°305 ・P type well, 1
06,206.306...Field oxide film, 107
,207.307...gate oxide film, 108,208
．． 308...Gate electrode, 109.309...N-
Type source/drain, 110.210...Oxide film, 3
10...Side wall, 111,211,311・
...N+ type source/drain region, 112, 212, 3
12...P type base region, 113,213.313.
...N-type collector diffusion layer, 115,215.315...
- Emitter electrode, 116, 216, 316... N-type emitter region, 117, 217... Silicide layer, 12
0...Photoresist film.

Claims (1)

[Claims] 1. A semiconductor device comprising, on the same substrate, a MOS type transistor having a source and drain made of a diffusion layer and a silicide layer, and a bipolar type transistor having a base made of a diffusion layer and a silicide layer.