JPH0362528A - Heterojunction field-effect transistor - Google Patents
Heterojunction field-effect transistorInfo
- Publication number
- JPH0362528A JPH0362528A JP19760989A JP19760989A JPH0362528A JP H0362528 A JPH0362528 A JP H0362528A JP 19760989 A JP19760989 A JP 19760989A JP 19760989 A JP19760989 A JP 19760989A JP H0362528 A JPH0362528 A JP H0362528A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- layers
- heterojunction
- type
- gaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims description 2
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 3
- 229910001423 beryllium ion Inorganic materials 0.000 abstract description 2
- 238000000137 annealing Methods 0.000 abstract 1
- 239000012141 concentrate Substances 0.000 abstract 1
- 239000006251 one-dimensional electron gas Substances 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はへテロ接合型電界効果トランジスタに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a heterojunction field effect transistor.
従来のへテロ接合型トランジスタは、第２図に示すよう
に、半絶縁性ＧａＡｓ基板１の上にアンドープＧａＡｓ
層２及びｎ＋型ＡｆｆｌＧａＡｓ層８を順次積層して設
けた後、ゲート電極形成方向と直交するようにｎ１型Ａ
、、ＲＧａＡｓ層８を０．３μｍ未満の幅で等間隔にエ
ツチングして除去し、２次元電子ガス層を空間的に分離
して１次元的にしていた。A conventional heterojunction transistor, as shown in FIG.
After layer 2 and n+ type AfflGaAs layer 8 are sequentially laminated, an n1 type A layer is formed perpendicular to the gate electrode formation direction.
,, the RGaAs layer 8 was etched and removed at regular intervals with a width of less than 0.3 μm, thereby spatially separating the two-dimensional electron gas layer and making it one-dimensional.
上述した従来のへテロ接合型電界効果トランジスタは細
い溝（１次元性をもたせるには０．３μｍ以下の幅でき
れば０．１μｍ以下の幅にする必要がある。）をつくる
ため非常な微細加工を必要とするという問題点がある。The conventional heterojunction field effect transistor described above requires extremely fine processing to create a narrow groove (to achieve one-dimensionality, the width must be 0.3 μm or less, preferably 0.1 μm or less). The problem is that it is necessary.
また、通常０．３μｍ以下に形成するゲート電極を段差
を横切って形成するためゲート電極を形成するためのり
ソグラフィ（エツチングを用いてつくる場合は均一なエ
ツチング〉技術が難しいという欠点がある。In addition, since the gate electrode, which is usually formed to a thickness of 0.3 μm or less, is formed across a step, there is a drawback that the lithography (uniform etching when using etching) technique for forming the gate electrode is difficult.
本発明のへテロ接合型電界効果トランジスタは、半絶縁
性半導体基板上に設けたアンドープＧａＡｓＪｉｌと、
前記アンドープＧａＡｓ層内に一定間隔で配列して埋込
んだｐ型ＧａＡｓ層と、前記アンドープＧａＡｓ層の上
に設けてヘテロ接合を形成するｎ型ＡｌＧａＡｓ層と、
前記ｎ型Ａ、ＲＧａＡｓ層の上に設けて前記ｐ型ＧａＡ
ｓ層と交差するように設けたゲート電極とを有する。The heterojunction field effect transistor of the present invention includes undoped GaAsJil provided on a semi-insulating semiconductor substrate,
a p-type GaAs layer arranged and buried at regular intervals in the undoped GaAs layer; an n-type AlGaAs layer provided on the undoped GaAs layer to form a heterojunction;
The p-type GaA is provided on the n-type A and RGaAs layers.
It has a gate electrode provided to intersect with the s-layer.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）、（ｂ）は本発明の一実施例の平面図及び
Ａ−Ａ’線断面図である。FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA' of an embodiment of the present invention.
第１図（ａ）、（ｂ）に示すように、半絶縁性ＧａＡｓ
基板上にアンドープＧａＡｓ層２を形成する。次に、ア
ンドープＧ ａ Ａ ｓ １ｇ ２の表面にＢｅイオン
を選択的にイオン注入して不純物濃度１×１０１６〜５
×１０１７ｃ１１すのｐ型ＧａＡｓ層３ａ、３ｂ、３ｃ
を幅０．１〜０．５μｍの短冊状に形成し且つ間隔０．
１〜０．５μｍで等間隔に配列して表面より０．０５〜
０．５μｍの深さに埋込み、しかる後アニールして活性
化し、ＭＢＥ法によりｎ＋型Ａ Ｉ Ｇ ａ Ａ ｓ
Ｍ ４を成長させてヘテロ接合を形成し、２次元電子ガ
ス層を界面に形成する。次に、ｎ＋型ＡｆｆｌＧａＡｓ
層４の上に短冊状のｐ型ＧａＡｓ層３ａ、３ｂ、３ｃと
直交するようにゲート電極５を形成する。ここで、ｐ型
ＧａＡｓ層３ａ、３ｂ、３ｃの上方のアンドープＧａＡ
ｓ層２のポテンシャルはｐ型ＧａＡｓ層３ａ、３ｂ、３
ｃに近いので、ｐ型Ｇ ａ Ａ ｓ層３ａとｐ型ＧａＡ
ｓ層３ｂの中間又はｐ型ＧａＡｓ層３ｂとｐ型ＧａＡｓ
層３ｃとの中間のアンドープＧａＡｓ層２のポテンシャ
ルよりも高く２次元電子ガス層はｐ型Ｇ ａ Ａ ｓ層
３ａ。As shown in FIGS. 1(a) and (b), semi-insulating GaAs
An undoped GaAs layer 2 is formed on the substrate. Next, Be ions are selectively implanted into the surface of the undoped GaAs 1g2 to give an impurity concentration of 1×1016 to 5
×1017c11 p-type GaAs layers 3a, 3b, 3c
is formed into a rectangular shape with a width of 0.1 to 0.5 μm and an interval of 0.
Arranged at equal intervals of 1 to 0.5 μm and 0.05 to 0.05 μm from the surface.
It is buried to a depth of 0.5 μm, then annealed and activated, and then formed into an n+ type A I G a A s by MBE method.
Grow M4 to form a heterojunction and form a two-dimensional electron gas layer at the interface. Next, n+ type AfflGaAs
A gate electrode 5 is formed on the layer 4 so as to be perpendicular to the strip-shaped p-type GaAs layers 3a, 3b, and 3c. Here, undoped GaA above the p-type GaAs layers 3a, 3b, 3c
The potential of the s-layer 2 is the same as that of the p-type GaAs layers 3a, 3b, 3
Since it is close to c, the p-type GaAs layer 3a and the p-type GaA
The middle of the s layer 3b or the p-type GaAs layer 3b and the p-type GaAs
The two-dimensional electron gas layer has a potential higher than that of the undoped GaAs layer 2 between the layer 3c and the p-type GaAs layer 3a.
３ｂの中間領域及びｐ型ＧａＡｓ層３ｂ、３ｃの中間領
域のへテロ接合界面に集中して形成される。また、ｐ型
ＧａＡｓ層３ａ、３ｂ、３ｃの濃度を高くし、且っヘテ
ロ接合との距離を近づけることでｐ型ＧａＡｓ層３ａ、
３ｂ、３ｃの上方の２次元電子ガス層を全くなくすこと
も可能である。3b and the heterojunction interface between the p-type GaAs layers 3b and 3c. In addition, by increasing the concentration of the p-type GaAs layers 3a, 3b, and 3c and shortening the distance to the heterojunction, the p-type GaAs layers 3a, 3b, and 3c are
It is also possible to completely eliminate the two-dimensional electron gas layer above 3b and 3c.
なお、ｐ型ＧａＡｓ層はアンドープＧａＡｓ層に短冊状
の溝を設け、溝の内部にｐ型ＧａＡｓ層を成長させて形
成しても良い。Note that the p-type GaAs layer may be formed by providing a strip-shaped groove in the undoped GaAs layer and growing the p-type GaAs layer inside the groove.
以上説明したように本発明はへテロ接合下に配列して設
けたｐ型ＧａＡｓ層を設けることでヘテロ接合界面の電
子を１次元的にできる効果がある。As explained above, the present invention has the effect of making the electrons at the heterojunction interface one-dimensional by providing the p-type GaAs layer arranged below the heterojunction.
また、電子ガス層が１次元的になることで移動度、飽和
速度の向上が可能となり高速のデバイスが実現できる。Furthermore, since the electron gas layer becomes one-dimensional, mobility and saturation speed can be improved, and a high-speed device can be realized.
第１図（ａ）、（ｂ）は本発明の一実施例の平面図及び
Ａ−Ａ’線断面拡大図、第２図は従来のへテロ接合型電
界効果トランジスタの断面図である。
１・・・半絶縁性ＧａＡｓ基板、２・・・アンドープＧ
ａＡｓ層、３ ａ 、 ３ ｂ 、 ３ ｃ−・ｐ型Ｇ
ａＡｓ層、４−ｎ＋型ＡＪＧａＡｓ層、５・・・ゲート
電極、６・・・ソース電極、７・・・ドレイン電極、８
・・・ｎ＋型Ａ、１２ＧａＡｓ層。FIGS. 1(a) and 1(b) are a plan view and an enlarged cross-sectional view taken along the line A-A' of an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a conventional heterojunction field effect transistor. 1... Semi-insulating GaAs substrate, 2... Undoped G
aAs layer, 3 a, 3 b, 3 c-/p type G
aAs layer, 4-n+ type AJGaAs layer, 5... gate electrode, 6... source electrode, 7... drain electrode, 8
...n+ type A, 12GaAs layer.
Claims (1)
、前記アンドープＧａＡｓ層内に一定間隔で配列して埋
込んだｐ型ＧａＡｓ層と、前記アンドープＧａＡｓ層の
上に設けてヘテロ接合を形成するｎ型ＡｌＧａＡｓ層と
、前記ｎ型ＡｌＧａＡｓ層の上に設けて前記ｐ型ＧａＡ
ｓ層と交差するように設けたゲート電極とを有すること
を特徴とするヘテロ接合型電界効果トランジスタ。An undoped GaAs layer provided on a semi-insulating semiconductor substrate, a p-type GaAs layer arranged and buried at regular intervals in the undoped GaAs layer, and an n-type GaAs layer provided on the undoped GaAs layer to form a heterojunction. type AlGaAs layer and the p-type GaAs layer provided on the n-type AlGaAs layer.
A heterojunction field effect transistor characterized by having a gate electrode provided to intersect with the s-layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19760989A JP2811780B2 (en) | 1989-07-28 | 1989-07-28 | Heterojunction field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19760989A JP2811780B2 (en) | 1989-07-28 | 1989-07-28 | Heterojunction field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0362528A true JPH0362528A (en) | 1991-03-18 |
| JP2811780B2 JP2811780B2 (en) | 1998-10-15 |
Family
ID=16377319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19760989A Expired - Fee Related JP2811780B2 (en) | 1989-07-28 | 1989-07-28 | Heterojunction field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2811780B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2660296C1 (en) * | 2017-02-20 | 2018-07-05 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) | Method for making semiconductor device |
-
1989
- 1989-07-28 JP JP19760989A patent/JP2811780B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2660296C1 (en) * | 2017-02-20 | 2018-07-05 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) | Method for making semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2811780B2 (en) | 1998-10-15 |
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