JPH0362023B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a dynamic memory using silicide as a conductor layer of a memory cell capacitor or a transfer gate electrode.

In order to self-align the manufacturing process of dynamic memory, a method is often used in which polysilicon is used as the material for each electrode and a surface insulating film is created by thermal oxidation to achieve mutual insulation.

Although polysilicon is doped with impurities, its resistance value is considerably higher than that of metals, so it has been proposed to use silicide, particularly molybdenum silicide, as a conductor, which can significantly reduce this resistance value.

In JP-A-54-132176, the underlying silicon oxide film is etched using undoped molybdenum silicide as a mask, and then the exposed silicon surface is oxidized by ordinary high temperature oxidation at about 1000°C. are doing. At this time, an oxide film is also formed on the surface of the molybdenum silicide, so the second layer electrodes are insulated from each other by the oxide film on the silicide surface, allowing self-alignment of the CCD transfer electrodes.

On the other hand, when manufacturing an insulated gate field effect transistor, a method has also been proposed in which molybdenum silicide is doped with impurities in advance and contact with the semiconductor region is made by diffusion from the molybdenum silicide (Japanese Patent Application Laid-Open No. 1983-1999). (See Publication No. 121667).

When this doped silicide is applied to the above-mentioned self-alignment process, impurities in the silicide are removed from the oxide film under the cell or gate by annealing for diffusion from the silicide or subsequent treatment (annealing during ion implantation). spread inside,
In the case of an extremely thin oxide film, it may penetrate to the substrate side, or even if it does not, it will cause deterioration of device characteristics.

Therefore, the present invention aims to provide a method for manufacturing a dynamic memory by a self-alignment process in which doped silicide can be used as a conductor on an extremely thin dielectric film.

According to the present invention, this purpose is achieved by laminating a dielectric film for forming a capacitance and a conductor layer made of metal silicide containing impurities effective for the semiconductor on the surface portion of the semiconductor substrate surrounded by the field insulating film. After that, a part of the surface of the semiconductor substrate is exposed, and an oxidation treatment is performed in a humid atmosphere to form an oxide film that is thicker than that formed on the surface of the semiconductor substrate. A gate oxide film of a predetermined thickness is formed by performing oxidation treatment at a temperature higher than the oxidation treatment temperature in , and then a transfer electrode is formed spanning over the gate oxide film and the thick oxide film on the conductor layer. This is achieved by providing a method for manufacturing a dynamic memory characterized in that it includes a step.

Below, in explaining the embodiments of the present invention,
The present invention will be summarized and the principles utilized in the present invention will be explained.

That is, according to the present invention, a metal silicide containing an impurity that becomes an effective impurity for the semiconductor substrate or layer is used as the interconnection and electrode structure.

The metal silicide includes molybdenum (Mo),
Tungsten (W), tantalum (Ta), titanium (Ti), niobium (Nb), chromium (Cr), manganese (Mn), cobalt (Co) or nickel (Ni)
silicides or alloys of these metals can be used.

When the semiconductor substrate or layer is silicon, the effective impurities include donor impurities such as phosphorus (P) and arsenic (As), and acceptor impurities such as boron (B), and the concentration of the impurity in the metal silicide is applied. is 1×10 ²⁰ to 4×10 ²¹ [pieces/cm ³ ]. If the concentration is less than 1×10 ²⁰ [particles/cm ³ ], the accelerated oxidation effect of the impurity-containing metal silicide layer as described below cannot be obtained, and if it exceeds 4×10 ²¹ [particles/cm ³ ], During heat treatment, the impurity-containing metal silicide layer may peel off from the surface of the semiconductor substrate or layer, or when the impurity-containing metal silicide layer is used as a gate electrode of an MIS type device, impurities may penetrate the gate insulating film. The particles may reach the semiconductor substrate or layers, making it difficult to manufacture the MIS type device or causing deterioration in operating characteristics.

The oxidation characteristics of the metal silicide are shown in FIG.
In the figure, the solid line a is the oxidation property of molybdenum silicide containing phosphorus (phosphorus concentration 1×10 ²¹ [pieces/cm ³ ]) according to the present invention, and the solid line b is the molybdenum silicide containing no effective impurities (non-doped). The solid line c shows the oxidation property of silicon crystal with plane orientation (100). The oxidizing atmosphere was a humid oxygen atmosphere at a temperature of 750 [°C].

As is clear from FIG. 1, the phosphorus-containing molybdenum silicide according to the present invention has an oxidation rate eight times or more compared to silicon crystal, and the phosphorus-containing molybdenum is applied to interconnects, etc. In this case, it is easy to form an oxide insulating layer on the surface.

It is also clear that metal silicides, including the phosphorus-containing molybdenum silicide, have lower resistance than semiconductors such as polycrystalline silicon, and from this point of view, metal silicides are used for interconnect electrodes, etc. It is advantageous to use.

Such an effective impurity-containing metal silicide can be formed, for example, by a reactive sputtering method.

When forming the molybdenum silicide layer containing phosphorus, a silicon plate or piece or a molybdenum plate or piece is inserted as a target material together with the semiconductor substrate to be processed into a sputtering apparatus, and then a sputtering gas is introduced into the sputtering apparatus. For example, sputtering treatment is performed by introducing a reactive gas such as phosphine (PH ₃ ) together with argon (Ar). This reactive sputtering process forms a molybdenum silicide layer containing phosphorus on the semiconductor substrate to be processed.

The present invention will be explained in detail below using examples.
FIG. 2 is produced according to an embodiment of the invention. 1 shows a dynamic random access memory element composed of one transistor and one capacitive element.

In the figure, 21 is a P-type silicon substrate, 22
23a and 23b are gate insulating films, 24 is a transfer gate electrode, and 25 is a field insulating film.
N ⁺ type drain region, 26 is the electrode of the capacitive element, 2
7 is an oxide film, 28 is a phosphorus silicate glass layer, 29
is the word line.

In order to realize such a structure, first, the silicon substrate 2 defined by the field insulating film 22 is
A gate insulating film 23a is formed on the surface of the gate insulating film 23a, and then a molybdenum silicide layer containing phosphorus is selectively deposited on the gate insulating film 23a to a thickness of about 4000 Å to form an electrode 26. Thereafter, using the electrode 26 as a mask, the gate insulating film 23a is selectively removed to expose the surface of the silicon substrate 21 in the transfer gate forming area and the drain region forming area.

Next, in a steam atmosphere at 750 [℃],
After heat treatment for about 100 minutes, the surface thickness of the electrode 56
An oxide film 27 having a thickness of about 2000 Å is formed. At this time, the exposed surface of the silicon substrate 21 has a thickness of 250 to 300 Å.
An oxide film of about 100% is formed.

Next, heat treatment is carried out in a dry oxygen atmosphere at 900 [°C] to form a film with a thickness of 350 [Å] on the silicon substrate 51.
Then, an oxide film 23b for a transfer gate is formed. At this time, the oxide film 27 formed on the surface of the electrode 26 is densified.

Next, the oxide film 2 on the surface of the silicon substrate 21 is
A transfer gate electrode 24 made of, for example, polycrystalline silicon is formed extending from above 3b onto the oxide film 27 on the surface of the electrode 26.

Next, using the transfer gate electrode 24 and field insulating film 22 as a mask, phosphorus or arsenic is ion-implanted into the silicon substrate 51 to form an N ⁺ type drain region 25 and a bit line (extending in a direction perpendicular to the plane of the paper).

Next, a phosphorus silicate glass (PSG) layer 28 is deposited on the entire surface to a thickness of about 8000 Å, and the phosphorus silicate glass layer 28 on the transfer gate electrode 24 is
Selectively remove 8.

Thereafter, a metal layer such as aluminum is deposited over the entire surface, and the metal layer is selectively removed using photolithography to form word lines 29.

FIG. 3 shows another embodiment of the present invention, and shows another configuration of the memory element composed of one transistor and one capacitive element shown in FIG. 2.

In the same figure, 31 is a P-type silicon substrate, 32
33a and 33b are gate insulating films, 34 is a transfer gate electrode, and 35 is a field insulating film.
N ⁺ type drain region, 36 is the electrode of the capacitive element, 3
7 is an oxide film, 38 is a phosphorus silicate glass layer, 39
is a bit line, and 30 is a word line.

According to this embodiment, the electrode 36 of the capacitive element and the bit line electrode 39 are made of a molybdenum silicide layer containing impurities.

In order to realize such a structure, first the silicon substrate 3 defined by the field insulating film 32 is
A gate insulating film 33a is formed on one surface, and then molybdenum silicide containing phosphorus is selectively deposited on the gate insulating film 33a to a thickness of about 4000 Å to form an electrode 36. Thereafter, using the electrode 36 as a mask, the gate insulating film 33a is selectively removed to expose the surface of the silicon substrate 31 in the transfer gate forming area and the drain region forming area.

Next, a molybdenum silicide layer containing phosphorus is formed on the surface of the silicon substrate 31 in the drain region forming portion.
A bit line 39 is formed by selectively depositing a layer of about 4000 Å.

Next, in a steam atmosphere at 750 [℃],
A heat treatment is performed for about 100 minutes to form an oxide film 37 with a thickness of about 2000 Å on the surfaces of the electrodes 36 and 39. At this time, the exposed surface of the silicon substrate 31 has a thickness of 250~
An oxide film of about 300 Å is formed.

Next, in a dry oxygen atmosphere at 900 [℃]
After heating for 180 minutes, the thickness of the silicon substrate 61 was 350 mm.
A transfer gate oxide film 33b having a thickness of about [Å] is formed. At this time, the oxide film 37 formed on the surfaces of the electrodes 36 and 39 is densified, and phosphorus is diffused from the electrode 39 into the silicon substrate 31 to form an N ⁺ type drain region 35.

Next, the oxide film 33 on the surface of the silicon substrate 31 is
A transfer gate electrode 34 made of polycrystalline silicon, for example, is formed extending from above the oxide film 37 on the surface of the electrode 66.

Next, using the transfer gate electrode 34 and field insulating film 32 as a mask, ions of phosphorus or arsenic are implanted into the silicon substrate 31, and the temperature is further increased to 900°C.
The remainder of the N ⁺ type drain region 35 is formed by performing a heat treatment for about 20 minutes.

Next, a phosphorus silicate glass layer 38 is applied to the entire surface.
The phosphorus silicate glass layer 38 on the transfer gate electrode 34 is selectively removed.

Thereafter, a metal layer such as aluminum is deposited on the entire surface, and the metal layer is selectively removed using photolithography to form word lines 30.

FIG. 4 shows a further embodiment of the present invention, in which one transistor-1 shown in FIGS. 2 and 3 is shown.
3 shows another configuration of a memory element made up of a capacitive element.

In the figure, 41 is a P-type silicon substrate, 42
43 is a field insulating film, 43a and 43b are gate insulating films, 44 is a transfer gate electrode, and 45 is a
N ⁺ type drain region, 46 is the electrode of the capacitive element, 4
7 and 48 are oxide films, and 49 is a bit line.

In order to realize such a structure, first, the silicon substrate 4 defined by the field insulating film 42 is
A gate insulating film 43a is formed on the surface of the electrode 46, and then a molybdenum silicide layer containing phosphorus is deposited on the gate insulating film 43a to a thickness of about 4000 [Å].
form. Thereafter, using the electrode 46 as a mask, the gate insulating film 43a is selectively removed to expose the surface of the silicon substrate 41 in the transfer gate forming area and the drain region forming area.

Then, in a steam atmosphere at 750 [℃]
After heat treatment for about minutes, the surface of the electrode 46 has a thickness of 2000 mm.
An oxide film 47 having a thickness of about [Å] is formed. At this time, an oxide film with a thickness of about 250 to 300 Å is formed on the exposed surface of the silicon substrate 41.

Next, heat treatment is carried out in a dry oxygen atmosphere at 900 [°C], and a thickness of 350 [Å] is formed on the silicon substrate 41.
Then, an oxide film 43b for a transfer gate is formed. At this time, the oxide film 47 formed on the surface of the electrode 46 is densified.

Next, the oxide film 43 on the surface of the silicon substrate 41 is
A transfer gate electrode 44 made of a molybdenum silicide layer containing phosphorus is formed extending from above b onto the oxide film on the surface of the electrode 46. The thickness of the molybdenum silicide layer containing phosphorus is approximately 4000 Å.

Next, using the transfer gate electrode 44 and field insulating film 42 as a mask, phosphorus or arsenic is ion-implanted into the silicon substrate 41 to form an N ⁺ type drain region 45.

Next, heat treatment is performed again in a steam atmosphere at 750 [° C.] for about 100 minutes to form an oxide film 48 with a thickness of about 2000 [Å] on the surface of the transfer gate electrode 44. At this time, the phosphorus or arsenic ions implanted in the previous process are activated.

Next, the oxide film 48 is densified by heat treatment in a dry oxygen atmosphere at 900[° C.].

Next, the N ⁺
The oxide film on the surface of the type drain region 45 is removed. At this time, since the oxide film on the surface of the drain region 75 is extremely thin compared to the oxide film 48 on the surface of the transfer gate electrode 44, there is no need to use an etching mask, and it can be etched by immersion in an etching solution for a short time. The oxide film on the surface of the drain region 75 is removed.

Next, a metal layer such as aluminum is deposited on the entire surface, and the metal layer is selectively removed using photolithography to form a bit line 49.

One transistor according to the present invention as described above.
For a memory element composed of one capacitive element,
The oxide film disposed between the electrode of the capacitive element and the transfer gate electrode has sufficient thickness and density to obtain a sufficiently high dielectric strength voltage, thereby configuring a highly reliable semiconductor memory device. I can do it.

In addition, in the process of forming a memory element composed of one transistor and one capacitive element, the oxide film under the transfer gate is
Instead of using an oxide film formed at the same time as the oxide film formed on the surfaces of 6 and 46, it may be removed once and then oxidized again to form a film having a desired thickness.

As is clear from the above embodiments, according to the present invention, it is possible to easily oxidize the surface of metal silicide containing effective impurities as a material constituting interconnects and electrodes, and to provide interlayer insulation in multilayer wiring structures. layer or a surface protection insulating layer can be easily formed.

Further, the thickness of the oxide film formed on the surface of the interconnector and the electrode is sufficiently thick compared to the thickness of the oxide film formed on the surface of the semiconductor substrate at the same time. No etching mask is particularly required when attempting to selectively remove only the oxide film.

Furthermore, the metal silicide containing effective impurities has a lower resistivity than a semiconductor also containing effective impurities, and does not become a factor in reducing the switching speed of the semiconductor device. Therefore, according to the present invention, it is possible to realize a semiconductor device with higher performance through a simpler manufacturing process compared to a conventional semiconductor device in which interconnects and electrodes are constructed using semiconductor layers. can.

Incidentally, in the above embodiment, the interconnector and the electrode were constructed using a single metal silicide containing the desired impurity, but the metal silicide containing the impurity was formed with the polycrystalline semiconductor disposed below. Interconnects and electrodes may be formed by a laminate of .

[Brief explanation of drawings]

FIG. 1 is a curve diagram showing the oxidation characteristics of metal silicide containing effective impurities according to the present invention, and FIGS.
The figure is a sectional view of a dynamic memory according to each embodiment of the present invention. In the figure, 21, 31, 41... semiconductor substrate, 22, 32, 42... field insulating film, 2
6, 36, 46, 38', 56, 66, 69, 7
6, 74... Metal silicide cell electrode containing effective impurities, 27, 37, 47, 48... Oxide film.

Claims (1)

[Claims] 1. After laminating a dielectric film for capacitance formation and a conductor layer made of metal silicide containing an effective impurity for the semiconductor on the surface portion of the semiconductor substrate surrounded by the field insulating film, the surface portion of the semiconductor substrate is laminated. A part of the conductor layer is exposed and oxidized in a humid atmosphere to form an oxide film on the surface of the conductor layer, which is thicker than that formed on the surface of the semiconductor substrate, and then oxidized in the humid atmosphere. By performing oxidation treatment in a dry atmosphere at a temperature higher than the processing temperature, a gate oxide film of a predetermined thickness is formed, and the thick oxide film generated on the surface of the conductor layer by this oxidation treatment is densified. 1. A method of manufacturing a dynamic memory comprising the step of: forming a transfer electrode spanning over the gate oxide film and the thick oxide film on the conductor layer.