JPH0359898A - Random access memory - Google Patents

Abstract

PURPOSE:To simplify and rationalize a selection test by simultaneously selecting plural random access memory cells and compulsorily writing write data in a high level or a low level. CONSTITUTION:Address decoders 1-2a to 1-2c and 1-4a to 1-4d which simultaneously select plural random access memory cells 1-12a to 1-12l and a data generation means which compulsorily generates write data in the high level or the low level in spite of data given from the write circuits of the random access memory cells 1-12a to 1-12l are provided. Then, the random access memory cells 1-12a to 1-12l which are respectively adjacent are set in different data holding state. An inter-power leak current can be measured by the number of test patterns with less setting and in short time, and the selection test can be simplified and rationalized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a random access memory, and more particularly to a test circuit built into a semiconductor integrated circuit thereof.

[Prior Art] Conventionally, a random access memory built into a semiconductor integrated circuit generally has a circuit configuration shown in FIG. 4. This is the address according to address information 4-1.
Decoders 4-2 and 4-3 perform random access
The structure was such that any one of the memory cells 4-4a to 4-4i was selected and read and written from terminals 4-6 and 4-7.

[Problems to be Solved by the Invention] In the conventional random access memory described above, the address decoders 4-2 and 4-3 select the random access memory cell 4-4a according to the address information 4-1.
- Select any one of 4-4i and connect terminal 4-6
．． It has a structure that reads and writes from 4-7. Therefore, for every random access memory cell, 1(I
Writing the I+ and 170+1 values requires generating addresses and data for each memory cell and performing the writes individually.

This is because in a selection test using an LSI tester, when measuring leakage current between power supplies, taking into account the presence or absence of leakage between power supplies due to differences in data held in random access memory cells, random access current is Access Memory ◆ It takes a considerable number of tests and time to set the retained data on the cells, and there is a drawback that the selection test cannot be simplified or streamlined as expected.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a random access memory capable of solving the above-mentioned drawbacks and realizing simplification and rationalization of screening tests.

[Differences between the invention and the prior art] Compared to the conventional random access memory described above, the present invention uses a small number of test patterns to change the state in which data held in adjacent random access memory cells differs in a short period of time. That is, it has means for setting a so-called checkerboard pattern and its inverse checkerboard pattern.

[Means for Solving the Problems] The random access memory of the present invention has an address decoder that simultaneously selects a plurality of random access memory cells, and an address decoder that selects a plurality of random access memory cells at the same time. It has a data generation means that forcibly generates high-level or low-level write data regardless of the random access data that is adjacent to each other.
It is characterized by setting memory cells to different data retention states.

[Implemented η Rico Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and is an example assuming an integrated circuit including only a random access memory. This circuit diagram is drawn by extracting 3 horizontal bits and 4 vertical bits from a large number of random access memory cells.

First, a case in which this random access memory is normally used will be explained. At this time, as shown in Figure 5, the test signal input terminal! -6, 1-7° and 1-8 are fixed at high level, and test terminals 1-9, 1-10 are fixed at low level. As a result, address information 1-1 causes address decoders 1-2a to 1-2c to
Also, any one of the same address decoders 1-4
Any one of a to 1-4d is selected. Here, being selected means that the address decoder 1-2a
This means that all of the input terminals ~1-2c, 1-4a ~1-4d become high level inputs, and the output becomes low level.

Now, since the logic values of test signal input terminals ]-7 and 1-8 are high level, NAND gates 1-5a to 1-5
d is address decoder 1-4a to 1-4d
It becomes high level in response to the output. Also, inverter 1-
Any one of 3a to 1-30 is address decoder 1-2
It becomes high level upon receiving the outputs of a to 1-2c. Also test signal input terminal 1-9.1-10? , i is low level, so it is an N-channel transistor]-13a to 1-1
All 41 of 3f are non-conducting. For example, assume that the outputs of the NA to D games 1-5c and the inverter 1-3b are at high level. Then, N-channel transistors 1-11a and 1-11b become conductive, and terminal 2 of random access memory cell 1-12g becomes conductive.
becomes high level, and as shown in FIG. 3, N-channel transistor 3-1.3-2 in the internal circuit diagram of random access memory cell 1-12g also becomes conductive. Therefore, only random access memory cell 1-12g is selected, and "read j" to retrieve data from terminal 1-14.1-15, "write" to give data, and random access・Memory cell 1-
12g access.

Next, the case of setting data during a screening test will be explained.

This time, signals are externally applied to the test signal input terminals 1-6 to 1-10 at the timing shown in FIG. Sections I and 3 shown in FIG. 6 are the normal use states. Section 2 is the section in which data is set. First, in section 4, all outputs of address decoders 1-2, 1-4 become high level by setting terminals 1-6 to low level. Therefore, N channel transistors 1-11a to 1-1
All of 1f becomes non-conductive. Terminal 1 in the middle of section 4
-9 to high level, N-channel transistor 1-
13a, 1-13d, and 1-13e are made conductive, and the terminal 1 or 3 of the random access memory cell is brought to a low level.

However, since all of NAND game) 1-5a to 1-5d are low level outputs, no writing is performed.

Figure 7 shows terminal 1 of a random access memory cell.
A map of the retained data on the A side is shown, and the state in which no writing is performed in the map of A is defined as the retained data and is marked as "'X". In section 5, the terminals 1-7 are set to low level, and the NAND gates 1-5b and 1-5d are set to high level output. As a result, the N-channel transistors 3-1 and 3-2 shown in FIG. 3 become conductive, so that the random access memory cell 1-12d
, 1-12f, 1-12j, 1-12 included terminal 1 side and 1
-12e and 1-12 on the terminal 3 side are held at a low level, and the data holding state becomes state B shown in FIG. In section 6, terminals 1-9 are set to low level, terminals 1-10 are set to high level, and N-channel transistor 1-13 b
, 1-13 c.

1-13f are made conductive. As a result, terminals 1 or 3 of the random access memory cell become low level in the opposite combination to the previous one, but since terminals 1-7 and 1-8 are both high level, NAND gates 1-5a to 1- 5d all become low level outputs, and no writing is performed at this stage. In section 7, terminals 1-8 are set to low level, and NAN
The D gates 1-5a and 1-5c are set to high level output.

As a result, random access memory ◆Cells 1-12
a,! -12c, 1-12g, 1-12i on the terminal 3 side and 1-12b, l-12h on the terminal 1 side become low level, and the data holding state becomes state C shown in FIG. In other words, the data is held in a checkered pattern. Thereafter, section 8 is set to a write-inhibited state, and the leakage current between the power supplies is measured in this state.

Next, when a signal is applied to the test signal input terminals 1-6 to 1-10 at the timing shown in FIG. 8 using the same procedure as explained above, the interval 5 in FIG. In section 7, the data holding state becomes the data holding state shown in FIG. 6C, and at the timing shown in FIG.

Note that there is no problem in setting data to this checkered pattern even if the order of the previous settings is reversed, so random access memory cells to which data are not set are marked with an "X" in Figure 9. be. Then, in this state, the leakage current between the power supplies is measured for the second time.

FIG. 2 is a circuit diagram of a second embodiment of the present invention, and is an example assuming a random access memory built into a single-chip microcomputer. This circuit diagram is drawn by extracting 3 horizontal bits and 3 vertical bits from a large number of random access memory cells.

The difference from the first embodiment is that a new instruction for setting data to random access memory cells is provided.

That is, it is added to instructions such as addition, subtraction, and transfer.

First, a case in which this random access memory is normally used will be explained. At this time, the newly installed instruction is not input to the instruction decoder 2-1, and the signals 2-3 to 2-7 output from the signal generator 2-2 are used for other instructions shown at the left end in FIG. The logical values of the section, that is, the signals 2-3 to 2-7 remain at high level. As a result, address information 2-8 causes address decoders 2-9a to 2-
9c is also the same address decoder 2.
-10a to 2-10c is selected. Further, N-channel transistors 2-15a to 2-15f become non-conductive. Therefore, during random access, any one of the memory cells 2-14a to 2-141 is selected and data is retrieved from the terminal 2-16.2-17 (reading).
, performs a "write" that provides data.

Next, the case of setting data during a screening test will be explained.

This time, execute the newly created data setting command. There are two types of instructions: one for setting data in a checkerboard pattern, and the other for setting data in a checkerboard pattern. The premise is that this is a mechanism that can be executed in some way during the selection test. When the instruction decoder 2-1 decodes one of the two types of data setting instructions, the signal generator 2-2 generates signals 2-3 to 2-7 at the timing shown in FIG. First, in section 1, by setting the signal 2-3 to low level, the address decoders 2-9a to 2-9c and 2-10a to 2
All outputs of -10c become high level.

Therefore, N channel transistors 2-13a to 2-13
All of f become non-conductive. Signal 2- in the middle of section 1
6 to low level, P channel transistor 2-1
5a, 2-15d, 2-15e conduct, causing terminal 1 or 3 of the random access memory cell to go high. However, NAND gate 2-11 a ~
Since all of 2-11c are low level outputs, no writing is performed. Figure 12 shows random access memory.
This is a map of the data held on the terminal 1 side of the cell. In section 2 shown in FIG. 10, the signal 2-4 is set to low level, and the NAND gates 2-11a, 2-11c
The output of is set to high level. As a result, random access memory cells 2-14a, 2-14c, 2-
Terminal 1 side of 14g, 2-14i and 2-14b, 2-14
The holding state on the terminal 3 side of h becomes high level, and the data holding state becomes state B shown in FIG. In section 3, the signal 2-6 is set to high level, the signal 2-7 is set to low level, and P channel transistors 2-15b, 2-15c are activated.
, 2-15f is made conductive. As a result, random
Terminals 1 or 3 of the access memory cells go high in the opposite combination, but signals 2-4 . Since both 2-5 are at high level, NAND gates 2-11a to 2
-11c are all output at low level, and no writing is performed at this stage. In section 4, signals 2-5 are set to low level. As a result, the retention states of the terminal 3 side of random access memory cells 2-14d and 2-14f and the terminal 1 side of 2-14e become high level, and the data retention state becomes state C shown in FIG. Become. This results in a data retention state with a checkered pattern. In section 5, the writing is prohibited, and in this state, the leakage current between the power supplies is measured for the first time.

Next, execute the other data setting instruction.

When the signal generator 2-2 outputs the signals 2-3 to 2-7 at the timing shown in FIG. 11 using the same procedure as explained above, the data retention state is in the 13th state in section 2 shown in FIG.
In state B shown in the figure, in interval 4, the data holding state becomes state C shown in FIG. 13, which is a data holding state with a checkered pattern opposite to that set by the previous command. There is no problem in executing this instruction even if the order of executing the previous instruction is reversed.
In FIG. 13, random access memory cells that have not been set by the execution of this instruction are marked with "'X". Then, in this state, the leakage current between the power supplies is measured for the second time.

[Effects of the Invention] As explained above, the present invention has the advantage that multiple random
It has an address decoder that selects an access memory cell, and a data generation means that forcibly generates high-level or low-level write data regardless of the data given from the write circuit of the random access memory. Random access memory cells adjacent to each other can be set to different data retention states. For this reason, when measuring leakage current between power supplies in a screening test using an LSI tester, taking into account the presence or absence of leakage between power supplies due to differences in the data held in random access memory cells, it is necessary to・It is possible to set retained data for access memory cells with fewer test clicks and in a shorter time.
Simplification 2 of screening tests can be streamlined. Moreover, because random access memory cells can be set to have the data held in adjacent cells reversed, the failure detection rate is improved in the event that adjacent cells are short-circuited due to a manufacturing defect in the LSI. , the effect is great.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, FIG. 3 is an internal circuit diagram of a random access memory cell, and FIG. The figure shows a circuit diagram of a conventional random access memory, FIG. 5 shows a timing diagram of signals applied to the terminals when the first embodiment is normally used as a random access memory, and FIG. FIG. 7 is a timing diagram for setting the data retention state in a checkered pattern in the embodiment shown in FIG.・Map, Figure 8 is a timing diagram to set the data retention state in the reverse checkered pattern when the data retention state is set at the timing shown in Figure 6 in the first embodiment.
Figure 9 shows the random access memory process in which data settings are performed according to the timing diagram in Figure 8.
10 is a cell data map, and FIG. 10 is a timing chart of signals generated when an instruction to set the data retention state to a checkerboard pattern is executed in the second embodiment.
In this example, when the data retention state is set at the timing shown in Fig. 10, a timing chart of signals generated when an instruction is executed to set the data retention state to a checkered pattern, which is the opposite of that shown in Fig. 10, is shown. Fig. 12 shows the timing diagram of Fig. 10. 13 is a data map of a random access memory cell showing the process of data setting according to the diagram; FIG. 13 is a random access memory cell data map showing the process of data setting according to the timing diagram of FIG.
3 is a data map of access memory cells. 1-1.2-8.4-1...Address information, 1-
2 a-c, 1-4 a-d. 2-9a-c, 2-10a-c. 4-2.4-3...Address decoder, 1-
3a-c, 2-12a to C2 3-3, 3-4...Inverter, 1-5
a-d. 2-11 a-C・ ・ ・ ◆ ・ ・ ・ ・ N
AND gate, 1-6. 1-7. 1-8゜1-9.1-10...Test signal input terminal, 1-
11a-f. 1-13a-f. 2-13a-f. 3-1. 3-2゜4-5a~f ◆ ・ ・N channel transistor, 1-12a~ included, 2-14a~i. 4-4a~1...◆...Random access◆Memory cell, 1-14. 1-15. 2-16. 2-17°4-
6.4-7... Data output terminal, 2-1...
......Instruction decoder, 2-2...
...signal generator, 2-3. 2-4. 2-5°2-6.2-7... Control signal. 2-15a-f ・・P channel transistor.

Claims (1)

[Claims] An address decoder that simultaneously selects multiple random access memory cells, and a data generation means that forcibly generates high-level or low-level write data regardless of the data given from the write circuit of the random access memory. What is claimed is: 1. A random access memory comprising: setting adjacent random access memory cells to different data retention states.