JPH0358384A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To accelerate a data rate and to reduce the number of external terminals by autonomically updating an address inputted from a data input terminal with a prescribed clock, and stopping input/output and the update of the address with a prescribed control signal. CONSTITUTION:A leading address and a final address are supplied in time division via data input/output terminals D0-D7. Also, a serial input or output operation and the stepping operations of a leading X address buffer XBS and a leading Y address buffer YBS are stopped selectively according to a serial input/output enable signal, the inverse of SE. Furthermore, a comparative collation result between internal address signals x0-x7 and y0-y7 held and updated with the address buffers XBS and YBS and a final Y address buffer YBE with an address comparator AC is transmitted from a timing generation circuit TG as a final address detection signal, the inverse of EC, then, an interruption processing is requested.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory device, for example,
This technology is particularly effective when used in serial access memories used in file memories, communication pamphlet memories, etc. [Prior Art] There is a serial access memory used as a field memory of an image system. These serial access memories include address counters or pointers that are updated autonomously according to a serial clock signal adapted to the dot rate of, for example, a CRT (cathode ray tube) display device.

Serial access memory is described, for example, in "Nikkei Electronics" published by Nikkei McGraw-Hill, February 11, 1985, pages 219 to 239. [Problems to be Solved by the Invention] With the advancement of miniaturization and large-capacity technologies for semiconductor integrated circuits, the applications of the above-mentioned serial access memory have gradually expanded, and are now being used, for example, as file memory in computer systems and buffer memory for communications. has also come to be used.
However, if the conventional serial access memory described above is used as is for the above purpose, several problems will arise in terms of path control, the number of external terminals, etc. That is, when a serial access memory is used as a file memory or the like, for example, DMA (Dir-ec
tMemory Access) is accessed via the controller. As is well known, the DMA controller has a path management function and acquires or loses the path right every pass cycle. Therefore, serial access to the serial access memory by the DMA controller must be performed in accordance with the serial clock signal that matches the pass cycle, and control must be performed in accordance with the pass right of the serial access memory or the DMA controller for each cycle of the serial clock signal. There is. However, the conventional serial access memory as described above does not have a function to temporarily stop serial input/output operations when a DMA controller or the like loses the pass right. Therefore, in order to realize these functions, it is necessary to selectively use a serial clock signal with a relatively high frequency depending on the path right, or to manage addresses using a DMA controller or the like. As a result, speeding up of a system including the serial access memory is limited, and the amount of hardware such as a memory control unit that must be added outside the serial access memory increases.

On the other hand, conventional serial access memory as described above can autonomously update addresses internally, but cannot arbitrarily set the range of addresses to be serially accessed, and It also does not have a function to indicate, for example, an interrupt, that the serial input/output operation has been completed. Furthermore, if an attempt is made to externally specify the range of addresses to be serially accessed, the number of external terminals required will increase.

An object of the present invention is to provide a serial access memory or the like that can control serial input/output operations depending on the presence or absence of pass rights. Another object of the present invention is to provide a serial access memory or the like that can arbitrarily specify a range of serially accessed addresses and that can indicate that serial input/output operations of a series of stored data have been completed. The purpose is to reduce the number of terminals by θj.

The above and other objects and novel features of this invention include:
This will become clear from the description in this memorandum and the attached drawings. [Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

That is, an address buffer 7 that holds and autonomously updates the start address and end address to be serially accessed is provided in a serial access memory, etc., and all or part of these addresses are input via a data input terminal. supply on a time-sharing basis.

When the serial access memory or its controller does not have the pass right, the increment operation of the address buffer and the serial input/output operation are temporarily stopped. [Operation] According to the above-described means, the serial input/output operation of the serial access memory can be controlled according to the pass right while continuously supplying the serial clock signal, which is considered to have a relatively high frequency, so that the data rate can be reduced. can be made faster. Furthermore, the number of external terminals required for the serial access memory can be reduced, and the amount of hardware added outside the serial access memory for address management etc. can be reduced. Thereby, it is possible to increase the processing power of a system including a serial access memory and promote cost reduction.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a serial access memory to which the present invention is applied. The circuit elements constituting each block in the figure are formed on a single semiconductor substrate such as single-crystal silicon using known semiconductor integrated circuit manufacturing techniques, although this is not particularly limited. Although not particularly limited, the serial access memory of this embodiment is used as a file memory of a computer system and is accessed via a DMA controller, etc. and a memory control unit. The serial access memory has eight data input/output terminals D, although there are no particular limitations.
coupled to the data path via O-D7 and from a corresponding memory control unit, including but not limited to:
Activation control signals such as a chip enable signal CE, a write enable signal WE, a serial output enable signal SE (control signal) and an address center signal As, and a serial clock signal SC (clock signal) are supplied.
Among these, activation control signals such as the chip enable signal CE are selectively set to a low level when they are enabled, and the serial clock signal SC is formed at a predetermined period according to the access cycle of the data path. Ru. Serial access memory is not particularly limited, but may be 8x65
It has a storage capacity of 536 bits, and serially inputs or outputs storage data to a plurality of specified addresses in units of 8 bits in accordance with a serial clock signal SC. For this reason, serial access memory has an address cent cycle for specifying the address range to be accessed and its operating mode. That is, as will be described later, in the serial access memory, when the address set signal As is set to a low level prior to the chip enable signal CE, the address set cycle is set.
Data input/output terminals DO to D7 receive the first X address at the first falling edge of the address sent signal AS, and the final X address, first Y address, and final Y address at the three subsequent falling edges of the address sent signal AS. Addresses are supplied sequentially and in a time-division manner. The serial access memory is placed in a serial write mode when the write enable signal WE is set to a low level at the falling edge of the chip enable signal Cτ, and placed in a serial read mode when set to a high level. On the other hand, the serial access memory executes a predetermined serial writing or reading operation according to the serial clock signal SC when the serial input/output enable signal SE is set to a low level.

When a series of serial input or output operations for the specified address range is completed, the final address detection signal EA is set to low level, and the memory control unit is requested to perform interrupt processing. If the DMA controller temporarily loses the pass right during serial access, the memory control unit temporarily stops the serial write or read operation of the serial access memory by setting the serial input/output enable signal SE to high level. It can be stopped.

In FIG. 1, the basic structure of the serial access memory is a memory array MARY that occupies most of the surface of a semiconductor substrate. The memory array MARY includes a plurality of word lines arranged in parallel in the vertical direction, a plurality of complementary data lines arranged in parallel in the horizontal direction, and a grid at the intersections of these word lines and complementary data lines. It includes multiple memory cells arranged in a shape. Although not particularly limited, the word line that connects the memory array MARY is coupled to the X address decoder XD and is alternatively brought into a selected state.

The X address decoder XD is supplied with 8-bit internal address signals xO to x7 from the leading X address buffer XBS. The X address decoder XD decodes these internal address signals and selectively selects the corresponding word line of the memory array MARY at a high level. On the other hand, the complementary data lines connecting the memory array MARY are divided into eight groups, although this is not particularly limited. These complementary data line groups are selectively connected to common data #IAC DO to CD7 via eight corresponding sets of switch MOSFETs of column switch CSW.

The column switch CSW is a plurality of switch MOSFEs provided corresponding to each phase data line of the memory array MARY and divided into eight groups corresponding to the phase data line groups.
Contains T. The gates of these switch MOSFET groups are commonly coupled, and a corresponding data line selection signal is supplied from a Y address decoder YD. The respective switch MOSFET groups of the column switch CSW are turned on all at once by the corresponding data line selection signal being selectively set to high level, and the corresponding 8 switch MOSFETs of the memory array MARY are turned on.
Selectively connect the paired data lines and common data lines CDO to CD7. Although not particularly controlled, the Y address decoder YD is supplied with an 8-bit internal address signal yO to y7 from the leading Y address buffer YBS. Y address decoder Y
D decodes these internal address signals and selectively sets the corresponding data line selection signal to a high level.

The common data lines CDO to CD7 are coupled to the input terminals of the corresponding unit circuits of the read amplifier RA, and are also coupled to the output terminals of the corresponding unit circuits of the write amplifier WA. Each unit circuit of the read amplifier RA is commonly supplied with a timing signal φ'a from the tie generation circuit TG, and each output terminal is coupled to the input terminal of the corresponding unit circuit of the output buffer OB. Each unit circuit of the output bath sofa OB is commonly supplied with the tie-control signal φos from the tie-control generation circuit TG, and each output terminal is coupled to the corresponding data input/output terminal DO-D7. Each unit circuit of the read amplifier RA is selectively put into an operating state by setting the tie control signal φra to a high level. In this operating state, each unit circuit of the read buffer RA receives read signals output from the eight selected memory cells of the memory array MARY via the corresponding common data lines CDO-CD7, and outputs the read signals output from the output buffer OB. is transmitted to the corresponding unit circuit. These read signals are sent out from the corresponding unit circuit of the output bath sofa OB via the corresponding data input/output terminals DO to D7 on the condition that the timing signal ψOe is set to a high level.

On the other hand, each unit circuit of the write amplifier WA is commonly supplied with a tie signal φwa from the tie generation circuit TO, although this is not particularly limited, and each input terminal is connected to the corresponding unit circuit of the input buff ylB. Connected to the output terminal. The input terminal of each unit circuit of the input sofa IB is coupled to the corresponding data input/output terminal DO-D7.

Each unit circuit of the write amplifier WA receives a tie main signal φw.
When B is set to high level, it is selectively put into an operating state. In this operating state, each unit circuit of the write amplifier WA uses the write data input from the data input/output terminals DO to D7 through the corresponding unit circuit of the input buffer IB as a predetermined write signal, and uses the corresponding common data as a predetermined write signal. Write to the selected memory cell of memory array MARY via lines CDO to CD7.

In this embodiment, the output terminals of each unit circuit of the input buffer IB are not particularly limited, but the output terminals of the input buffer IB are not limited to the first QX address buffer XBS and the first uy address buffer YB.
coupled to the input terminal of the corresponding bit of S, and
It is coupled to the input terminals of the corresponding bits of the i&end X address buffer XBE and the i&end y address buffer YBH. The leading X address buffer XBS is supplied with tying signals φx3 and φxc from the tying generating circuit TG, and the leading Y address buffer YBS is supplied with tying signals φys and φyc of No. 8 tying signals. The final X address buffer 7XBE and the final Y address buffer YBE include
Tying signals φXe and φye are supplied, respectively. Although not particularly limited, the leading X address breadth signal φxs is temporarily set to a high level, so that the first Bint start X address
Take in 3a and keep it. In addition, by temporarily setting the tie control signal φxc to a high level, the above-mentioned
Count and amplify addresses sequentially. The X address held and updated by the first X address buffer XBS is
It is supplied as the internal address signal xQxx7 to the X address decoder XD, and is also supplied to the address comparison circuit A.
It is supplied to C. The i, sx address backer XBE is the tie main signal φ
By temporarily setting xe to a high level, the 8-bit final X address xea supplied via the data input/output terminals DO to D7 and the input bus sofa IB is taken in and held. These final X addresses are supplied to address comparison circuit AC. Similarly, the leading Y address buffer YBS is supplied via the data input/output terminals DO to D7 and the input buffer IB when the tie control signal ψys is temporarily set to a high level, although this is not particularly limited. 8 bits ahead [Fetch Y address ysa and hold it. In addition, by temporarily setting the timing signal φyC to a high level,
Count up the Y address above. The Y address held and updated by the first Y address buffer YBS is supplied as internal address signals yO to y7 to the Y address decoder YD and also to the address comparison circuit AC. The final Y address buffer YBE receives a tie main signal φy.
By temporarily setting the signal e to a high level, the final Y address yea of the 8th bin supplied via the data input/output terminal DO-07 and the input bus sofa IB is taken in and held. These final Y addresses are supplied to address comparison circuit AC.

The address comparison circuit AC is the first X address buffer XB.
Internal address signals xO to x held and updated by S
7 and the final X address and first Y address buffer YBS held by the final X address buffer XBE.
Internal address signals yO to y7 held and updated by
and the final Y address held by the final Y address buffer YBE are compared bit by bit.
As a result, when all bits of these addresses match, the output signal 6a is set to high level. The output signal ea of the address comparison circuit AC is supplied to the tie generation circuit TG, thereby setting the final address detection signal EA to a low level. The timing generation circuit TG receives a serial clock signal SC and a serial clock signal SC supplied as a start control signal from an external memory control unit.
Based on this, the various tying signals mentioned above are formed and supplied to each circuit. In addition, the output signal s of the address comparison circuit AC
a, the final address detection signal EA- is selectively shaped and supplied to the memory control unit. Although not particularly limited, the final address detection signal EA is transmitted from the memory control unit to the DMA controller, and an interrupt processing request is thereby made. FIGS. 2 and 3 show timing diagrams of one embodiment of the address cent cycle and serial read mode of the serial access memory of FIG. This section provides an overview of the operation of an example serial access memory and its characteristics. In the gJ2 diagram, the serial access memory is configured to perform an address set cycle by setting the chip enable signal CE to a low level and prior to the change of the chip enable signal GE to a low level and setting the address set signal As to a low level, although this is not particularly limited. It is said that As will be described later, the serial access memory receives the serial input/output enable signal SE after completing the address cent cycle.
The serial read or write mode is started when the signal is set to low level. Therefore, the serial access memory determines the level of the write enable signal WE at the falling edge of the chip enable signal GE in the address cent cycle, and selectively prepares for either serial read or write mode.

Although not particularly limited, the data input/output terminals DO to D7 are first supplied with the first X address xaa prior to the change of the chip enable signal GE to a low level in the address send cycle, and are supplied with the address set (the second
In synchronization with the fourth low level change, the final X address xea, the first Y address yaa, and the final Y address yea are sequentially supplied in a time-division manner.

In the serial access memory, the tie control signal φx
3 is temporarily set to high level, and the address sent signal A
According to the second to fourth low level changes of s, the timing signals φX6, φys, and φye are sequentially temporarily set to high level. Therefore, first, the tie control signal φXs is temporarily set to high level, so that the leading X
The address XSa is fetched into the first X address breadthr XBS, and then the tie control signal φxe is temporarily set to high level, so that the final X address x e a 7>
<Imported to final X address buffer XBE. Further, by temporarily setting the tie control signal ψys to a high level, the first By address ysa is taken into the first Y address buffer Y, and the tie control signal φye is temporarily set to a high level. So, the final Y address yen
is taken into the final Y address buffer YBE. In the tie generation circuit TG, the chimp enable fa number GE
At the falling edge of the write enable signal WE
Since this is at a high level, an operation mode flag is prepared to execute serial read mode. In addition, the X address decoder XD has the first X address xaa.
Internal address signals xO to x7 corresponding to Y are supplied, and Y
Address decoder YD is supplied with internal address signals 70-77 corresponding to the first Y address yaa. As a result, the eight memory cells designated by these addresses are brought into a selected state, and their read signals are amplified by the corresponding unit circuits of the read amplifier RA. In FIG. 3, the serial access memory starts the serial read mode when the serial input/output enable signal SE is set to low level following the address set cycle. A serial clock signal SC having a predetermined frequency is continuously supplied to the serial access memory without being aware of address set cycles or serial read or write modes. The level of the serial input/output enable signal SE is changed at a predetermined phase of the serial clock signal SC. In the serial access memory, although not particularly limited, the tying signal φoe is set to a high level due to a change in the serial input/output enable signal SE to a low level. As a result, 8 pints of stored data (XSa/ysa) at the address specified by the first X address xsa and the first By address ysa are read out and sent out via the data input/output terminals DO to D7. In the serial access memory, the tying signal φyc is also temporarily set to a high level in synchronization with the rising edge of the serial clock signal SC. For this reason,
The leading Y address expander YBS is incremented, and its count value, that is, the internal address signals yO to y7, becomes ysa+1. By the way, if the DMA controller temporarily loses the pass right in the next pass cycle, the memory control unit is not particularly controlled, but stops the serial clock (lsc) as illustrated in FIG. At the same time, the serial input/output enable signal SE is temporarily returned to a high level while the chip enable signal CE is kept at a low level.In the serial access memory, the serial input/output enable signal SE is temporarily set to a high level. in,
The tying signal φos is set to low level, and the output operation of the stored data is temporarily stopped. Furthermore, since the serial input/output enable signal SE is at a high level at the rising edge of the serial clock signal SC, the timing signal φyc is not applied, and the incrementing operation of the leading Y address buffer YBS is stopped. ．． As a result, the serial access memory temporarily stops the serial read mode and waits for the serial output enable signal SE to become low level again. When the serial input/output enable signal SE is set to low level again, a similar serial read operation is executed, and the serial clock fB No.
At each rising edge of C, the leading Y address buffer YBS is incremented. Then, start Y address bar 7
The count value of YBS, that is, the internal address signal y O-
When y7 reaches its last address y255, the tie-control signal φxc is temporarily set to high level at the same time as the tie-control signal φyc. As a result, the count {ffl, that is, the internal address signal xQxx7 of the first X address buffer XBS is incremented and becomes the next address xsa+l. Below, the serial read operation as described above, the first X address buffer XBS, and the first! IY Address Banfa YB
The stepping motion of S is repeated. Then, when the count value of the first X address buffer XBS becomes the final X address xea and the count value of the first KIY address buffer YBS becomes the final Y address yea, the output signal ea of the address comparison circuit AC becomes high level. , the final address detection signal EAIJ<low level. The memory control unit transmits the final address detection signal EA to the DMA controller to request interrupt processing, and also sets the chip enable signal CE to a high level when the read data (xea-ysa) of the final address is taken in. shall be. As a result, the serial access memory is released and the final address detection signal EA is also returned to high level. As described above, the serial access memory of this embodiment has the function of autonomously updating addresses in accordance with the serial clock signal SC and serially inputting or outputting a series of stored data. Therefore, the serial access memory holds the first X address and the next By address at which the serial input or output operation is started, and the first X address buffer X updates these according to the serial cross signal SC.
BS and a leading Y address buffer YBS, and a final and the address updated by the first Y address buffer YBS and the last X address buffer XBE
and an address comparison circuit A for comparing and verifying the final address held by the final Y address buffer YBE.
Equipped with C. In this embodiment, the first address and the last address are supplied in a time-division manner via data input/output terminals DO to D7. Further, the serial input or output operation and the stepping operation of the first X address buffer XBS and the first Y address buffer YBS are selectively stopped in accordance with the serial input/output enable signal SE.
The address comparison result by the address comparison circuit AC is transmitted to the DMA controller as the final address detection signal EA, and is used for interrupt request processing. Therefore, in the serial access memory of this embodiment, the number of external & IS terminals required to be installed is reduced, and the serial input or output operation is performed without interrupting the serial clock signal SC, which has a relatively high frequency. Controlled according to pass rights. In addition, it is possible to distinguish whether a serial input or output operation of the serial access memory has ended without providing an address management function in the memory control unit or the like. As a result, the data rate of serial input or output operations to the serial access memory can be correspondingly increased, and the amount of hardware added outside the serial access memory, such as a memory control unit or DMA controller, can be reduced, and the system can be improved. This can promote cost reduction.

As shown in the above embodiment, by applying the present invention to a semiconductor storage device such as a serial access memory,
The following effects can be obtained.

That is, (11) Provide an address buffer in a serial access memory or the like that holds the start address and end address to be serially accessed and that is incremented according to the serial clock signal, and compare and check the counted value of this address buffer with the end address. By providing an address comparison circuit to
It is possible to arbitrarily set the address range for serial input or output using a serial access memory or the like, and to autonomously identify when the serial input or output operation has been completed.

(2) In the above item +11, by supplying all or part of the above-mentioned start address and end address in a time-sharing manner via the data input terminal, the number of external terminals such as serial access memory can be reduced. can get. (3) In paragraphs (1) and (2) above, when the serial access memory or its controller does not have pass rights, the increment operation and serial input/output operation of the address buffer are temporarily controlled according to a predetermined control signal. By making it possible to stop the serial clock signal at a relatively high frequency, it is possible to control the serial input or output operation of the serial access memory according to the pass right while continuously supplying the serial clock signal, which is considered to have a relatively high frequency. .

(4) According to the above items (1) to (3), it is possible to increase the temitter rate of serial input or output operations of a serial access memory or the like, thereby increasing the processing capacity of the system.

(5) Items (13 to (3)) above have the effect of reducing the amount of external hardware such as serial access memory for address management, etc., and promoting lower system costs. .

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in FIG. 1, the memory array MARY may be of a divided array type, or one or more memory cells may be selected from a plurality of divided arrays. Furthermore, it is not an essential condition to supply the start address or the end address in a time-sharing manner via the data input/output terminal Do-D7. For example, by providing a separate address input terminal, only a part of the start address and the end address may be supplied in a time-division manner via the data input/output terminals Do to D7, or all may be supplied from a dedicated address input terminal. In this embodiment, the memory control unit or DMA controller has the path management function.
It is also possible to have this in the serial access memory itself. Address management in the serial access memory may be replaced with a pointer method using a shift register. If you want to execute serial read operations and serial write operations at the same time, you can provide both a serial input port and a serial output port in the serial access memory, and perform address management as described above for each port. If serial input or output storage data can be divided into blocks, you only need to input the first address. Furthermore, various embodiments including the block configuration of the serial access memory shown in FIG. 1, its storage capacity, and the combinations of timing signals and address signals shown in FIGS. 2 and 3, their names and bit numbers, etc. It can be harvested.

In the above explanation, the invention made by the present inventor was mainly explained in the case where it was applied to serial access memory for file memory, which is the field of application that formed the background of the invention, but it is not limited thereto. It can also be used for serial access memory, image memory, etc. used for other purposes. The present invention is widely applicable to semiconductor memory devices having at least a serial input or output function and digital integrated circuit devices including such semiconductor memory devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, an address buffer is provided in a serial access memory or the like that holds the start address and end address to be serially accessed and updates them autonomously, and the address buffer is used to compare and match the counted value of this address buffer with the end address. Provide a comparison circuit. In addition, all or part of the above address is supplied via the data input terminal in a time-sharing manner, and the sidewalk operation and serial input/output operation of the address buffer can be temporarily stopped depending on the pass right. Thereby, it is possible to arbitrarily set the address range for serial input or output, and to automatically identify that the serial input or output operation has been completed. In addition, the number of external terminals can be reduced, and serial input or output operations can be controlled according to path rights while continuously supplying a serial clock signal with a relatively high frequency. As a result, the data rate of serial input or output operations can be increased, and the amount of external hardware added for address management etc. can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a serial access memory to which the present invention is applied; FIG. 2 is a tie diagram showing an embodiment of the address cent cycle of the serial access memory of FIG. 1; FIG. 3 is a timing diagram showing an embodiment of the serial read mode of the serial access memory of FIG. MARY...Memory array, XD...X address decoder, CSW...Column inch, YD...Y address decoder, XBS...First Buffer, YBS・
...Destination MY address buffer, YBE...Zhang end Y address buffer, AC...Address comparison circuit, WA...
・Write amplifier, RA...Read amplifier, IB...
Input buffer, OB...Output buffer, TG...Tie sentence generation circuit.

Claims (1)

[Claims] 1. Has a function of serially inputting or outputting a series of stored data by autonomously updating addresses according to a predetermined clock signal, and selectively inputting or outputting a series of stored data according to a predetermined control signal. A semiconductor memory device characterized in that output operation and address update operation can be stopped. 2. The control signal is selectively enabled when a predetermined pass right is not given to the semiconductor memory device or its control device, and the address of the serial input or output series of storage data is set to a predetermined address. The semiconductor memory device can be specified arbitrarily according to a signal, and the semiconductor memory device further has a function of indicating that the serial input or output operation regarding the series of stored data has been completed. A semiconductor memory device according to claim 1. 3. The semiconductor memory device according to claim 1 or 2, wherein part or all of the address signal is supplied through a data input terminal.