JPH0357715B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse width modulation control device, and particularly to a pulse width modulation output control device which is one of the output voltage control means of an inverter device.

[Prior Art] A conventional pulse width modulation (hereinafter abbreviated as PWM) control device compares a sawtooth wave signal 10 and a DC voltage 12 to obtain an output 14, as shown in FIG.

By changing the voltage value e ₁ of the DC voltage 12 from 0 to e, the pulse width modulation ratio b/a is controlled from 0 to 100%.

[Problems to be Solved by the Invention] However, since this conventional device is of an analog type, it requires many adjustment points such as the magnitude e of the sawtooth wave signal 10, its frequency, the offset of the comparator, etc. The characteristics drift due to changes, making it difficult to obtain highly accurate ones.

The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to provide a digital, highly accurate pulse width modulation output control device for an inverter device.

[Means and effects for solving the problem] In order to achieve the above object, the present invention includes a first frequency dividing means for frequency dividing an input pulse, and a frequency dividing means for dividing an output pulse of the first frequency dividing means. a second frequency dividing means for outputting a carrier frequency pulse, a synchronizing signal output means for outputting a signal synchronized with either the rising edge or the falling edge of the carrier frequency pulse, and setting the output frequency of the inverter. an output frequency setting means for outputting an output frequency command using the output frequency command; and an output frequency setting means for storing an output frequency setting value of the inverter by inputting the output frequency command, and outputting a pulse width modulation ratio setting value for setting a pulse width corresponding to this output frequency. By inputting an output signal from the fixed storage means and the synchronization signal output means, counting of the output pulses of the first frequency dividing means is started, and when the counter value corresponding to the pulse width modulation ratio setting value is reached, a counter for outputting an inactivation pulse; a storage means for outputting an output signal of the inverter by being set by the output signal of the synchronization signal output means and reset by the inactivation pulse output by the counter; a rate multiplier that outputs a pulse proportional to the output frequency command value in response to an input of the output frequency command; and a third frequency dividing means that outputs the output pulse of the rate multiplier as a reset signal for the second frequency dividing means. It is characterized by having the following.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described based on the drawings. Figure 2 is a digital diagram of the device of the present invention.
FIG. 2 is a block diagram showing the principle of PWM. In FIG. 2, an oscillation circuit 18 having a crystal resonator 16.
First frequency divider 20, second frequency divider 22, differentiation circuit 2
4. Connect the memory circuits 26 in series, and
The output terminals of the frequency divider 20 and the differentiating circuit 24 are connected to the C terminal and the P terminal of the counter 28.
8 is connected to the R terminal of the memory circuit 26.

The digital PWM according to the present invention has the above configuration, and its operation will be explained below with reference to the signal waveform diagram shown in FIG. A signal 100 with a frequency f ₁ Hz is generated by the crystal oscillator 16 and the oscillation circuit 18, and this signal 100 is divided by the first frequency divider 20 (in the illustrated example, the division ratio is 1/2) to obtain the frequency f _v Hz signal 10
Get 2. Next, this signal 102 is frequency-divided by the second frequency divider 22 (in the illustrated example, the frequency division ratio is 1/12) to obtain a signal 104 having a carrier frequency f _c Hz. Differential circuit 24
outputs a signal 106 in synchronization with either the rise or fall (in the illustrated example, rise) of the above-mentioned signal 104, and sets the memory circuit 26 with this signal 106.

The counter 28 synchronizes with the rise or fall (in the illustrated example, the rise) of the signal 104.
It presets the PWM ratio setting value ("4" in the illustrated example) supplied to the D terminal, and counts down each time it receives the signal 102. When the counter content reaches 0, it generates the signal 108, and this signal 10
8, the memory circuit 26 is reset.

Therefore, an output signal 110 is obtained from when the memory circuit 26 is set by the signal 106 until it is reset by the signal 108. Therefore, counter 2
Signal 108 by changing the PWM ratio setting value for 8
The PWM ratio can be changed by changing the timing of occurrence of , that is, the timing of resetting the memory circuit 26, and by changing the pulse width C of the output signal 110.

In the above example, fine PWM control is performed by increasing the frequency division ratio of the second frequency divider 22 to make the frequency f _v Hz of the signal 102 sufficiently higher than the carrier frequency f _c Hz of the signal 104. I can do it.

FIG. 4 is a block diagram showing a part related to PWM control in an embodiment in which the device of the present invention is applied to an inverter, and the same members as in FIG. 2 are given the same reference numerals. Fourth
In the figure, the output frequency setter 30, rate multiplier 32, and third frequency divider 34 are connected in series, and the output terminal of the third frequency divider 34 is connected to the R terminal of the second frequency divider 22. There is. The output terminal of a clock signal generator (not shown) is connected to the rate multiplier 32 and the C terminal of the first frequency divider 20. This first
The Q terminal of the frequency divider 20 is connected to the C terminal of the second frequency divider 22 and the C terminal of the counter 28. Differential circuit 2
The output terminal of 4 is connected to the S terminal of the memory circuit 26 and the P terminal of the counter 28. The fixed storage device 36 has its input terminal A connected to the output terminal of the output frequency setter 30, and its output terminal D connected to the D terminal of the counter 28.

In the present invention, the rate multiplier 3
2 multiplies the output frequency of the output frequency setter 30 by an integer by a predetermined multiplication factor, and as described later, the output of the frequency divider 34, which is the frequency division signal, forms a PWM switching timing synchronization signal.

Therefore, the rate multiplier 32 inputs the pulse train signal 112, which is an integral multiple of the output frequency of the inverter output frequency setter 30, into the storage device 26.
By synchronizing PWM control, it becomes possible to perform PWM control at the frequency set for the inverter output, for example, within one cycle of the inverter output frequency.
By dividing the pulse into 30 degree or 60 degree phase angles and changing the modulated pulse width for each phase angle,
PWM can be performed according to the inverter output frequency, and the PWM frequency at this time can be made to correspond to the inverter output frequency.

Further, a characteristic feature of the present invention is that the output of the inverter output frequency setter 30 is supplied to a fixed storage device 36, and a predetermined V/F pattern is stored in this fixed storage device in advance. For example, in a relationship where the inverter output frequency is used as an address and the inverter output voltage is used as data, each of a plurality of inverter output frequencies is stored and corresponds to the pulse width with which this output voltage is modulated. Therefore, when the inverter output frequency output from the output frequency setter 30 is input to the fixed storage device 36, the inverter output voltage corresponding to that address, that is, the pulse width modulation ratio setting value is output. . Therefore, the ratio setting value that is the output of the setter 36 becomes a value that is PWM-controlled in accordance with the specified inverter output frequency, and pulse width control of the inverter output frequency is executed.

Further, in the present invention, the fixed storage device 36
The ratio setting value change changes depending on the inverter output frequency.

Hereinafter, the operation of the example shown in FIG.
This will be explained with reference to the signal waveform diagram shown in the figure. When the output frequency is set as a binary value by the output frequency setter 30, a pulse train signal having a frequency 6f that is six times the inverter output frequency f is output from the third frequency divider 34 via the rate multiplier 32. Get 112. Therefore, according to the embodiment, each cycle of the inverter output frequency f can be divided into 1/6 or 1/12, and the pulse width of PWM, which will be described later, can be switched at intervals of 60 degrees or 30 degrees in phase angle. 12 times or 6 times
PWM conversion is performed on the inverter output frequency output by PWM switching. clock signal 11
4 obtains a pulse train with a frequency sufficiently higher than the inverter output frequency using a crystal resonator or the like. This clock signal 114 causes a signal 10 with a carrier frequency f _c Hz to be transmitted through the first frequency divider 20 and the second frequency divider 22.
4, and based on this signal 104, the differentiating circuit 24.
Output signal 11 PWMed via memory circuit 26
Obtaining 0 is the same as the example in FIG.

In this embodiment, the second frequency divider 22 is synchronized with the above-mentioned pulse train signal 112, and the PWM always starts from the on state at the change point of the inverter output signal.
Of course, PWM can also be started from an off state. Further, the output of the inverter output frequency setter 30 is used as an address signal of the fixed storage device 36, and the output signal of the fixed storage device 36 is used as the PWM
It is supplied to the counter 28 as a ratio setting value.
Therefore, in the present invention, the pulse width C of the output signal 110 of the storage device 26 is adjusted in conjunction with the inverter output frequency.
The V/F pattern can be controlled arbitrarily depending on the contents of the fixed storage device 36, and a free V/F pattern can be easily obtained.

That is, according to the present invention, the fixed storage device 36 stores data corresponding to the output frequency according to the address signal of the inverter output frequency setter 30.
The PWM ratio setting value is supplied to the counter 28, and this
A pulse width C corresponding to the PWM ratio setting value is output from the storage device 26, and the address signal is transmitted to the rate multiplier 32 described above in the embodiment.
Similarly to the pulse train signal 112 determined by the frequency divider 34, it changes according to the inverter output frequency command. Therefore, when a fixed output frequency command is applied from the inverter output frequency setter 30 to the address input of the fixed storage device 36, this address input is assigned to a specific address set in the fixed storage device 36, such as a rate multiplier as described above. Pliers 3
2, the division period of one period of the output frequency determined by 2, for example, 12 or 6, makes a set of addresses sequentially read out, thereby determining the periodicity of the PWM ratio setting value in which the pulse width changes at a predetermined period. changes are obtained from persistent storage 36. As described above, the periodic change in the ratio setting value read from the fixed storage device 36 causes the output signal 110 of the storage device 26 to change to the pulse train signal 112.
By synchronizing the switching timing with the switching timing, the switching timing can be accurately controlled.

Furthermore, as is well known, when controlling a motor or the like using an inverter, the V/F pattern must correspond to the applied voltage V and the applied frequency F in a fixed pattern. If this is stored in the storage device 36 and both the frequency and voltage are controlled as PWM-controlled pulse widths, inverter control of motors and the like can be extremely effective.

At the PWM ratio setting, the pulse width C directly determines the voltage V, and the frequency of the synchronizing pulse train 112 determined by the rate multiplier 32 and frequency divider 34 and the frequency in the fixed storage 36. The set of addresses read out when the constant output frequency command is given determines the frequency F, and as is clear from FIG. 5, the pulse train signal 11
The period in which 2 is repeated six cycles is one cycle of the inverter output frequency.

By synchronizing the pulse train signal 112 of the present invention, the output signal 110 of the storage device 26 always starts from the on state at the rise and fall of the signal 112, and one cycle of the inverter output frequency is generated.
The pulse width of the output signal 110 is sequentially changed from the synchronization timing of each of the 12 equally divided pulse train signals 112, and one cycle of pulse width modulation of the inverter output frequency is performed after 12 cycles.

However, according to the present invention, the carrier frequency signal 104 is forcibly synchronously controlled by the pulse train signal 112 of frequency 6f, resulting in a situation as shown in FIG. Therefore, the PWM controlled output signal 1
10 is as shown in FIG. 5, and as compared to the output signal 110' when PWM is performed at a target ratio within one carrier period as in the example of FIG. 2, the following error occurs. That is, in FIG. 5, the output signal 11
0' becomes c/a, and the output signal 110 becomes (c×2)/(a+a-b)=2c/(2a-b).

However, also in this embodiment, the carrier frequency f _c
When becomes an integral multiple of the frequency 6f, b=0 and the error becomes 0. In addition, the inverter output frequency f,
Once the carrier frequency f _c is determined, the value of b can be found by calculation, so the output signal 110'' shown in Figure 5 is
By calculating the value of c' so that 2c'/(a+a-b)=c/a and correcting the contents of the fixed storage device 36 in advance, errors can be eliminated even in non-integer multiples. It is something that can be done.

That is, when synchronization is considered at an integer multiple period of the inverter output frequency f, the b value indicates a period during which the carrier frequency f _c is insufficient to maintain an integer multiple of the inverter output frequency f.

To explain this b value using Fig. 5, it is synchronized at 6 times the period, so 1/6f=n×1/f _c +r=n×a+r, where n is the synchronization of carrier frequency f _c In addition, r indicates the remainder at this time, and when n=1 in FIG. 5, the illustrated width value indicates r.

Therefore, b=a-r It can be found at

Therefore, it is understood that in the present invention, the b value is determined from the inverter output frequency f and the carrier frequency f _c .

Therefore, based on the above-mentioned principle, the fixed storage device 36
It is understood that in order to correct the pulse width ratio setting value of , the following calculation may be performed.

As mentioned above, if the b value is not 0, the average voltage of the inverter output will always be higher than the average value indicated by the predetermined modulation rate c/a value, which is undesirable as the inverter output voltage will be high as a result. .
The purpose of the error correction is to suppress this increase in output voltage to obtain a desired average voltage.

First, in order to obtain the error amount, the example shown in FIG. 5 will be explained.

The shortage period b is a period in which the 110' signal is "L". Therefore, in the 110' signal, the average voltage within the 1/6f period is expressed as 2c/(a+a-b) [>c/a].

In this state, in order to obtain a predetermined average voltage, it is necessary to reduce the on-period c of the PWM signal.

2c'/(a+a-b)=c/a Therefore, 2c'=c(2a-b)/a c'=(2a-b)×c/2a=c-b×c/2a, and the above c ′, the predetermined value c
It is understood that by subtracting b×c/2a from the average voltage within a 1/6f period becomes a predetermined value.

Therefore, by pre-storing the modified c' rather than c as the content of the fixed storage device 36, it is possible to always obtain a modified average voltage.

[Effects of the invention] As described above, the device of the present invention can digitally
Since it controls PWM, there is no need for the trouble of adjusting multiple points as in conventional analog-controlled devices. Furthermore, since it is a digital type, it is less susceptible to temperature changes and has the advantage of being able to perform PWM with high precision.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of a conventional pulse width modulation control device, FIG. 2 is a block diagram showing the principle digital modulation circuit of the pulse width modulation output control device of the present invention, and FIG. FIG. 4 is a block diagram showing a preferred embodiment of the pulse width modulation output control device for an inverter device according to the present invention, and FIG. 5 is a signal waveform diagram of each part of FIG. 4. The same members in each figure are given the same reference numerals, 16 is a crystal resonator, 18 is an oscillation circuit, 20 is a first frequency divider,
22 is a second frequency divider, 24 is a differential circuit, 26 is a storage circuit, 28 is a counter, 30 is an output frequency setter, 32 is a rate multiplier, 34 is a third frequency divider, and 36 is a fixed storage device.

Claims (1)

[Claims] 1. A first frequency dividing means for frequency dividing an input pulse, a second frequency dividing means for dividing an output pulse of the first frequency dividing means and outputting a carrier frequency pulse, and a rising edge of the carrier frequency pulse. or a synchronizing signal output means for outputting a signal synchronized with either one of the falling edges; an output frequency setting means for setting the output frequency of the inverter and outputting an output frequency command; fixed storage means for storing a frequency setting value and outputting a pulse width modulation ratio setting value for setting a pulse width corresponding to this output frequency; a counter that starts counting the output pulses of the means and outputs an inactivation pulse when the counter value corresponding to the pulse width modulation ratio setting value is reached; and a counter that is set by the output signal of the synchronization signal output means and a storage means that is reset by the inactivation pulse output from the counter and outputs the output signal of the inverter; a rate multiplier that outputs a pulse proportional to the output frequency command value by inputting the input pulse and the output frequency command; A pulse width modulation output control device for an inverter device, comprising: third frequency dividing means for outputting the output pulse of the rate multiplier as a reset signal of the second frequency dividing means.