JPH0355830B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a liquid crystal display device used, for example, in a blood pressure monitor.

Conventionally, there has been a bar graph display device of this type, which can display two systems: the amount of fluctuation and the set value, and is convenient as a display device for a blood pressure monitor or the like. However, since there are many types of drive voltage values to perform this display, and the voltage values do not have an integer multiple relationship, it is difficult to obtain these voltage values easily, the circuit configuration becomes complicated, and the power consumption increases. It had drawbacks such as high current.

Therefore, the present invention selectively supplies four types of common pulses and four types of segment pulses each having a voltage of 0, V0, or 2V0 to the common electrode and segment electrode, thereby simplifying the circuit configuration and reducing the voltage. The present invention provides a liquid crystal display device that can be driven and provides good display.

An embodiment of the present invention will be described below based on the drawings. In Figure 1, 1 is a one-digit counter that counts the pulses supplied to terminal _a0 and generates a binary decimal output, and 2 counts the carry pulses of counter 1 and generates a binary digit decimal output. This is the second digit of the counter generated. Pulses corresponding to the display target are collected at terminal a _0. For example, when displaying a percentage of a measured variable relative to a reference value, a number of pulses corresponding to the calculated percentage value are collected. Become a pulse. In addition, when used as a display device for a blood pressure monitor, a pulse corresponding to the value measured by the blood pressure monitor is supplied, but in this case, a third digit counter is also required, and the scale needs to be adjusted accordingly. .

In this example, a display example will be described in which the percentage of the former variation amount and the current time are held at a specific time. Reference numerals 3 and 4 indicate memory latch circuits constituting a memory circuit for storing the output values of counters 1 and 2, respectively, and the above-mentioned values are determined by pulses supplied to terminal _b0 from a clock device (not shown) at a specific time. A memory operation is performed. 5 and 6 are integration type decoders that convert each output value of counters 1 and 2 into decimal, generate an output to the corresponding terminal, and also maintain the output state of each previous terminal; Configure the integration output circuit. Decoders 7 and 8 convert the output values of the memory latch circuits 3 and 4 into decimal values and generate outputs only to terminals corresponding to the values. Reference numeral 9 denotes a coincidence circuit that generates a detection output when the respective output values of the counter 2 and the memory latch circuit 4 match. 1
Reference numerals 0 and 11 are output value conversion circuits that change the order of output generation depending on whether the output values of the counter 2 and the memory latch circuit 4 are even or odd. 12 is a segment voltage supply circuit that selectively applies voltage to segment electrodes, which will be described later. Reference numeral 13 designates a common voltage supply circuit that selectively applies a voltage to the common electrode, which will also be described later. The outputs of these voltage supply circuits control the lighting of display elements, which will be described later. 4a and 4b are inverters. The segment voltage supply circuit 12 and the common voltage supply circuit 13 constitute a pulse supply circuit.

2 and 3 show arrangement patterns of common electrodes and segment electrodes that receive pulse voltages from the common voltage supply circuit 13 and segment voltage supply circuit 12 shown in FIG. 1. 14a-1
4j is a common electrode and is insulated from each other. Reference numeral 15 indicates a group of ten segment electrodes facing each of the common electrodes 14a to 14j. Ten segment electrodes 15 . . . 15 facing each common electrode 14 a to 14 j are connected in common to ten adjacent segment electrodes and those located symmetrically with respect to their boundaries. Reference numeral 16 is a common electrode for scale, which is disposed at a position facing a part of the segment electrodes 15 . . . 15 and is used to form a scale. The display element configured by interposing a liquid crystal between each common electrode and the segment electrode is omitted because it can be easily implemented by a person skilled in the art based on the prior art.

FIG. 4 is a detailed circuit diagram of the integration type decoder 5 shown in FIG.
Decode the forward force into decimal and output the corresponding output terminal a ₀
~A Logic value “1” (hereinafter referred to as “1”) is applied to one terminal of ₉ .
That's what it means. ). 17 to 20 are OR gate circuits.

FIG. 5 is a detailed circuit diagram of the output rank conversion circuit 10 shown in FIG. 1, and 21 to 30 are AND gate circuits 31 to 35 are OR gate circuits.

Figure 6 shows the segment voltage supply circuit 1 shown in Figure 1.
2, in which 36-47 are AND gate circuits, 48-61 are analog switches that are turned on when the input is "1" and turned off when the logic value is "0" (hereinafter referred to as "0"), and 62-68 is an inverter.

FIG. 7 is a detailed circuit diagram of the common voltage supply circuit 13 shown in FIG. 1, 69 to 78 are AND gate circuits, 79 to 89 are analog switches similar to those shown in FIG. 6, and 90 to 95 are inverters. .

FIG. 8A shows a second pulse generation circuit that generates segment pulses, and FIG. 8B shows a first pulse generation circuit that generates common pulses.
96 to 115 are analog switches similar to the above,
116 to 120 are OR gate circuits, and 121 is a timing pulse generation circuit, which sequentially generates pulses at terminals p ₁ , p ₂ and p ₃ every time a pulse of, for example, 256 Hz is input from the clock pulse generation circuit 122. 123 is a flip-flop circuit.

Figure 9 shows terminals S ₁ to S ₄ and C ₁ of terminals 8A and B.
~ _C4 is a chart showing the pulse voltage generated in one period T and the voltage waveforms _W1 to _W16 of the difference between both pulse voltages. In the figure, a segment electrode selection pulse, a first segment electrode half selection pulse, a second segment electrode half selection pulse, and a segment electrode non-selection pulse are generated at terminals S1 to S4, respectively;
Common electrode all selection pulse for each terminal C1 to C4,
A first common electrode half selection pulse, a second common electrode half selection pulse and a common electrode non-selection pulse are generated. In addition, pulses W1 to W3, W5,
W6, W9, W11 and W13 become on voltage, pulse W4, W7, W8, W10, W12 and W14~
W16 is the off voltage. Here, the terminal
The pulse voltage occurring in s ₁ to _{s 4} is the ratio of the period T to the total generation time t ₀ of the pulses of voltage V ₀ occurring during that period.
When t ₀ /T is 2/6 and the total generation time of a pulse of voltage 2V ₀ is t ₁ , the ratio t ₁ /T represents a pulse voltage of 2/6. The pulse voltage at terminals C ₁ and C ₄ is
The ratio t ₀ /T is 4/6, t ₁ /T is 1/6, and terminals C ₂ and C ₃ show pulse voltages with t ₁ /T 3/6.

Note that when any one of the voltage waveforms W ₁ to W ₃ , W ₅ , W ₆ , W ₉ , W ₁₁ and W ₁₃ is applied periodically, the display element lights up, and for the other voltage waveforms, The display element is set to be off.

As an example, the display when "30" is stored in counters 1 and 2 "25" and memory latch circuits 3 and 4 will be described below. Since the output value of the counter 1 shown in the first diagram is "5", the terminal _a5 of the decoder 5a shown in the fourth diagram is "1", and therefore the terminal _x5 of the OR gate circuit (omitted due to the periodicity of the circuit configuration)
produces “1”. This logical value is sequentially input to the preceding OR gate circuit, producing "1" at the terminals _x0 to _x4 and producing "0" to the other terminals _a6 to _a9 . These theoretical values are applied to the output rank conversion circuit 10, but since the content of the counter 2 is "2", that is, an even number, the terminal _a1 becomes "1" and the terminal _b1 becomes "0". As a result, the AND gate circuit 2 shown in FIG.
1, 23, 25, 27 and 29 are opened, and AND gate circuits 22, 24, 26, 28 and 30 are closed. Therefore, terminals i ₀ to i ₅ are “1” and terminals i ₆ to
i ₀ becomes “0”.

On the other hand, regarding the memory latch circuit 3, its value is "0", so the terminal _y0 of the decoder 7 becomes "1", the terminals _y1 to _y9 become "0", and the value is input to the output order conversion circuit 11. Ru. Here, the value of memory latch circuit 4 is "3", that is, an odd number, so terminal a ₂
becomes “0” and terminal _b2 becomes “11”. Since _the output order conversion _circuit 11 has _the same configuration as shown in FIG.
It turns out that it becomes. Since the values _of each of the above terminals are applied to _the segment voltage supply circuit _{12 ,} from FIG. The second output from the left is "1", and among the four AND gate circuits of terminals i ₆ to j ₆ and i ₈ to j ₈ , the fourth output from the left in the drawing is "1", and terminal i For ₉ ~ j ₉ , AND gate circuit 4
The output of 6 becomes "1". Therefore, the analog switch circuit 5 corresponding to each AND gate circuit
1, 55...61 are turned on. By the way, since each value of the counter 2 shown in the first figure and the memory latch circuit 4 are different, the terminal m of the coincidence circuit 9 is held at "0", and the analog switch 4 shown in the sixth figure is held at "0".
9 is turned on and analog switch 48 is turned off.
Therefore, the pulse voltage that is applied to terminal s ₂ is generated at terminals e ₀ to _{e 5} , the pulse voltage that is applied to terminal s 4 is generated to terminals e ₆ to e ₃ , and the pulse voltage that is applied to terminal s ₄ is generated at terminal e ₉ . ,
This results in a pulsed voltage being applied to terminal _s3 .

Regarding the common electrode side, since the values of the counter 2 and the memory latch circuit 4 are "2" and "3", the units k ₀ to _{k 2} of the integration type decoder 6 are "1", and the values of the terminals k ₃ to k ₉ is “0”, terminal q ₃ of decoder 8 is “1”, terminals q ₀ to _{q 2} and terminals q ₄ to
q ₉ becomes “0”. Therefore, in Figure 7,
Pulsed voltage applied to terminal c ₁ on terminal g ₀ and g ₁ , pulsed voltage applied to terminal c ₂ on terminal g ₂ , pulsed voltage applied on terminal c ₃ on terminal g ₃ , terminal g The pulse voltage applied to the terminal c ₄ and the pulse voltage applied to the terminal c ₁ are generated at the terminal d and 4 to _{g 9} , respectively.

Therefore, referring to FIG. 9, the common electrode connected to terminals g ₀ and g ₁ and the segment electrodes conductively connected to terminals e ₀ to c ₉ , the common electrode connected to terminal g ₂ and the terminal e Segment electrodes conductively connected to ₀ to e ₅ , common electrode connected to terminal g ₃ , segment electrode conductively connected to terminal e ₉ , scale common electrode 16 and all segment electrodes A display element whose constituent elements are lit up. FIG. 10 shows the lighting state, where the display elements indicated by hatching are lit.

In this way, the counts of counters 1 and 2 and the stored contents of memory latch circuits 3 and 4 are illuminated.

Note that the operating margin (effective value of lighting voltage/effective value of non-lighting voltage) in this example is √5, and although the maximum voltage value applied between the electrodes is low, the operating margin is a large value.

In this embodiment, a bar graph has been described, but the present invention is not limited to this, and a display device formed in a circular shape may be used.

As detailed above, the present invention is applicable to voltages 0, V0,
2V0 constitutes four types of common pulses and four types of segment pulses, and these pulses are used to display the total and a specific value that serves as a pointer, so there are fewer types of voltage values. , and since only V0 and twice its voltage are required, the power supply circuit for creating these voltages can be easily configured. Moreover, it has low voltage, low current consumption, high operating margin, and the ability to simultaneously display specific values such as integration display, pointer display, and scale display regardless of the number of common electrodes.

[Brief explanation of drawings]

The drawings show an embodiment of the present invention; FIG. 1 is an electric circuit diagram thereof, FIG. 2 is a plan view of the common electrode arrangement pattern of the bar graph display section, and FIG. 3 is a plan view of the arrangement pattern of the common electrodes of the bar graph display section. Plan view of arrangement pattern, 4th
Fig. 5 is a detailed circuit diagram of the integration decoder shown in Fig. 1, Fig. 5 is a detailed circuit diagram of the output rank conversion circuit shown in Fig. 1, Fig. 6 is a detailed circuit diagram of the segment voltage supply circuit shown in Fig. 1, and Fig. 7 is a detailed circuit diagram of the segment voltage supply circuit shown in Fig. 1. 8 is a detailed circuit diagram of the common voltage supply circuit, FIGS. 8A and 8B are pulse generation circuits for the voltage applied to the segment voltage supply circuit and the common voltage supply circuit, and FIG. A chart showing the voltage waveform and the voltage waveform between both electrodes, and FIG. 10 is an explanatory diagram showing the lighting display state of the bar graph. 1, 2... Counter, 3, 4... Memory latch circuit, 5, 6... Integration type decoder, 7, 8
... Decoder, 9 ... Matching circuit, 10, 11 ...
Output rank conversion circuit, 12... segment voltage supply circuit, 13... common voltage supply circuit.

Claims (1)

[Claims] 1. Segment electrodes are arranged close to each other, common electrodes are arranged facing each other for each group of segment electrodes, and segment electrodes at symmetrical positions in adjacent groups are connected to each other, A display element is constructed by interposing a liquid crystal between the segment electrode and the common electrode, a counter is provided that generates a count output, an integration output circuit is provided that receives the output of the counter and generates an integration output, and a specific value is stored. A memory circuit is provided to generate four types of common electrode full selection pulses, first common electrode half selection pulses, second common electrode half selection pulses, and common electrode non-selection pulses each having a voltage of 0, V0, or 2V0. A first pulse generation circuit that generates a common pulse is provided, and a segment electrode selection pulse consisting of a voltage of 0, V0, or 2V0, a first segment electrode half selection pulse, a second segment electrode half selection pulse, and a segment electrode. A second pulse generation circuit that generates four types of segment pulses including non-selected pulses is provided, and the pulse generation circuit selectively generates each pulse from the first pulse generation circuit in accordance with the output values of the integration output circuit and the storage circuit. A pulse supply circuit is provided to supply the common electrode and selectively supply the pulse from the second pulse generation circuit to each segment electrode, and the display element is generated by the potential difference between the common electrode all selection pulse and each segment pulse. applying an on voltage to the display element based on the potential difference between the first common electrode half selection pulse, the segment electrode selection pulse and the first segment electrode half selection pulse; applying an off voltage to the display element by a potential difference between the common electrode half selection pulse, the second segment electrode half selection pulse and the segment electrode non-selection pulse; An on-voltage is applied to the display element by a potential difference between the electrode selection pulse and the second segment electrode half selection pulse, and the second common electrode half selection pulse, the first segment electrode half selection pulse and the segment electrode selection pulse are applied. Applying an off-voltage to the display element based on the potential difference between the common electrode non-selection pulse and each of the segment pulses; applying an off-voltage to the display element based on the potential difference between the common electrode non-selection pulse and each segment pulse; A liquid crystal display device characterized by displaying an integration value and a specific value.