JPS58178283A - Electronic time piece - Google Patents

Abstract

PURPOSE:To enable the measurement of clock rate for any kind of clock rate measuring apparatus by selecting the alarm OFF mode or the chime mode. CONSTITUTION:With a rotary operation of a crown, the alarm mode is selected and an alarm function display pattern AL is indicated by lighting. At this point, when the alarm is set not to work, namely the signal ALON is at the level L, only the mark signal MB2 from a mark control circuit 10 is at the level H while other mark signals are 11 at the level L, and hence circumferential display patterns a1-a20 are all OFF in the indication. On the other hand, 20 display patterns b60, b3, b6...b57 alone light and a display for OFF state of the alarm is done. At the same time, an electric field signal of 2nHz (128Hz) is released on the surface of a liquid crystal cell thereby enabling the measurement of clock rate with a clock rate measuring apparatus with 1, 2 and 10sec gates.

Description

[Detailed description of the invention] The present invention relates to an electronic watch having a display device.

In recent years, electronic watches have appeared that use liquid crystal cells for display and display the time as a pointer. These three factors are based on the chip size of integrated circuits (hereinafter referred to as ICs) and the advantages of circuit wiring.
A split matrix drive scheme is used.

However, in the 3-split matrix IJ drive system, the frame frequency of the liquid crystal drive waveform is 2°/311z, so the rate measuring device with measurement gates of 1 second, 2 seconds, 10 seconds etc. The drawback was that it was difficult to measure the rate from the liquid crystal cell surface of the watch.

In order to eliminate the above-mentioned drawbacks, the present invention provides a rate measuring device that can measure the rate of a watch without adding a large amount of circuitry.
The present invention provides an electronic timepiece equipped with a multi-segment display device that emits an nH2 electric field signal.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The external appearance of an electronic timepiece to which this invention is applied is as shown in FIG. 2 is provided.

In normal use, the crown 2 is in the first stable position N shown by the solid line, and when it is pulled out one step from there to the second stable position M, the display on the display device 1 can be corrected by rotating the crown 2. I can do it. In either case, as seen from the right side of Fig. 1, there are two cases in which IJ and -Z 2 are rotated clockwise in the direction of arrow R and those in which they are rotated counterclockwise in the direction of arrow ■. Each corrects different information; for example, rotating crown 2 to the right will adjust the time or alarm time in the backward direction, and conversely, rotating crown 2 to the left will adjust the time or alarm time in the forward direction. .

Furthermore, by rotating the crown 2 at the first stable position N, the display functions of the display device 1 are switched, such as hours, minutes and seconds, alarm time or OFF display, and chime ON.
Each function can be selected to display N or OFF. Furthermore, if the chime is selected by the rotation operation at the first stable position N, the crown 2 is pulled directly to the second stable position M in this selected state.
By repeating the operation of pushing Lees 2 to the first stable position N, the chime function will be turned on and off (ringing set and non-ringing set) each time the button is pressed.
It is done alternately.

If, for example, the alarm time display function is selected by the rotation operation at the first stable position N, then with this function selected, the Lease 2 is pulled to the second stable position M, and then By repeating the operation of pushing the leash 3 to the first stable position N, the on/off control (sounding set and non-ringing set) of the alarm function is alternately set for each pushing operation.

FIG. 2(A) is a plan view of a three-part matrix display device 1 which is an embodiment of the present invention.
outer circumferential display patterns a1 to aa.

, 60 inner circumferential display patterns b1 to bao, a pm display pattern P, and an alarm function display pattern A L, for example, the time of 9:20 p.m. In this case, as shown by the hatched line in FIG. 2(A), the hours are displayed using the inner display pattern b46, and the minutes are displayed using the inner display pattern yb2. and outer peripheral display pattern 22
0, and seconds are displayed by lighting up the inner display pattern b60 and the outer display pattern a6°, respectively, and lighting up the afternoon display pattern P.

FIG. 2(B) is a plan view showing the upper substrate 1a of the display device 1 when viewed from the display surface side. On the lower surface of the upper substrate 1a, outer segment electrodes DAI to DA2 (1:, inner segment electrodes DBI) are provided. -Transparent electrode segments each consisting of the DB 20 and the character display segment (Pad) are formed. 7 Further, on the lower surface of the upper substrate 1a, there are common electrodes COM1' to COM3 connected vertically to common electrodes C0M1 to C0M3 formed on the lower substrate 1b, which will be described later.
' is formed.

FIG. 2(C) is a plan view showing the lower substrate 1b of display device #1, and a common electrode C0M1 is provided on the upper surface of this lower substrate 1b.
~C0M3 is formed (・ru.

Therefore, by sandwiching the liquid crystal between the upper substrate 1a and the lower substrate 1b and laminating and sealing them, the outer peripheral segment of the hook of the upper substrate 1a) I) A l -DA 20. Inner segment electrode DBI-DB20 and character display segment electrode Pa
β and the common electrodes COM] to C0M3 on the upper substrate 1b side overlap each other in a plane, and as shown in FIG. 2(A), the outer peripheral display patterns a1 to aeo and the inner peripheral display patterns b, to
b6o will be configured respectively.

Further, the signal Pal output from the mark segment driver 151 is connected to the function display segment Pa.

In other words, these relationships are shown in Table 1 below in detail.

FIG. 3 of Table 1 is a block diagram of an electronic timepiece according to an embodiment of the present invention. 4 is a frequency dividing circuit that divides the oscillation signal from the crystal oscillation circuit 6 as a time standard and outputs frequency-divided signals P1, P2, Pa, and P4; 5 is the potential of the battery (not shown) DD (for example, 0 volts) and the potential vsgr,
(for example -15 volts) as the reference potential and the frequency-divided signal P4
A booster circuit that outputs a boosted potential V, H (for example, -30 volts). 6 is a safety switch that closes when the crown 2 is in the stable position M and outputs an H level signal MH; 7 is a safety switch that alternately switches T, (level, A switch 8 outputs an L level signal SL, a switch 8 outputs a signal 81-L when the crown 2 is rotated in the direction of the arrow R, and 9 is a switch control circuit, as shown in the circuit diagram of FIG. A pulse generator 9a outputs a narrow pulse signal SO in synchronization with the rise of the signal MH and a narrow pulse signal SD in synchronization with the fall of the L level signal MH, and a pulse generator 9a outputs a narrow pulse signal SD in synchronization with the rise of the signal SL. A pulsing circuit 9b that outputs a narrow pulse signal PL, a pulsing circuit 9c that outputs a narrow pulse signal PR in synchronization with the rise of the signal SR, and an inverter that receives the signal MH as an input. 9d, AND gates 9e and 9f whose one input is supplied with the output signal of the inverter 9d and whose other inputs are supplied with the signals PL and PR, respectively, and TK-+AL→CH for each output signal of the AND gate 9e. →TK, and each output signal of AND gate 9f is selected in the order of K T K
-+ Selected in the order of CH → A L → TK, and then H
A mode selection circuit 9g that outputs mode signals TK, AL, and C1l that become levels, and an AND gate that is supplied with input signals M H and PL and outputs a correction signal US for correcting the time or alarm time in the forward direction. 9h, an A N D gate 9 to which signals MH and PR are supplied to inputs and outputs a correction signal D S for correcting the time or alarm time in the direction of delay; OR gate 9 using each correction signal US1DS manually
In this case, the mode signal AL and the signal SU are supplied to the inputs of A.
N ], ) gate 9J and a flip-flop (hereinafter referred to as The output signal of the gate 9m and the AND gate 9J is 1 level. an F-F9n which is set when the AND gate 9m outputs a signal ALON which is inverted at the falling edge of the output signal of the AND gate 9m, stores whether or not the alarm is allowed to sound, and outputs a signal ALON which becomes level 11 when the alarm is in the allowed state; When the mode signal CH and the signal SD are supplied to the inputs of the ND gate 9o and the output signal of the AND gate 90 falls, the mode signal CH and the signal SD are supplied to the input terminal A, and the output signal of the AND gate 90 performs an inverting operation. [F-F" 9p which outputs the signal CHON which becomes I level, AND gate 9q whose inputs are supplied with the mode signal AL and signal ALON, and the output signal of the AND gate 9q and the input of the mode signal TK. is supplied to the display selection signal TA.
An inverter 9s inverts the display selection signal TA and outputs a display selection signal 1. Reference numeral 10 shown in FIG. 3 is a mark control circuit, and the configuration of this mark control circuit 10 is shown in the circuit diagram of FIG.

'That is, the chime-on-mark circuit 10a, which receives the frequency-divided signal P2 to the clock terminal y and outputs signals CI, C2, and C3 which sequentially become II level each time the frequency-divided signal P2 is output, and the signal CI- 1ON and mode signal CI-
(and the AND gate 10b whose input is supplied with
AND gates 110C, 10d and 10e have one input supplied with the output signal of the gate 10b and the output signals CI, C2 and C3 of the chime-on-mark circuit 10a supplied with the other input, respectively, and invert the signal CHON. an inverter 10g that outputs a mark signal MA2 by inputting an output signal of the inverter 10g and a mode signal CI;
an inverter 101 for inverting LON; an ANI gate 10i to which the output signal of the inverter 10h and a mode signal AI are supplied;
0 do) Output signal and AND game) The mark signal MA3 output from jQe is supplied to the input and the mark signal M
OR gate 10J that outputs AI and AND gate IO
The output signal of A and the mark signal MA3 are supplied to the OR gate 10 which outputs the mark signal MB1.
N I) Output signal of gate 101 and mark signal MA2
is supplied to the input and outputs the mark signal M B 2.
R, Gu) 101:, A N I) Kate 10C, 1
an OR gate 10m whose inputs are supplied with each output signal of 0d and a mark signal MA3, and which outputs a mark signal MH3;
Mode signal TK and mode signal A L are input, and signal M
Consists of 4 & output 0■(, gate 10n (
·reactor.

Reference numeral 11 in FIG. 3 is a timing signal generating circuit which receives the frequency divided signal P3 as an input signal and outputs timing signals '1'1, G2, T3 and T4 as shown in the time chart of FIG.

Reference numeral 12 designates a timekeeping circuit, which includes a time counter section 12a that counts the frequency-divided signal P1 and outputs the current time content as a time information signal DT, and an alarm counter section 12 that outputs the alarm set time content as an alarm time information signal DA.
b, and when the mode signal TK is selected at the I (level), the time counter section 12a is corrected in the advance direction by the correction signal USK or by the correction signal DS.
It is corrected to lag behind vc.

Further, when the mode signal AL is selected to the I] level, the alarm counter section 12b is modified in the forward direction by the modification signal US or in the delay direction by the modification signal DS. 13 is the mode signal TK and A L
A switching circuit 14 selectively outputs the time information signal DT and the alarm time information signal DA as a switching control signal, and a switching circuit 14 supplies the time information signal DT or the alarm time information signal DA from the switching circuit 16 to set the time or alarm time. This is a decoder for displaying a pointer and selectively displaying the afternoon display pattern P in a timely manner, and the decoder 16 outputs a code signal Sa corresponding to the outer display pattern aI-atto and the inner display patterns b1 to bao, respectively. ,
~5a6o and code signal sb.

~Sb0° is being output and the time counter section 12
When alarm counter 12a or alarm counter 12b takes the afternoon count (8 in memory), it is configured to output a signal T A P of level I]. 16 are timing signals TI, T
2, T3 and T4 as input signals, common signals Com 1, Com 2 and C having potentials of VD, V, BL and VI18H as shown in the time chart shown in FIG.
It is a common driver that outputs om3, and the common signal C
om1, Com2 and Com3 are the common electrodes COMI, C0M2 and COM3 of the display device 1, respectively.
K is supplied. Reference numeral 15 denotes segment dryers, which are constructed as shown in the circuit diagram of FIG.

That is, mark signals MAI to MA3 and MBI to MB
3 are used as data inputs and have a surface, respectively, mark signals MAI to MA3, bark 15a to 15f (hereinafter abbreviated as Ci), and code signals CS a ) to S.
a6o, Sa5g], [Sa2, Sas, Sa4]
...20 outer circumferential segment drivers 15g1 to 15gn each having the same circuit configuration and inputting [Sa, 6.5a57, Sa5g), and code signals [sb, .sb, 0.5b5o]・(sb2・
sb,・sb,]・・・・・・(Sb56,sb,,
, 5b58] as inputs, and each has the same circuit configuration. ~
15hn, and a C which receives the mode signal A L and the signal TAP as inputs, respectively, and receives the outputs of Ci (yo) and (evening) as inputs, respectively.
The wired 0Ft (■e) connecting the output lines of i (shi), (n) and Ci (shi) and (n), and the output signal of the wire FOR (We) and the timing signal T4 are input. EX-NOR (
A character segment driver 151 is configured.

Moreover, these outer circumferential segment drivers 15g1 to 15
Outer segment driver 1 for each circuit configuration of gn
Representative L'''C'C with the circuit configuration of the inner segment driver 15h1 In the explanation of the circuit configuration of each of the inner segment drivers 15h1 to j 5hn, the circuit configuration of the inner segment driver 15h1 will be explained first. The circuit configuration of the driver 15g1 is based on the code signal Sa3.5aa.
o and! , ISa5g are respectively input, and when the display selection signal TA is at H level, the inversion passage permission state is established3.
Ci(a), (b) and (...) and the Ci(a)
, (b) and ()・) and the above 0118a
, t5C and 115e are connected to each other as shown in the figure.

(W,), (W2) and (Ws,), and each output signal from the wires oR, ZW, -) to (W,) are input, respectively, and the timing signals T1 to T3 are input to the respective output signals. Three Cis that are in the reverse passage permission state when
(d), (e) and (e), and the wired OR, (W4) which connects each output line Y of said C1(d), (e) and (e), and said wired 0a(W , ) is supplied to one input terminal, the timing signal T 4 is supplied to the other input terminal, and the segment signal D a ] is outputted.
OR, ()) (hereinafter abbreviated as EX-NOR)
It is composed of (・ru.

Moreover, each segment signal 1) a 1 to I) a output from each outer circumferential segment driver 15g1 to 15gn
2 (1 is CB)K shown in FIG. 2. Each of the outer circumferential segment electrodes 1)Al to I)A is connected so as to be supplied in correspondence with 20.

Similarly, the circuit configuration of the inner segment driver i5h+ is based on the code signals sb, , 5b6o and sb5. Ci (chi), (su) and (nu) which are in the inverted passage permission state when the display selection signal TA is 1 level and the respective outputs of the corresponding Ci (chi), (su) and (nu). line and cilBb, 1!5d and 1! Each output line of If is connected to a wire FOR (
W a ), (wb ) and (Wc), and the wire F
The output signals from OR (Wa), (wb), and (Wc) are input, and the timing signals TI, T2, and T3 are the three Cis that are in the inversion pass permission state when they are at [l level, respectively. (o) and (wa), and the Ci(ru), (
Wired 01 (,, (W d ) that connects the output lines of E) and (W), respectively, and the wire F
EX-NOR (power) that supplies the output signal from OR (Wd) to one input terminal, supplies the timing signal T4 to the other input terminal, and outputs the segment signal Dbl.
It is composed of.

Moreover, each segment signal Dbl to Db20 outputted from each inner circumferential segment driver 15hi to 15hn is transmitted to each inner circumferential segment electrode DB1 to DB2 shown in FIG. 2(B).
The connection structure is such that the signals are supplied in correspondence with 0.

17 is a time information signal from the time counter section 12a〕T
18 is a coincidence detection circuit that detects coincidence between time information signal 1) T and alarm time information signal 1) A. 19 is a control signal that uses signal ALON and signal C110N. This is a sound control circuit that performs sound control so as to supply the output signal from the hour detection circuit 17 and the output signal from the negative number detection circuit 18 to the buzzer drive circuit 20 (AND gates 19a, 19b and OR gate).
119C. 21 is a buzzer driven by the buzzer drive circuit 19;

Next, the operation of the electronic timepiece with the above configuration will be explained.

In the normal clock state (.), the mode selection circuit 9g is selected to the time mode which takes the timekeeping mode, that is, the mode signal TK = l level (. Level display selection signal TA
Therefore, the time information signal D of the clock circuit 12
T is displayed as a time point on the display device 1 via the switching circuit 16, decoder 14, and segment driver 15.

From this state, when the crown 2 is set to the second stable position ffiIM to adjust the time, the safety switch 6 closes and the signal M
At the H'b'-II1 level, the AND gate 9h is in a state where the signal PL can pass, and the AND gate 91 is in a state where the signal PR can pass. Therefore, a signal S is sent to repeatedly rotate the crown 2 at the second stable position M in the direction of the arrow.
L is outputted as a correction signal TJS via the pulse forming path 9b and the AND gate 9h, and corrects the contents of the time counter section f2a in the timekeeping circuit 12 in the forward direction.

Conversely, when the IJ and -z 2 are rotated in the direction of the arrow R at the second stable position M, the switch 8 opens and closes, and the switch 9C opens and closes.
A, ND gates 91 are output as correction signals DS, and the contents of the time counter section 12a in the timekeeping circuit 12 are corrected in the direction of delay.

Next, when the crown 2 is returned to the first stable position tN in order to select the alarm mode from this state, the signal 4H goes to the L level and the inverter 9d outputs the I-level output signal. When the crown 2 is rotated in the direction of the arrow L in the first stable position N of the crown 2 and the switch 8 is opened and closed once, the signal SL is converted to the pulse generator 9.
It is output as an output signal whose level changes via the signal line b.

As a result, the mode selection circuit 9g determines that the mode signal AL is [
At the same time, the character segment driver 15iK lights up and displays the alarm function display pattern AL.

At this time, for example, if the alarm is not sounding, that is, the signal A L ON is at the L level, the output signal of the AND gate 9q is at the Y level, and since the mode signal TK is at the 17 level at this time, the OR gate is )9r
and an inverter 9s. Moreover, at this time,
The mark signals MAI to MA3 and MB1 to MB3 from the mark control circuit 10 are converted into a mark signal MB by an inverter 10h, an AND gate 101, and an OR gate 10p.
Only mark signal MAI to MA is at L level, and the other mark signals MAI to MA
3. Since MBI and MB3 are all at L level, C1
Each output signal of 15a, 15C and 15(・ is 1 level,
Each output signal of the wire FOR(W,) to (W3) is I
(Level, each output signal of Ci (d) to (g) is L level, the output signal of wired 11OR, (W4) is L level, and the timing signal from EX-NOFt (G) is as shown in Figure 7. The inverted signal of T4 is the segment signal D
It will be outputted as A1 to DA20, and all of the outer peripheral display patterns 31 to a20 will be in a non-lit display state. On the other hand, the inner segment Drino C15hi-15h n is
Since the mark signals MBI and MB3 are at the same level,
C115b, 15f output signal wired OR (W a
), (Wc) output signals are 1% i/v, , Ci(
/lz), (O,.Each, force signal.YoI7 level,Ci(
The output signal of (e) is the timing signal 0 The output signal of Ft (Wd) is the timing signal '1'2 (power) as shown in Figure 7.
As shown in the inner segment signal 1) b1 to I) b 2
0 will be output.

Therefore, the common electrode C
OM 2 and inner segment electrode I) B 1 ~ ■]) 1
D B 20 The conditions under which the voltage of VDD-Vfill+ and VsslI-VDD is applied between the top and bottom are 'Iti
In other words, <20 display patterns a, as shown in the schematic display state diagram of FIG. , a3, "6...
...a3O...only a54 and a5□ are lit and the alarm is not set (alarm OFF display)
A display indicating the meaning of is displayed. At this time, a 2 nHz (128 Hz) electric field signal as shown in FIG. 9 (2) is emitted onto the liquid crystal cell surface, and the rate can be measured using a rate measuring device having 1 second, 2 second, and 10 second gates.

Next, an explanation will be given of the operation of displaying the alarm sounding cent and setting the alarm time from this state.

In this state, when the lens 2 is moved to the second stable position MIICj, the switch 6 is closed, the signal MH becomes H level, and the A
At the same time, the ND gates 9h and 9i are in a state where the signals 1)L and PR can pass through, respectively, and the pulse signal SU output from the pulse generator 9a in synchronization with the rise of the signal Mf-1 is A.N. I) F-F via gate 9J
The output signal Q of 91 is set to a cent state of 1 level, and the signal A L ON of F-F9n is set to a level (■).

Moreover, at this time, the AND gate 9q outputs a signal at II level, and the OR gate 9' outputs a display selection signal TA at H level, so that the alarm time stored in advance in the alarm counter section 12b is Information signal 1)
A is the outer circumferential segment signal Dal~I via the switching circuit 16, decoder 14, and segment driver 15, respectively.
) a 20 and inner segment signals Dbl to Db2 (
1) is supplied to each outer circumferential segment electrode I) Al to DA20 and inner circumferential segment electrode i1) B ] to I) B 20, and the alarm time is displayed in the form of a guide, for example, as shown in FIG. A display state in which the alarm time is displayed indicates that the alarm is set to sound (alarm ON state).

Moreover, from this state where the alarm time is displayed,
For example, the user uses IJ at the second stable position M of Lease 2 to adjust to a new alarm time.

- When the lens 2 is rotated, the following operation is performed.

That is, when the crown 2 is rotated in the direction of the arrow 2, the signal SL is outputted as a correction signal US via the pulse generator 9b and the AND game 9h, and the alarm time in the alarm counter section 12b is corrected in the forward direction. The operation is performed, and by rotating the crown 2 in the direction of the arrow R, the signal SR is output to the pulsing circuit 9C and the AN
The correction signal DS is outputted through the D gate 91, and an operation is performed to correct the alarm time of the alarm counter section 12b in the direction of delay.

Moreover, once the crown 2 is rotated in the direction of the arrow or in the direction of the arrow R at the second stable position M in order to adjust the alarm time as described above, an H level signal is sent from the OR gate 9k. is output and the output signal Q of F-F9/
A reset operation is performed to set the 1j level to the 1j level, and the 9m becomes closed.

Therefore, in this state, when pushing the IJ, -2 from the second stable position M to the first stable position NlCf, an 11-level signal SD is output from the pulse generator 9a in synchronization with the downward movement. , A N I) Ge) 9m by F-F9n
The inversion operation of is prohibited, and deF9n is the output signal ALON.
Continue to be set at the H level, which is the state in which the alarm is set.

In addition, when the user pulls the IJ, -z 2 from the first stable position N to the second stable position M in this state, the signal MH becomes the [■ level again, and is output from the pulse generator 9a. 1 level signal S U or A N I) Gate 9J
FF91 and F-F9n are set to the set state via .

Therefore, in order for the user to set the alarm not to sound, the user does not rotate the crown 2 from this state, but simply pushes the crown 2 from the second stable position M to the first stable position NK.

That is, if the crown 2 is not rotated at the second stable position M, F-F9J will be in the previous set state.

9m is in the closed state, the signal MH generated based on the pushing operation of IJ, -2 from the second stable position M to the first stable position N is The l (level signal S I) output from the pulse generation circuit 9 in synchronization with the downlink is inverted to change the output signal ALON of the F-F9n to the I level via the A N I) gate 9m. The alarm can be set to a non-ringing state (alarm OFF state).

Furthermore, from this state, by repeating the operation of pulling the leash 2 from the first stable position @N to the second stable position MK, and pushing it again to the first stable position N, the alarm will be activated each time the push operation is performed. Ringing and non-ringing sets are performed alternately.

As described above, when the alarm time setting operation is performed and the time content of the time counter section 12a coincides with the alarm time of the alarm counter section 12b, the coincidence detection circuit 18 outputs a coincidence signal of 1 level. Ru.

Therefore, at this time, if the alarm sounding state is set in advance with the signal A L ON at the I-J level, the coincidence signal from the coincidence detection circuit 18 passes through the A N D gate 19a and the OR gate 19c. When the buzzer 21 emits a sound, the buzzer drive circuit 20 takes a drive operation.

Also, at this time, if the alarm is set in advance to a non-sounding state (signal A L (,) N = L level), the passage of the coincidence signal is prohibited by the AND gate 9aK, and the buzzer drive circuit 20 does not drive the buzzer 21.

Next, to explain the operation of the character segment driver 151, first, the mode signal T K = H
When the time counter unit 12a takes the morning time information, the signal TAP=L level, so when the timing signal 1-3 takes the H level, the signal TAP from the decoder 14 becomes Ci( Evening), Ci (So),
Wired OR (W e ) and E X -N OFt
The signal P a 7 as shown in FIG.

Second, when the mode signal TK2II level is set and the time counter section 12a is taking the afternoon time content, the -do signal A
Since the timing signal T3 takes 1 level, the signal TAP from the decoder 14 becomes Ci
(Yu), Ci (N), Wired 0R (We) and EX
-NOR, (T) to the signal P as shown in Figure 7 ■
a7, and as a result, the display pattern P lights up to indicate that it is afternoon.

Thirdly, when the mode signal AL=)I level, the alarm counter section 12b takes the memory contents of the morning, and the mode signal TK=:L level, so when the timing signal T2 takes the H level, The mode signal A L is Ci
(Y), Ci (shi) and wired OR, (W e )
is input to EX-NOR, (SO) via
P is Ci (evening), Ci (n) and wire FOR (W
Since the signal is input to EX-NOR (T) via e), the signal Pae as shown in Figure 7 (■) is output from EX-NOII (T), and as a result, display patterns A and L are lit. Alarm mode is selected and indicates °C.

Fourthly, when the mode signal A L = H level, the alarm counter section 12b takes the memory contents of the afternoon, and the mode signal TK = L level, so the timing signal T
2 takes H level, mode signals A and L are Ci(
EX-NOR (:, 7) K is input through the wire FOR (W e ), C
i (evening), Ci (n) and wire FOR (W e )
Since it is input to E X TN (,) l ((ツ) through If the alarm time is set to afternoon (
・Show something.

- (to rope t) These relationships are briefly shown in Table 2 below.
.

Table 2 Next, the operation of the chime function (time axis function) will be explained.

Alarm mode is selected (・A) state (signal A L
= 11 level), then switch the IJ use 2 in the direction of the arrow I with the first female localization 1iIN and rotate it 1- so that 8 opens and closes once, input 4.4 + jsr. - from the pulse generator 9b, a pulse signal 1'1. When the pulse signal PL is input to the output signal tl, the output signal of the 1-ro AN D game) 9e is 1. Level →
The mode selection circuit 9g selects the chime mode and the mode signal (11,
Mode signal A L = L level (-1-7-), so 0
1 (the display yrk selection information TA is set to level 11 by the gate 9r and the inverter 9S).

Moreover, at this time, the chime is not set (that is, if the signal CII ON is at level 17, the mote signal C1
l is output as the Trubel mark signal MA,2 through the A N D gate 10f, and outputs the OI (II level σ through the gate 10) mark (ri QM) to the history.
Since it is output as 132, the mark transmission NlA2 is
When the timing signal T2 is II level V), C115C,
Wired 0a (W2), (1 (E) and wire F
It is supplied to the input of 1.]\-N (eye (G) through OR (W, ), and 1132 to the mark signal is supplied to C115 (1, wire FOR(Wd), (', i (λ) and wired (J R, (W d) via EX −N □ If
(force) input, so the segment signal Dal
~Da20 and Db1~■) As for b20, a signal as shown in FIG. 7 (■) is output.

Therefore, the outer peripheral display patterns a3 and C6 corresponding to the common electrode COM2K to which the common signal Com2 is supplied
, a, ...C6o and inner circumference display pattern b,
,b, ,b,... only bao lights up as shown in Figure 80 and the chime is not set (chime OFF).
state). At this time, a ninth cell is placed on the liquid crystal cell surface.
A 2nHz electric field signal as shown in Figure ■ is induced, and
It is possible to measure the rate with a rate measuring device having a second and 10 second gate.

At this time, for example, even if the hour detection circuit 17 is disconnected @ the hour counter section 12a detects the hour, the signal CHO at level ■
Since the AND gate 19b is prohibited from passing the hour detection signal, the buzzer 21 is not driven by the buzzer drive circuit 20.

Next, in this chime mode state, the following operation is performed to set the chime to the chime set state (chime ON state).

That is, when the IJ, - 2 is pushed from the second stable position M to the first stable position N, the signal M H
A Lebel pulse (iqsI) is generated from a, and this pulse signal SD is passed through an A N D gate 9m to F, F
The 9n signal CHON is inverted and outputted to 1 level, and
A chime set state is set in which the gate 19b is opened.

Therefore, when the hour detection circuit 17 detects the hour on the time counter section 12a in this state, the AND gate 19b allows the hour detection signal to pass by the 1-level signal CHON, so the buzzer 21 is activated by the buzzer drive circuit. 20.

In addition, in this chime set state, signal 10I)
As the output signal of ANI) reaches level 14, the ANI gates 10C to 10e allow each output signal (1-C3) of the chime-on signal circuit 10a to pass through.

Therefore, in synchronization with the frequency-divided signal P2, signals that sequentially become I (1 to C3 are OR, and mark signals MAI, MM H1, M1 are output through gates 10j, 10k and 10m)
33, and furthermore, this le is output as inverter 1.
Since the output signal of 0g has a level of 17, each mark signal MAI to MA3, mark signal M H1 to MB3, and mark signal M4 from the mark control circuit 10 is output as a signal with a logic level as shown in Table 3 below. be done.

Furthermore, mark signals MAI~M, A3, mark signals M
Bl-M 133 and the mark signal M4 are supplied to the segment driver 15, and C115a-151, the outer segment drivers 15g1 to 15gn or the inner segment drivers 15h1 to 15h11, and the character segment driver 151 select the t1 segment. / segment signal D a ] ~ I) a 20 , segment signal D
I)] -1,) b 20 and segment signal P a
7 outputs signals as shown in Table 4 below.
Therefore, when the signal CI = H level, the signal in Fig. 8 (I)),
When the signal C''2 is at II level, the signal shown in FIG. 8 (1';
), when the signal C"3 = If level, CF in Figure 8
), the respective patterns are displayed cyclically on the display device 1 as shown in Figure 8 (1). ,(E)
, CF ) on the liquid crystal cell surface as shown in Figure 9 ■, Oθ
) is induced, and an electric field signal of 2nH2 is induced for 1 second, 2 seconds, 1
A rate measuring device with a 0-second gate can be used to accurately measure the rate.

Next, each time the leads 2 are pushed to the second stable position M and then returned to the first stable position N, the same JQ+ is applied to the falling edge of the signal Mll, and the narrow pulse signal is output from the pulse generator 9a. S I) is output, and I
By reversing the P/D 9p, you can alternately switch between chime ringing and non-ringing.

In addition, FIG. 9 shows the 2nl generated from the liquid crystal cell surface in the frequency divided signal P3 in the alarm mode and chime mode.
1z (n is an integer) is a time chart showing each electric field signal, and FIG. 9G) is a display indicating the OFF state in alarm mode or chime mode (i.e., FIG. 8([3) or FIG. 8(C)] ), the waveform in Figure 7 and the waveform in Figure 7 (' o m 2 and 0) combined waveform ((!E
) −Com m 2 ) is 2°+17. Shows electric field signal.

Figure 9 @ shows the waveforms in Figure 7 that occur when the chime mode is displayed to indicate the ON state (i.e., Figures 8 (D), (E), and (I)). Combined waveform with Com 1 (■ - Com ] ) - (: certain 2 n
l1z (128Hz) ノ is shown in the world fi number.

Figure 9 ○ indicates the waveform ■ in Figure 7 and the waveform Co in Figure 7 that occurs when the chime mode is displayed to indicate the ON state (i.e., Figure 8 (I)), (E), and (F)). 2°1lz (128
Hz) electrical signal.

As described above, according to the present invention, an electric field signal of 2" Ilz is induced on the liquid crystal cell surface simply by controlling the alarm non-setting, chime cent, and non-setting mark information signals for each common signal. Alarm (J I”F
By selecting the mode or chime mode, it is possible to measure the rate with any rate measuring device, making maintenance on the market very easy. Furthermore, by sharing the mark information with the display orientation in which the time information is displayed, it is possible to provide a complete and well-designed clock.

[Brief explanation of drawings]

FIG. 1 is a plan view showing the external appearance of an electronic timepiece that is an embodiment of the present invention, FIG. 2 (A) is a plan view of a three-part matrix display device that is an embodiment of the present invention, and FIG. 2 (13) is shown in Figure 2 (
A) K1 - A top view showing the formed segment electrodes viewed from the display surface side; 3 is a block diagram of an electronic timepiece according to an embodiment of the present invention, FIG. 4 is a circuit diagram of the switch control circuit shown in FIG. 3, and FIG. FIG. 3 is a circuit diagram of the mark control circuit shown in FIG. 3, FIG. 6 is a circuit diagram of the segment driver shown in FIG. 3, FIG. 7 is a time chart showing the main voltage waveforms in FIG. 3, and FIGS. (F) is Figure 2 (A)
FIG. 9 is a time chart showing the waveform of an electric field signal emitted from above the liquid crystal cell. 1...Display device, 2-1...Leads,
6 ・Crystal oscillation circuit, 4... ・Frequency division circuit, 6-8・
- Switch, 9 - Switch control circuit, 10... Mark control circuit, 11... Timing signal generation circuit, 12... Open circuit, 12a... Time counter section, 12b - Alarm counter section , 16 switching circuit, 14... decoder, 15...
Segment driver, 16... Common driver, 17... Hourly detection circuit, 18...-Several output circuit, 19... Ringing control circuit, (
20. ・Buzzer drive circuit, 21. ・Buzzer, (Figure 1 Figure 9

Claims (1)

[Claims] A crystal oscillator circuit, a frequency dividing circuit, a timing signal generation circuit that receives the frequency divided signal from the frequency dividing circuit and outputs each timing signal, a time counting circuit consisting of a time counter section and an alarm counter section, and the time counting circuit. a switching circuit that selectively outputs the time content or alarm time content; a decoder that takes the content from the switching circuit as input and converts it into a code signal for displaying the content as a guide; A signal that inputs each signal to modify each content of the clock circuit, a mode signal that selects time mode, alarm mode, and chime mode, a signal that sets the alarm to sound/non-sound, and a signal that sets the chime to sound/non-sound. a mark control circuit that receives the various signals from the switch control circuit and outputs a plurality of mark signals; and a mark control circuit that receives the code signal from the decoder and each mark signal from the mark control circuit. a segment driver, a common driver that receives each timing signal from the timing signal generation circuit as input and outputs a plurality of common signals, and a multi-segment display device that receives each of the common signals and each of the segment signals. , each set information of the alarm non-sounding set or the chime sounding/non-sounding set is displayed on the display device by turning on or off for each of the common signals, and an electric field signal of 2 nHz (n is an integer) is transmitted from the display device. An electronic clock characterized by being configured to emit