JPH0354471B2 - - Google Patents

Info

Publication number
JPH0354471B2
JPH0354471B2 JP17207282A JP17207282A JPH0354471B2 JP H0354471 B2 JPH0354471 B2 JP H0354471B2 JP 17207282 A JP17207282 A JP 17207282A JP 17207282 A JP17207282 A JP 17207282A JP H0354471 B2 JPH0354471 B2 JP H0354471B2
Authority
JP
Japan
Prior art keywords
metal
thermal conductivity
thermal expansion
semiconductor device
buffer plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP17207282A
Other languages
Japanese (ja)
Other versions
JPS5961052A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17207282A priority Critical patent/JPS5961052A/en
Publication of JPS5961052A publication Critical patent/JPS5961052A/en
Publication of JPH0354471B2 publication Critical patent/JPH0354471B2/ja
Granted legal-status Critical Current

Links

Description

【発明の詳細な説明】 (イ) 産業上の利用分野 本発明は半導体装置、特にパワー半導体素子を
組込んだ半導体装置の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to improvements in semiconductor devices, particularly semiconductor devices incorporating power semiconductor elements.

(ロ) 従来技術 従来第1図に示す如く、銅等のステム1上に銅
のヒートシンク2およびモリブデン板3を介して
シリコンパワー半導体素子4を固着していた。こ
れは銅とシリコンの熱膨張率が著しく異なり、温
度サイクルによつて半導体素子4を固着するろう
材にクラツクが発生してしまう欠点があり、シリ
コンと熱膨張率のほぼ等しいモリブデン板3によ
りクラツクの発生を防止しているのである。
(b) Prior Art Conventionally, as shown in FIG. 1, a silicon power semiconductor element 4 has been fixed onto a stem 1 made of copper or the like via a copper heat sink 2 and a molybdenum plate 3. This has the disadvantage that the thermal expansion coefficients of copper and silicon are significantly different, and cracks occur in the brazing material that fixes the semiconductor element 4 due to temperature cycles. This prevents the occurrence of

しかしながら斯上した従来の構造ではクラツク
の発生は低減できるが、モリブデン板3が高価で
あり且つ半導体素子4を固着できる様に銀メツキ
等の表面処理が必要となり、コストアツプとなる
欠点があつた。またモリブデン板3の介在により
半導体素子4からステム1までの熱抵抗が増加す
る欠点もある。
However, although the above-mentioned conventional structure can reduce the occurrence of cracks, it has the drawback that the molybdenum plate 3 is expensive and requires surface treatment such as silver plating so that the semiconductor element 4 can be fixed, resulting in an increase in cost. Another disadvantage is that the presence of the molybdenum plate 3 increases the thermal resistance from the semiconductor element 4 to the stem 1.

そこで本発明者はコストダウンを図るため、モ
リブデン板の代りにインバー(ニツケル36%、鉄
64%の合金)を用いた。即ち第2図に示す如く、
ステム1上にヒートシンク2およびインバー5を
介してシリコンパワー半導体素子4を固着する構
造とした。インバーは第8図から明らかな様にモ
リブデンの約1/3の熱膨張率であり、熱膨張につ
いてはモリブデンより好結果を得られる。しかし
熱伝導度はモリブデンの約1/10以下であり良好な
放熱効果は期待できない。銅のヒートシンク2上
に半導体素子4を直接固着した場合の放熱効果を
1とすると、モリブデン板3を介した場合は0.75
となり、インバー5を介した場合は0.28となる。
従つて第2図の構造は放熱効果の点で実現できな
いのである。
Therefore, in order to reduce costs, the inventor of the present invention replaced the molybdenum plate with invar (nickel 36%, iron plate).
64% alloy) was used. That is, as shown in Figure 2,
A structure was adopted in which a silicon power semiconductor element 4 was fixed onto a stem 1 via a heat sink 2 and an invar 5. As is clear from FIG. 8, Invar has a coefficient of thermal expansion that is approximately 1/3 that of molybdenum, and can obtain better results than molybdenum in terms of thermal expansion. However, its thermal conductivity is about 1/10 or less than that of molybdenum, so good heat dissipation effects cannot be expected. If the heat dissipation effect when the semiconductor element 4 is directly fixed on the copper heat sink 2 is 1, then when it is via the molybdenum plate 3, it is 0.75.
If it goes through Invar 5, it becomes 0.28.
Therefore, the structure shown in FIG. 2 cannot be realized in terms of heat dissipation effect.

(ハ) 本発明の目的 本発明の第1の目的は熱膨張率の小さい且つ熱
伝導度の大きい緩衝板を実現することにある。
(C) Objective of the present invention The first objective of the present invention is to realize a buffer plate with a low coefficient of thermal expansion and high thermal conductivity.

本発明の第2の目的は熱膨張率の小さい且つ熱
伝導度の大きい緩衝板を安価な材料で実現するこ
とにある。
A second object of the present invention is to realize a buffer plate with a low coefficient of thermal expansion and high thermal conductivity using inexpensive materials.

(ニ) 本発明の構成 本発明に依る半導体装置は第7図に示す如く、
熱伝導性良好な金属板11上に銅等のヒートシン
ク12を介してシリコンパワー半導体素子14を
固着する構造に於いて、分割した良熱伝導性金属
を熱膨張係数の小さい金属で囲んで形成した緩衝
板13を設けることに特徴を有している。
(d) Structure of the present invention The semiconductor device according to the present invention is as shown in FIG.
In a structure in which a silicon power semiconductor element 14 is fixed on a metal plate 11 with good thermal conductivity via a heat sink 12 made of copper or the like, a divided metal with good thermal conductivity is surrounded by a metal with a small coefficient of thermal expansion. The feature is that a buffer plate 13 is provided.

(ホ) 本発明の実施例 本発明の特徴とする緩衝材について詳述する。
第3図および第4図にその第1の実施例を示す。
本実施例では銅の如き良熱伝導性金属21とイン
バーの如き熱膨張係数の小さい金属22を同心状
に交互に配置して緩衝板13を形成する。斯る緩
衝板13は銅の円柱状の芯材に径の異なるインバ
ーと銅の円筒を交互に密着して挿入したものをス
ライスして製造する。この緩衝板13上には点線
で示す如くシリコンパワー半導体素子14が固着
される。本実施例では銅とインバーとをほぼ同一
幅にし、両者を等面積としている。
(e) Examples of the present invention The cushioning material, which is a feature of the present invention, will be described in detail.
The first embodiment is shown in FIGS. 3 and 4.
In this embodiment, the buffer plate 13 is formed by alternately arranging a metal 21 having good thermal conductivity such as copper and a metal 22 having a small coefficient of thermal expansion such as invar in a concentric manner. Such a buffer plate 13 is manufactured by slicing a cylindrical copper core material into which invar and copper cylinders of different diameters are alternately inserted in close contact with each other. A silicon power semiconductor element 14 is fixed on this buffer plate 13 as shown by dotted lines. In this embodiment, the copper and invar have approximately the same width and have the same area.

第5図および第6図に第2の実施例を示す。本
実施例では銅の如き良熱伝導性金属21を碁盤状
に配置し、その間にインバーの如き熱膨張係数の
小さい金属22を格子状に配置して緩衝板13を
形成する。斯る緩衝板13は格子状のインバーに
圧延により銅を嵌合させて製造する。この緩衝板
13上には点線で示す如くシリコンパワー半導体
素子14が固着される。
A second embodiment is shown in FIGS. 5 and 6. In this embodiment, the buffer plate 13 is formed by arranging metals 21 with good thermal conductivity such as copper in a grid pattern, and metals 22 with a small coefficient of thermal expansion such as invar in a lattice pattern between them. Such a buffer plate 13 is manufactured by fitting copper into a lattice-shaped invar by rolling. A silicon power semiconductor element 14 is fixed on this buffer plate 13 as shown by dotted lines.

上述した緩衝板13は第7図に示す如く、ステ
ム等の金属板11上に固着された銅等のヒートシ
ンク12のくぼみに埋設され、この緩衝板13上
にシリコンパワー半導体素子14が固着される。
As shown in FIG. 7, the above-mentioned buffer plate 13 is embedded in a recess of a heat sink 12 made of copper or the like fixed on a metal plate 11 such as a stem, and a silicon power semiconductor element 14 is fixed onto this buffer plate 13. .

斯上の構造に於いては、シリコンパワー半導体
素子14からの発熱は緩衝板13の銅よりなる分
割した良熱伝導性金属21を通して放熱され、一
方良熱伝導性金属21の大きい熱膨張はインバー
よりなる熱膨張係数の小さい金属22で囲むこと
により少く抑えることができる。この結果良熱伝
導性金属21の熱膨張は横方向ではなく上下方向
のみに限られ、半導体素子14のろう材に加わる
ストレスを最少限にとどめられる。具体的には銅
のヒートシンク12上に半導体素子14を直接固
着した場合の放熱効果を1とすると、本発明の構
造では0.85となり、これは前述したインバーを介
した構造の約3倍ほど放熱性を向上できる。
In the above structure, the heat generated from the silicon power semiconductor element 14 is radiated through the divided good heat conductive metal 21 made of copper of the buffer plate 13, while the large thermal expansion of the good heat conductive metal 21 is caused by an inverter. It can be suppressed by surrounding it with a metal 22 having a small coefficient of thermal expansion. As a result, the thermal expansion of the highly thermally conductive metal 21 is limited only in the vertical direction, not in the lateral direction, and the stress applied to the brazing material of the semiconductor element 14 can be kept to a minimum. Specifically, if the heat dissipation effect when the semiconductor element 14 is directly fixed on the copper heat sink 12 is 1, then the structure of the present invention has a heat dissipation effect of 0.85, which is about three times as much as the above-mentioned structure using Invar. can be improved.

(ヘ) 効果 本発明に依れば熱伝導性の良い金属と熱膨張性
の小さい金属を組み合せることにより容易に熱伝
導性が良く且つ熱膨張の小さい緩衝材を実現でき
る。しかもインバーを用いると銅とインバーとの
組み合せで安価な緩衝材を提供できる。
(f) Effects According to the present invention, by combining a metal with good thermal conductivity and a metal with low thermal expansion, a cushioning material with good thermal conductivity and low thermal expansion can be easily realized. Moreover, by using Invar, an inexpensive cushioning material can be provided by combining copper and Invar.

なおインバーの代りにモリブデンあるいはタン
グマテンを用いても本発明の目的を十分達成でき
モリブデン板を用いる場合よりも安価で且つ放熱
性が良くなる。
Note that even if molybdenum or tungmate is used instead of invar, the object of the present invention can be sufficiently achieved, and the cost will be lower and the heat dissipation will be better than when a molybdenum plate is used.

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図は従来例を説明するための
断面図、第3図は本発明に用いる緩衝板の一実施
例を説明する上面図、第4図は第3図の−線
断面図、第5図は本発明に用いる緩衝板の他の実
施例を説明する上面図、第6図は第5図の−
線断面図、第7図は本発明を説明する断面図、第
8図は熱膨張率および熱伝導度を説明する表であ
る。 主な図番の説明、11は良熱伝導性金属板、1
2は銅のヒートシンク、13は本発明の特徴とす
る緩衝板、14は半導体素子である。
1 and 2 are cross-sectional views for explaining the conventional example, FIG. 3 is a top view for explaining one embodiment of the buffer plate used in the present invention, and FIG. 4 is a cross-sectional view taken along the line -- in FIG. 3. , FIG. 5 is a top view illustrating another embodiment of the buffer plate used in the present invention, and FIG.
A line sectional view, FIG. 7 is a sectional view explaining the present invention, and FIG. 8 is a table explaining the coefficient of thermal expansion and thermal conductivity. Explanation of main drawing numbers, 11 is a metal plate with good thermal conductivity, 1
2 is a copper heat sink, 13 is a buffer plate which is a feature of the present invention, and 14 is a semiconductor element.

Claims (1)

【特許請求の範囲】 1 熱伝導性良好な金属板上にシリコンパワー半
導体素子を固着する半導体装置に於いて、前記金
属板とパワー半導体素子間に分割した良熱伝導性
金属を熱膨張係数の小さい金属で囲んで形成した
緩衝板を設けることを特徴とする半導体装置。 2 特許請求の範囲第1項に於いて、前記良熱伝
導性金属と熱膨張係数の小さい金属とを交互に同
心状に配置した緩衝板とすることを特徴とする半
導体装置。 3 特許請求の範囲第1項に於いて、前記良熱伝
導性金属を飛石状に配置し前記熱膨張係数の小さ
い金属を格子状にした緩衝板とすることを特徴と
する半導体装置。 4 特許請求の範囲第1項に於いて、前記良熱伝
導性金属として銅を用い、前記熱膨張係数の小さ
い金属としてインバーを用いることを特徴とする
半導体装置。
[Scope of Claims] 1. In a semiconductor device in which a silicon power semiconductor element is fixed on a metal plate with good thermal conductivity, a metal with good thermal conductivity divided between the metal plate and the power semiconductor element has a coefficient of thermal expansion. A semiconductor device characterized by providing a buffer plate surrounded by a small metal. 2. A semiconductor device according to claim 1, wherein the semiconductor device is a buffer plate in which the metal with good thermal conductivity and the metal with a small coefficient of thermal expansion are alternately arranged concentrically. 3. A semiconductor device according to claim 1, wherein the semiconductor device is a buffer plate in which the metal with good thermal conductivity is arranged in the form of stepping stones and the metal with a small coefficient of thermal expansion is arranged in the form of a lattice. 4. The semiconductor device according to claim 1, wherein copper is used as the metal with good thermal conductivity, and invar is used as the metal with a small coefficient of thermal expansion.
JP17207282A 1982-09-29 1982-09-29 Semiconductor device Granted JPS5961052A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17207282A JPS5961052A (en) 1982-09-29 1982-09-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17207282A JPS5961052A (en) 1982-09-29 1982-09-29 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5961052A JPS5961052A (en) 1984-04-07
JPH0354471B2 true JPH0354471B2 (en) 1991-08-20

Family

ID=15935017

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17207282A Granted JPS5961052A (en) 1982-09-29 1982-09-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5961052A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2505065B2 (en) * 1990-10-04 1996-06-05 三菱電機株式会社 Semiconductor device and manufacturing method thereof
JPH06125023A (en) * 1992-10-14 1994-05-06 Kyocera Corp Semiconductor device

Also Published As

Publication number Publication date
JPS5961052A (en) 1984-04-07

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