JPS60180130A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60180130A
JPS60180130A JP3668084A JP3668084A JPS60180130A JP S60180130 A JPS60180130 A JP S60180130A JP 3668084 A JP3668084 A JP 3668084A JP 3668084 A JP3668084 A JP 3668084A JP S60180130 A JPS60180130 A JP S60180130A
Authority
JP
Japan
Prior art keywords
buffer plate
metal
inver
height
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3668084A
Other languages
Japanese (ja)
Inventor
Hisashi Shimizu
清水　永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP3668084A priority Critical patent/JPS60180130A/en
Publication of JPS60180130A publication Critical patent/JPS60180130A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To realize a buffer plate having a small thermal expansion coefficient and a large thermal conductivity by providing a buffer plate, consisting of a good heat conductive metal of which center is formed like a height and a metal having almost the same thermal expansion coefficient as silicon which surrounds said height and forms flat surface, between a metal plate and a power semiconductor element. CONSTITUTION:A power semiconductor element 15 is welded on a metal plate 11 having a good heat conductivity like copper through a buffer plate 12. The buffer plate 12 is composed of a good heat conductive metal 14 of which center is formed like a height and an inver 13 which surrounds said height 16 and forms the flat surface. The inver 13 has the thermal expansion coefficient which is almost equal that of silicon. The inver 13 surrounds the height 16 and forms the flat surface in matching with the upper surfaces of height 16 and inver 13. The good heat conductive metal 14 and inver 13 are integrated by the brazing, forming a flat buffer plate 12. Thereby, the buffer plate 12 can be formed with an economical material such as copper and inver and the buffer plate 12 which is just suitable for mass-production can be realized.

Description

【発明の詳細な説明】 （イ）産業上の利用分野 本発明は半導体装置、特にパワー半導体素子を組込んだ
半導体装置の改良に関する。　′（ロ）従来技術 従来第１図に示す如く、銅等のステム（１１上に銅のヒ
ートシンク（２）およびモリブデン板（３）を介してシ
リコンパワー半導体素子（４）を固着していた。これは
鋼とシリコンの熱膨張率が著しく異なり、温度サイクル
によって半導体素子（４）を固着するろう材にクラック
が発生してしまう欠点があり、シリコンと熱膨張率のほ
ぼ等しいモリブデン板（３）によりクラックの発生を防
止しているのである。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to improvements in semiconductor devices, particularly semiconductor devices incorporating power semiconductor elements. (b) Prior Art As shown in FIG. 1, a silicon power semiconductor element (4) was fixed onto a stem (11) of copper or the like via a copper heat sink (2) and a molybdenum plate (3). This has the drawback that the coefficient of thermal expansion of steel and silicon is significantly different, and cracks occur in the brazing material that fixes the semiconductor element (4) due to temperature cycles. This prevents the occurrence of cracks.

斯る従来技術として例えば特開昭５１−６６７２号公報
等が知られている。As such a conventional technique, for example, Japanese Unexamined Patent Publication No. 51-6672 is known.

しかしながら斯上した従来の構造ではクラックの発生は
低減できるが、モリブデン板（３）が高価であり且つ半
導体素子（４）を固着できる様に銀メッキ等の表面処理
が必要となり、コストアップとなる欠点があった。また
モリブデン板（３）の介在により半導体素子（４）から
ステム（１）までの熱抵抗が増加する欠点もある。However, although the conventional structure described above can reduce the occurrence of cracks, the molybdenum plate (3) is expensive and requires surface treatment such as silver plating to fix the semiconductor element (4), which increases costs. There were drawbacks. Another disadvantage is that the presence of the molybdenum plate (3) increases the thermal resistance from the semiconductor element (4) to the stem (1).

そこで本発明者はコストダウンを図るため、モリブテン
板の代りにインバーにッケル３６％、鉄６４％の合金）
を用いた。即ち第２図に示す如く、ステム（１１上にヒ
ートシンク（２１おヨヒインバー（５）を介してシリコ
ンパワー半導体素子（４）を固層する構造とした。イン
バーは第４図から明らかな様にモリブデンの約１の熱膨
張率であり、熱膨張についてはモリブデンより好結果を
得られる。しかし熱伝導度はモリブデンの約１以下であ
り良好な１０ 放熱効果は期待できない。銅のヒートシンク（２）上に
半導体素子（４）を直接固着した場合の放熱効果を１と
すると、モリブデン板（３）を介した場合は０．７５と
なり、インバー（５）を介した場合は０．２８となる。Therefore, in order to reduce costs, the present inventors replaced the molybdenum plate with an alloy of 36% Invar and 64% iron.
was used. That is, as shown in FIG. 2, a silicon power semiconductor element (4) is solidly layered on the stem (11) via a heat sink (21) and an invar (5).As is clear from FIG. It has a coefficient of thermal expansion of about 1, which gives better results than molybdenum in terms of thermal expansion.However, the thermal conductivity is about 1 or less than that of molybdenum, so a good heat dissipation effect cannot be expected.On the copper heat sink (2) If the heat dissipation effect is 1 when the semiconductor element (4) is directly fixed to the substrate, it is 0.75 when the semiconductor element (4) is directly fixed to the substrate, and it is 0.28 when the semiconductor element (4) is attached via the molybdenum plate (3).

従って第２図の構造は放熱効果の点で実現できないので
ある。Therefore, the structure shown in FIG. 2 cannot be realized in terms of heat dissipation effect.

（ハ）発明の目的 本発明の第１の目的は熱膨張率の小さい且つ熱伝導度の
大きい緩衝板を実現することにある。(c) Purpose of the Invention The first purpose of the present invention is to realize a buffer plate with a low coefficient of thermal expansion and high thermal conductivity.

本発明の第２の目的はヒートサイクルに強い緩衝板を実
現することにある。A second object of the present invention is to realize a buffer plate that is resistant to heat cycles.

に）発明の構成 本発明に依る半導体装置は第３図に示す如く、熱伝導性
良好な金属板θυ上にシリコンパワー半導体素子θ艶を
固着する半導体装置に於いて、金属板０］）とパワー半
導体素子（１５）間に中央部を台地状にした良熱伝導性
金属０４）と該台地を囲み且つ平担上面を形成するシリ
コンと熱膨張係数の略等しい金属０島より成る緩衝根囲
を設けて構成される。2) Structure of the Invention As shown in FIG. 3, the semiconductor device according to the present invention is a semiconductor device in which a silicon power semiconductor element θ is fixed on a metal plate θυ having good thermal conductivity. A buffer wall surrounding the power semiconductor elements (15) consisting of a metal 04) with good thermal conductivity with a plateau shape in the center and a metal island with a coefficient of thermal expansion substantially equal to that of silicon surrounding the plateau and forming a flat upper surface. It is configured by providing.

（ホ）実施例 本発明に依る一実施例を第３図を参照して説明する。(e) Examples An embodiment according to the present invention will be described with reference to FIG.

本実施例では銅等の熱伝導性良好な金属板（１１）上に
本発明の特徴とする緩衝板０りを介してパワー半導体素
子α艶を固着している。In this embodiment, a power semiconductor element α is fixed on a metal plate (11) having good thermal conductivity, such as copper, through a buffer plate, which is a feature of the present invention.

緩衝板（１３４ま中央部を台地状にした良熱伝導性金属
０４）と台地０６）を囲み且つ平担上面を形成するイン
バー（１３）より構成される。インバー（１３）は第４
図から明らかな様にシリコンとその熱膨張率を略等しく
している。良熱伝導性金属（１４）は中央部を肉厚とし
円形または正方形状の台地０６）を形成する。インバー
（１３＋は台地（Ｉ６）の周囲を囲み、台地（国の上面
とインバー０３）の上面とを一致させて平担上面を形成
する。It is composed of a buffer plate (134), which is a highly thermally conductive metal 04 with a plateau-like central portion, and an invar (13) surrounding the plateau (06) and forming a flat upper surface. Invar (13) is the fourth
As is clear from the figure, the coefficient of thermal expansion is approximately equal to that of silicon. The highly thermally conductive metal (14) has a thick central portion to form a circular or square plateau 06). Invar (13+) surrounds the plateau (I6) and forms a flat top surface by aligning the top surface of the plateau (the top surface of the country and the top surface of Invar 03).

この結果良熱伝導性金属ＬＩ４＋とインバー（１：勺と
はろう付けされて一体となり、平板状の緩衝板Ｑ２１Ｙ
構成する。即ち緩衝板（１り上面中央部に良熱伝導性金
属０４）が露出している。そしてこの艮熱伝纒性金属圓
は固着されるパワー半導体素子（１〜により完全に仮構
される大きさに設ｎ士されている。As a result, the good thermal conductive metal LI4+ and Invar (1: 1) are brazed and integrated, and a flat buffer plate Q21Y is formed.
Configure. That is, the buffer plate (metal 04 with good thermal conductivity at the center of the upper surface) is exposed. This heat conductive metal ring is sized to be completely temporarily constructed by the power semiconductor element (1 to 1) to which it is fixed.

斯上した本発明の構造に依ればヒートサイクルを繰り返
して行ってもろう材のクランクおよび酸化に伴うシリコ
ンパワー半導体素子の劣化を防止できる。即ちインバー
（１３１と良熱伝導性金属（１４）のろう付は面はヒー
トサイクルによるクラックの発生−酸化によりろう材の
劣化は進行する。シリコンパワー半導体素子（国とイン
バー（１３１とのろう付は面は熱膨張係数が等しいので
ヒートサイクルによるろう材の劣化は防止できる。また
シリコンパワー半導体素子０ωと良熱伝導性金属０４）
とのろう付は面は熱膨張係数の違いによりクラックは発
生するが、インバー０３１に囲まれているのでろう羽の
酸化はしない。この結果パワー半導体素子０５）のろう
付は面では良熱伝導性金属０４）との接触面でクランク
は発生するがろう材の酸化は防止でき、シリコンパワー
半導体素子Ｑ５１のろう材の劣化を防止できる。そして
放熱は良熱伝導性金属Ｑ４１より良好に行なえる。According to the structure of the present invention described above, it is possible to prevent deterioration of the silicon power semiconductor element due to cranking of the brazing material and oxidation even if heat cycles are repeated. In other words, when brazing Invar (131) and a metal with good thermal conductivity (14), cracks occur on the surface due to heat cycles - deterioration of the brazing material progresses due to oxidation. Since the surfaces have the same coefficient of thermal expansion, deterioration of the brazing filler metal due to heat cycles can be prevented.Also, silicon power semiconductor element 0ω and good thermal conductive metal 04)
When brazing with the wire, cracks will occur on the surface due to the difference in coefficient of thermal expansion, but since it is surrounded by Invar 031, the solder blades will not oxidize. As a result, when brazing power semiconductor element 05), cranking occurs at the contact surface with metal 04), which has good thermal conductivity, but oxidation of the brazing material can be prevented, and deterioration of the brazing material of silicon power semiconductor element Q51 can be prevented. can. And heat dissipation can be performed better than the good heat conductive metal Q41.

（へ）発明の効果 本発明に依れば緩衝板ｕｉｒと中央に台地ｔｔｅを有す
る良熱伝導性金属α４）とそれを囲み平担上面を有する
インバー０．１１で形成することにより、シリコンパワ
ー半導体素子０句の固着をするろう材の劣化を有効に抑
制できる良好な緩衝板（ｌ渇を実現できる。(F) Effects of the Invention According to the present invention, silicon power A good buffer plate that can effectively suppress the deterioration of the brazing filler metal that fixes the semiconductor elements.

また本発明に依る緩衝板０２は銅、インバー等の安価な
材料で形成でき、極めて量産に適する緩衝板（１２１を
実現できる。Further, the buffer plate 02 according to the present invention can be formed of an inexpensive material such as copper or invar, and can realize a buffer plate (121) that is extremely suitable for mass production.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図および第２図は従来の半導体装置を説明する断面
図、第３図は本発明の半導体装置を説明する断面図、第
４図は熱膨張率および熱伝導度を説明する図である。 Ｑｌ）は金属板、　ａ４は緩衝板、　Ｈはインバー、０
４）は良熱伝導性金属、　（Ｉ５）はパワー半導体素子
、Ｑ６１は台地である。 出願人　三洋電機株式会社　外１名 代坤人　弁理士　佐　野　靜　夫FIGS. 1 and 2 are cross-sectional views for explaining a conventional semiconductor device, FIG. 3 is a cross-sectional view for explaining a semiconductor device of the present invention, and FIG. 4 is a view for explaining thermal expansion coefficient and thermal conductivity. . Ql) is a metal plate, a4 is a buffer plate, H is invar, 0
4) is a metal with good thermal conductivity, (I5) is a power semiconductor element, and Q61 is a plateau. Applicant: SANYO Electric Co., Ltd., 1st representative Patent attorney: Shizuo Sano

Claims (1)

【特許請求の範囲】[Claims] （１）熱伝導性良好な金属板上にシリコンパワー半導体
素子を固着する半導体装置に於いて、前記金属板とパワ
ー半導体素子間に中央部を台地状にした良熱伝導性金属
と該台地を囲み且つ平担上面を形成するシリコンと熱膨
張係数の略等しい金属より成る緩衝板を設けることを特
徴とする半導体装置。(1) In a semiconductor device in which a silicon power semiconductor element is fixed on a metal plate with good thermal conductivity, a metal plate with good thermal conductivity and a plateau-like central part is provided between the metal plate and the power semiconductor element. 1. A semiconductor device comprising a buffer plate made of a metal having a coefficient of thermal expansion substantially equal to that of silicon that surrounds and forms a flat upper surface.
JP3668084A 1984-02-27 1984-02-27 Semiconductor device Pending JPS60180130A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3668084A JPS60180130A (en) 1984-02-27 1984-02-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3668084A JPS60180130A (en) 1984-02-27 1984-02-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60180130A true JPS60180130A (en) 1985-09-13

Family

ID=12476561

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3668084A Pending JPS60180130A (en) 1984-02-27 1984-02-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60180130A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4907067A (en) * 1988-05-11 1990-03-06 Texas Instruments Incorporated Thermally efficient power device package
US5053855A (en) * 1988-10-25 1991-10-01 Mitsubishi Denki Kabushiki Kaisha Plastic molded-type semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4907067A (en) * 1988-05-11 1990-03-06 Texas Instruments Incorporated Thermally efficient power device package
US5053855A (en) * 1988-10-25 1991-10-01 Mitsubishi Denki Kabushiki Kaisha Plastic molded-type semiconductor device

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