JPH0352916B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a pulse modulation type photoelectric switch that detects the presence or absence of a person or object based on the presence or absence of light shielding between a light emitter and a receiver. This paper relates to preventing malfunctions in so-called asynchronous photoelectric switches, which cannot be known on the device side.

Conventional technology Photoelectric switches are used to control the opening and closing of automatic doors and to detect the presence or absence of moving workpieces and equipment in factories.
There is a direct current method that uses continuous light, and a pulse modulation method that uses pulsed intermittent light and determines whether the light is received or blocked based on the number of times it is received, but they are less susceptible to noise such as ambient light. For this reason, pulse modulation systems are often used.

In the above pulse modulation method, the output of the light receiving element is generally selectively taken out using a gate circuit that opens in synchronization with the light emission timing of the light emitting element. This is called a synchronous type, and has the effect of not accepting noise due to disturbance light input outside the gate period.

However, due to restrictions such as installation location, the light projector and light receiver must be installed apart from each other, and the light receiver may not be able to know the light emission timing of the light projecting element. In this case, a so-called asynchronous photoelectric switch is used. This asynchronous photoelectric switch normally integrates the number of received light pulses, and when the integrated amount reaches a predetermined value, it detects that a predetermined number of consecutive received light pulses have been input, and determines whether it is in the light receiving state or is blocked. Determining whether the status is

Problems to be Solved by the Invention When the above-mentioned asynchronous photoelectric switch receives noise superimposed with high frequencies generated due to the interrupting operation of an electromagnetic switch, the integrating circuit becomes saturated in a short period of time, causing a false judgment. There are things to do.

Furthermore, some of the asynchronous photoelectric switches mentioned above perform an integrating operation while performing so-called period verification, in which it is determined that the light receiving element is in the light receiving state when the light receiving element receives light at a period corresponding to the light emitting period. A photoelectric switch equipped with this period detection circuit has the effect of not accepting non-periodic noise. However, if noise with superimposed high frequencies occurs at time intervals close to the light projection period, or if this noise occurs in the time width necessary for the integrating circuit to determine light reception, the light reception determination operation will still be incorrect.

In addition, as a device to prevent malfunctions due to noise contamination, the invention of Utility Model Application Publication No. 53-112780 and the
There is an invention disclosed in Publication No. 57-70477.

However, in the former device, if high-frequency noise is mixed in during light reception, an erroneous output of light blocking occurs even though light is being received. Also, in the latter invention, if high frequency noise of a certain number of pulses or more continuously enters during light shielding, an erroneous output is generated that determines that light has been received.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a photoelectric switch that does not malfunction even when noise with superimposed high frequencies is input.

Means for Solving the Problems The present invention was made to eliminate the above-mentioned malfunction of an asynchronous photoelectric switch that occurs when noise with superimposed high frequencies is input, and consists of the following configuration means.

That is, the present invention uses a light receiving element that receives light emitted from a light emitting element at a predetermined period and generates a light receiving pulse, and integrates the received light pulse and determines whether the integrated amount reaches a predetermined value or not. A photoelectric switch is equipped with an integrating circuit that determines whether the light is in the light-blocking state or in the light-receiving state and outputs the result.The light-receiving pulses are counted and reset at predetermined intervals, and during that time, the counted number is determined when the light is not in the light-blocking state. A noise pulse detector equipped with a noise pulse detector that stops the judgment operation while retaining the judgment result at that point when the number of pulses received from the optical element exceeds a predetermined set value. It is.

Example A specific example in which the present invention is implemented in a photoelectric switch having an integrating circuit with a period verification function is as follows.
This will be explained below with reference to the drawings.

In Fig. 1, 1 is a light receiving element such as a phototransistor, 2 is a pulse amplifier, 3 is an amplitude discriminator that extracts a positive signal component above a certain level and outputs it as a received light pulse A, and 4 is a light emitting element such as an LED. ,
5 is a light emitting oscillator that causes the light emitting element 4 to emit pulses at a constant frequency; 6 is an oscillation circuit that outputs a sawtooth oscillation wave; and 7 is an oscillator that outputs a sawtooth wave every time the rise of the sawtooth wave output from the oscillation circuit 6 exceeds a certain level. shifted to
Timing clocks T ₀ , T ₁ , which make one cycle with 16 shots.
...Frequency divider circuit that sequentially generates T ₁₅ repeatedly, 8
is the timing clock _T2 output from the frequency divider circuit 7.
The gate circuit 9 is controlled by the timing clocks T ₀ and T ₁ output from the frequency dividing circuit 7, and is opened when a predetermined number or more of the received light pulses A are continuously input through the gate circuit 8. An integrator circuit 10 that generates the light reception judgment output _Q2 counts the light reception pulses A output from the amplitude discriminator 3, and generates a count-up output B when it counts three pulses before being reset by the timing clock _T0 . A noise pulse detector 11 is a period verification circuit that matches the timing of light reception with the timing of light emission. The light emitting period t of the light projecting element 4 is set to be equal to or slightly smaller than three times the period of generation of one timing clock of the frequency dividing circuit 7. The components of the above circuit will be explained in more detail.

The integrating circuit 9 includes a first flip-flop circuit 12 which is set by the received light pulse A passing through the gate circuit 8 and reset by the timing clock _T1 .
, a second flip-flop circuit 13 that stores and outputs the current judgment state of light reception or light blocking;
and the outputs Q ₁ and Q ₂ of the second flip-flop circuits 12 and 13, and when they match, it becomes “1”.
The timing clock consists of a coincidence detection circuit 14 that generates a coincidence output with a logic level of It is reset by the counter gate 16 that passes the mismatch output C and the match output D at the generation timing of _T0 , and the match output D that has passed through the counter gate 16, and the mismatch output C is countered and the mismatch output C continues. It is inserted and connected between the second AND gate 16b and the clear terminal CR of the second AND gate 16b and the clear terminal CR of the second AND gate 16b, which generates a count-up output _Q7 when seven pulses are input. It consists of a first OR gate 18 that resets the mismatch counter 17 by the count-up output B, and third and fourth AND gates 19a and 19b.
Count-up output of discrepancy counter 17
A data transfer gate 19 which opens when _Q7 occurs and transfers the memory contents of the first flip-flop circuit 12 to the second flip-flop circuit 13, and a data transfer gate 19 which transfers the timing clock _T15 of the frequency divider circuit 7 to the second flip-flop circuit. 13, a second
It is composed of an OR gate 20.

The period test circuit 11 uses a timing clock _T3 .
The fifth AND gate ₂ passes the output Q1 of the first flip-flop circuit 12 at the timing of occurrence of
1, and a third OR gate 22 which calculates the logical sum of the output of the fifth AND gate 21 and the output B of the noise pulse detection circuit 10 and inputs the result to the clear terminal CR of the frequency divider circuit 7. . In order to make the function of the period verification circuit 11 work effectively, the output of the gate circuit 8 is applied to the oscillation circuit 6, and when the received light pulse A is generated during the period of the timing clock _T2 , the oscillation circuit 6 outputs a sawtooth wave. The output period of the frequency divider circuit 7 is temporarily shortened by causing the output of the frequency divider circuit 7 to rise rapidly, and the output of the frequency divider circuit 7 is immediately transferred to the timing block _T3 upon this rise.

Next, the normal operation in which noise superimposed on high frequencies is not input will be described with reference to the timing diagram shown in FIG.

Assuming that the first flip-flop circuit 12 is initially in a reset state and in a light-shielded state,
The frequency dividing circuit 7 operates at a frequency division ratio of 1/16 and sequentially outputs timing clocks T ₀ , T ₁ to T ₁₅ . When the light blocking state changes to the light receiving state and the light receiving element 1 receives light from the light emitting element 4, the amplitude discriminator 3 receives the output of the pulse amplifier 2 and selects the received light pulse A.
occurs. This received light pulse A is counted by the noise pulse detector 10, and when the third received light pulse A is generated, the noise pulse detector 10 generates a count-up output B. This count-up output B passes through the first OR gate 18 and clears the mismatch counter 17, while at the same time
The signal enters the clear terminal CR of the frequency divider circuit 7 through the OR gate 22 and is cleared. Immediately after that, the frequency divider circuit 7 generates a timing clock T ₀ , T ₁ ,
Output T ₂ ... in order.

If the light receiving element ₁ is receiving light when the timing clock T2 is generated, a light receiving pulse A is generated, and the light receiving pulse A is sent to the first flip-flop circuit 12 through the gate circuit 8 which is opened in response to the timing clock _T2 .
is set, and its output _Q1 is set to a logic level of "1". This received light pulse A passes through the gate circuit 8 and is also input to the oscillation circuit 6. Therefore, its output waveform rises rapidly, and in response to this rising input, the frequency divider circuit 7 is shifted and immediately generates the next timing clock _T3 . The reason why the output period of the oscillation circuit 6 is temporarily shortened and the remaining time of the timing clock _T2 is shortened in this way is that the frequency of the pulsed light emission of the light emitting element 4 and the oscillation circuit 6 that shifts the frequency dividing circuit 7 are Although there is a certain relationship with the frequency of be. When the timing clock _T3 occurs, the fifth AND gate 21 opens, so it becomes “1”.
The _Q1 output of the first flip-flop circuit 12, which is at the logic level of
The frequency dividing circuit 7 is cleared through the OR gate 22. Therefore, timing clock _T3 appears instantaneously, and immediately timing clock _T0 occurs. In other words, immediately after the light reception pulse A is generated, the timing clock _T0 is reached.

Since the counter gate 16 is opened by this timing clock _T0 , the output of the logic level "1" of the first flip-flop circuit 12 set by the received light pulse A passing through the gate circuit 8 is output.
Q ₁ and “0” of the second flip-flop circuit 13
The mismatch output C generated due to the mismatch of the logic level output Q ₂ passes through the counter gate 16 and causes the mismatch number counter 17 to count by one. After this, the light receiving element 1 detects the timing clock.
If light is received continuously at the timing of T ₂ ,
By the above-described operation, the mismatch number counter 17 increases its count number by one.

When counting the seventh shot from the beginning, the mismatch counter 17 generates a count-up output _Q7 , which opens the data transfer gate ₁₉ and transfers the memory contents of the first flip-flop circuit 12 to the second flip-flop circuit. Transfer to circuit 13. Then, the output Q2 of the second flip-flop circuit ₁₃ becomes a logic level of "1" indicating the light receiving state. This output Q ₂ is compared with the output Q ₁ of the first flip-flop circuit 12 in the coincidence detection circuit 14 to generate a coincidence output D, so that the mismatch number counter 17 is reset and the count-up output Q ₇ disappears. The seventh light reception pulse A mentioned above
All operations from the occurrence of T0 to the reset of the mismatch counter 17 are performed immediately after the occurrence of the timing clock _T0 .

After this, the light receiving element 1 receives the timing clock T ₂
When light is received at the timing of occurrence of , the logic level output Q1 of the first flip-flop circuit 12 is " ₁ " and the output Q1 of the second flip-flop circuit 13 is "1".
The coincidence detection circuit 14 detects that the logic level output Q ₂ of the output signal 2 coincides with the logic level output Q 2 and generates the coincidence output D, and resets the mismatch count counter 17 at the generation timing of the timing clock T ₀ . The output _Q2 of the flip-flop circuit 13 continues to maintain the logic level of "1" indicating the light receiving state.

However, if the light receiving element 1 does not receive light at the timing of the timing clock _T2 , the first flip-flop circuit 12 will not be set and its output _Q1 will be at the logic level of "0", so that the timing clock _T3 will be generated. Sometimes the divider circuit 7 is not cleared.
The frequency dividing circuit 7 sequentially outputs timing clocks T ₄ and T ₅ to T ₁₅ following the timing clock T ₃ . When timing clock T ₁₅ occurs, it resets the second flip-flop circuit 13 through the second OR gate 20. Then, the output Q ₂ becomes a logic level of "0" indicating a light shielding state.

After this, if the light-shielded state continues and the light-receiving element 1 does not receive light, the light-receiving pulse A will not be generated, so the output _Q1 of the first flip-flop circuit 12 and the output Q2 of the second flip-flop circuit ₁₃ will both be at the logic level of "0". , the coincidence detection circuit 14 generates a coincidence output D and continues to reset the mismatch count counter 17, so that the output of the second flip-flop circuit 13
_Q2 maintains a logic level of "0".

In short, this photoelectric switch 23
When the light is received, the period verification circuit 11 operates to match the gate timing _T2 with the light emission timing of the light emitting element 4, and the integration circuit 9 outputs the light reception pulse A.
When this occurs seven times in a row, it is determined that the light receiving state has entered and is output.

Next, a description will be given of the stopping of the integral operation when noise on which a high frequency is superimposed is input to the photoelectric switch 23.

The operating state of the integrating circuit 9 before noise input is a stable state of light reception judgment or light blocking judgment where the mismatch number counter 17 is cleared, and a stable state of light reception judgment or light blocking judgment where the mismatch number counter 17 has started counting operation. It is divided into the state of change of judgment. In either of these states, when noise with a superimposed high frequency is input, timing pulse T ₀ is generated, shifted to T ₁ , T ₂ , ...T ₁₅ , and timing pulse T ₀ is generated again. During the period of light shielding until or timing pulse T ₀ occurs and shifts from T ₁ to T ₂ , timing pulse T ₃
During the period of the light receiving state from when the timing pulse T 0 is cleared and the timing pulse T ₀ is generated again, three or more light receiving pulses A will be input, and as a result, the noise pulse detector 10 will immediately start counting up and output. B is generated and the mismatch count counter 17 is cleared through the first OR gate 18, and a change in the light receiving or light blocking judgment output _Q2 stored in the second flip-flop circuit 13 of the integrating circuit 9 is prohibited.
At the same time, the count-up output B is output from the third
The timing pulse is input to the frequency divider circuit 7 through the OR gate 22 and cleared.
T ₀ occurs, which clears the noise pulse detector 10 and immediately puts it in a state where it can re-detect the high frequency superimposed noise. If high-frequency superimposed noise is subsequently input, the noise pulse detector 10 counts the high-frequency pulses in this noise and repeatedly generates count-up output B. 1
7 continues to be cleared and the integral operation is stopped while the judgment state before stopping is memorized. When the high frequency superimposed noise is no longer input, the count-up output B of the noise pulse detector 10 is no longer generated, so the photoelectric switch 23 resumes its normal operation.

The reason why the count number until the noise pulse detector 10 counts up is set to three is as follows.

In addition to being used alone, photoelectric switches
They may be juxtaposed as shown in FIG. In this case, incident light from the light emitting elements of two adjacent photoelectric switches 24 and 25 may enter the own light receiving element 1. In this case, if this is detected as noise and the integral operation is stopped, the function of the photoelectric switch 23 will be stopped even though the light from its own light projecting element is being incident. Then, another adjacent photoelectric switch 24,
In order to prevent the integral operation from being stopped with the projected light from the photoelectric switch 25, the noise pulse detector 10 is prevented from counting up even if up to two light reception pulses from other photoelectric switches are input during one self-test period. It goes without saying that this number can be set as appropriate depending on the usage situation.

The above explanation has been about the photoelectric switch 23 that employs an integrating circuit with a periodic verification function.
The present invention can also be applied to a photoelectric switch having an integrating circuit that does not perform cycle verification.

Effects of the Invention The present invention provides noise pulse detection in an asynchronous photoelectric switch that detects the arrival of high-frequency superimposed noise and stops the operation of the integrating circuit while maintaining the previous light reception or light blocking judgment output for that period. Since the switch is provided, it is possible to prevent the photoelectric switch from malfunctioning due to noise input associated with the interrupting operation of the electromagnetic switch. Particularly, when the present invention is applied to a photoelectric switch having a cycle verification function, the operation of the integrating circuit can be prevented from being stopped due to incident light from an adjacent photoelectric switch, and the range of application can be widened.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an asynchronous photoelectric switch which is an embodiment of the present invention, Fig. 2 is a timing diagram for explaining its operation, and Fig. 3 is an explanation of problems when photoelectric switches are arranged side by side. This is a diagram for DESCRIPTION OF SYMBOLS 1... Light receiving element, 3... Amplitude discriminator, 4... Light emitting element, 5... Light emitting oscillator, 6... Oscillation circuit,
7... Frequency dividing circuit, 8... Gate circuit, 9... Integrating circuit, 10... Noise pulse detector, 11... Period verification circuit, 23... Photoelectric switch, A... Light receiving pulse, B... Noise Pulse detector count-up output, _Q2 ... Judgment output of light reception or light blocking state.

Claims (1)

[Claims] 1. A light-receiving element that receives light emitted at a predetermined period from a light-emitting element and generates a light-receiving pulse, and whether or not the integrated amount reaches a predetermined value by integrating this light-receiving pulse. A photoelectric switch is equipped with an integrating circuit that determines whether the light is in the light-blocking state or in the light-receiving state and outputs the result.The photoelectric switch is equipped with an integrating circuit that determines whether the light is in the light-blocking state or in the light-receiving state and outputs the result. A noise pulse detector is provided that causes the above integration circuit to stop its judgment operation while retaining the judgment result at that point in time when the number of pulses exceeds a predetermined set value than the normal number of pulses that should be received from a light emitting element that is not in use. A photoelectric switch characterized by the following: