JPS61198091A - Photoelectric switch - Google Patents

Abstract

PURPOSE:To scarcely increase average current consumption, and to increase the response speed by raising a pulse modulation frequency only when necessary. CONSTITUTION:A frequency dividing circuit 9 divides an output of an oscillating circuit 8 and generates repeatedly timing clocks T0, T1 and T2, and an integration circuit 11 integrates a photodetecting signal which has passed through a gate circuit 10, and decides a photodetecting state or a light shielding state and outputs it. A controlling circuit 12 controls the circuit 9, when the circuit 11 executes an integral operation, and multiplies a frequency of the timing clock T2 of a projected light only at the time of a variation between the photodetecting state and the light shielding state, so that the remaining time occupying the greater part of time in which a photoelectric switch 33 is being operated becomes low. In this way, the average current consumption is scarcely increased, and only when an operation of the switch is necessary, the projecting and photodetecting operations are executed by a high frequency.

Description

[Detailed Description of the Invention] The present invention is a pulse modulation type photovoltaic device that increases the response speed without increasing the average current consumption by increasing the pulse modulation frequency only when necessary. Regarding switches.

A pulse modulation type photoelectric switch that emits pulsed light from a light emitting element through a detection space to a light receiving element, and detects the presence or absence of an object by receiving or blocking the light, generally opens at the timing of the light emission. A synchronous detection method is adopted in which the output of the light receiving element is taken out by a gate to synchronize the emission and reception of light, and an integrating circuit determines that the light receiving state has entered when the received light pulse hits the gate a set number of times in succession.

Here, in order to increase the response speed of the photoelectric switch, it is possible to reduce the number of settings before the integrator circuit outputs, but the integrator circuit may integrate the noise and mistakenly determine the light receiving state. In order to increase the response speed without causing the adverse effect of reducing the noise margin mentioned above, it is possible to increase the timing clock frequency of the light emission and reception. (The average current consumption of the light emitting element increases, which accounts for the
This is disadvantageous in the case of a photoelectric switch (3) of the type that is connected in series with the power source (2) and used as a control switch for the small electromagnetic switch (1).

In other words, this type of photoelectric switch (3) extracts the operating current from its output contacts (3a) (3b), so when the output contacts (3a> (3b) are cutting off the current, the small electromagnetic switch The photoelectric switch must be operated with a current lower than the holding current in (1).Therefore, it was difficult to adopt the method of increasing the timing frequency of light emission and reception.

In order to increase the response speed without substantially increasing the current consumption of the photoelectric switch, the present invention changes the frequency of the light emitting/receiving timing clock only when the integrating circuit operates in response to changes in light shielding and light receiving states. The average current consumption is not increased.

That is, the present invention includes an oscillation circuit, a frequency division circuit that divides the frequency of the oscillation output to generate a timing clock for transmitting and receiving light, and
A light emitting element that emits pulse light according to the above timing clock, a light receiving element that receives light from the light emitting element, a gate circuit that passes the output of the light receiving element at the generation timing of the above timing clock, and a light emitting element that has passed through the gate circuit. In the photoelectric switch, the photoelectric switch is equipped with an integrating circuit that integrates the output and outputs a light reception determination signal when a predetermined number of outputs are generated consecutively at each generation timing of a timing clock, wherein the integrating circuit starts integrating the output of the light receiving element. The photoelectric switch is characterized in that it is equipped with a control circuit that controls the frequency dividing circuit to increase the frequency of the timing clock for light emission and reception until the post-determination signal is output.

1 relic The present invention will be explained below with reference to the drawings.

In Figure 1, (4) is a light receiving element such as a phototransistor, (5) is a pulse amplifier, (6) is an amplitude discriminator that extracts positive signal components above a certain level, and (7) is an LED.
etc., (8) is an oscillation circuit, (9) is an oscillation circuit (
8) is frequency-divided to create a timing clock T Os T
1, T2, etc. occur repeatedly in sequence, and the frequency division ratio is 1/16 during normal times, and the frequency division ratio is 1/16 when light reception and light blocking change.
(10) is a gate circuit that is opened by the timing clock T2 output from the frequency dividing circuit (9), and (11) is a light reception signal that passes through the gate circuit (10) at the timing of generation of the timing clock T2. (hereinafter referred to as light reception pulse A), and determines that the light reception state has entered when a predetermined number of light reception pulses A are input in succession;
an integrating circuit (12
) controls the frequency divider circuit (9) during the integration operation,
This is a control circuit that increases the frequency of the timing clock T2 for transmitting and receiving light.

The components of the above circuit will be explained in more detail.

The oscillation direction path (8) includes a capacitor C and a resistor R.

, R2, a Schmitt trigger circuit (14), an inverter (15), and an amplifier (16) consisting of a transistor Tr.

The frequency dividing circuit (9) consists of four T-type frisopfromp circuits (
17) (1B) (19) (20) and three multi-input type AND gates (21) (22) (2
3).

The integrating circuit (11) includes a first flip-flop circuit (24) which is set by the light reception pulse A and reset by the timing clock Tl, and a second flip-flop circuit (24) which stores and outputs the current judgment state of light reception or light blocking. Flip-flop circuit (25
), and first and second flip-flop circuits (24)
A coincidence detection circuit (26) receives the outputs Q, , Q2 of (25) and generates a coincidence output of logic level "1" when they match, and inverts the outputs of the -number output circuit (26). an inverter (27) that generates a mismatch output;
and a second AND gate (28a) (28b), which passes the mismatch output B and the match output C at the generation timing of the timing clock To.
8) is reset by the coincidence output C that has passed through the counter gate (2B), counts the mismatch output B, and generates the count-up output Q7 when the mismatch output B is input seven times in a row. Comprised of a counter (29) and third and fourth AND gates (30a) (30b'), when the count-up output Q7 of the mismatch counter (29) is generated, it is opened and the first flip-flop circuit (24) is opened. The memory contents are transferred to the second flip-flop circuit (
25) and a data transfer gate (30).

The control circuit (12) includes an inverter (31) that inverts the output Qo (the logic level is "1" when the count number is 0) of the mismatch counter (29), and an inverter (3).
1), when the output of the T-type flip-flop circuit (20) reaches the logic level of "1", the fifth circuit supplies the output Qd of the "1" logic level of the T-type flip-flop circuit (20) to the reset terminal of each T-type flip-flop circuit. It is composed of an AND gate (32).

The operation of the photoelectric switch (33) will now be described with reference to the timing chart shown in FIG.

The oscillation circuit (8) generates an oscillation output of a constant frequency and an output E which is an inversion of the oscillation output. The output of the above oscillation circuit (8) is connected to four T-type flip circuits (17) (1B)
(19) (20) to 11 [connected frequency divider circuit (9
), the frequency is divided by Each T-type flip-flop circuit inverts each time an oscillation pulse is input to its input terminal T.

Therefore, those output terminals Qa, Qb, Qc, and Qd are set to "O" when the output F of the inverter (31) of the control circuit (12)
When you are at the level of the ruler, (0,010,0) (1,0
, 0, O) - (1, 1, 1, 1), and when the output F of the inverter (31) of the control circuit (12) is at the logic level of "1" (0, 0 ,0,0)(1
, 0, 0, 0), -- (1, 1, 1, 0) are repeated in sequence. Then, the multi-input type AND gates (21), (22), and (23) in the frequency dividing circuit (9) each change the output state to (0 , O, 010), timing clock To is generated, timing clock T1 is generated when (1, 0, 0, O), and timing clock T2 is generated when (0, 1, 0, O). In short, the frequency divider circuit (9) is a ring counter that divides the oscillation output of the oscillation circuit (8) into 1/16 or 1/8 and outputs it.
Timing clocks 'p O , T I , and T2 are sequentially generated for each of the first three counts out of eight counts. This timing clock TO1T
I, T2, the photoelectric switch (33) operates as follows.

The light emitting element (7) emits pulse light in synchronization with the timing clock T2, and the pulse amplifier (5) and amplitude discriminator (6)
Only the output of the light-receiving element (4) processed by the above-mentioned timing T2 is taken out by the gate circuit (10), and if the light is received during the above-mentioned timing clock T2, a light-receiving pulse A is generated. . The first flip-flop circuit (24) is set by the light receiving pulse A and reset by the timing clock T1, so when the light receiving element (4) receives light at timing T2, the output Q1 of the first flip-flop circuit (24) is set at timing T2. The logic level is "1" during the period of clocks T2 to T.

Here, it is assumed that the mismatch count counter (29) and the second flip-flop circuit (25) are in an initial state where they are reset. At this time, the output Qo of the mismatch number counter (29) is at the logic level of "1", and the output F of the inverter (31) (7) which is inverted is at the logic level of "0". ) operates at a frequency division ratio of 1/16.

When the light reception pulse A occurs at timing clock T2,
The first flip-flop circuit (24) stores and holds this until the next timing clock T1. On the other hand, the counter game (28) opens at the timing clock To within this memory retention period. At this time, the output Q1 of the first flip-flop circuit (24) is at the logic level of "1", and the second flip-flop circuit (24) Output Q2 of circuit (25) is “0”
Since the logic level is , a mismatch output B is generated, and the mismatch counter (29) counts by one. As a result, the output Qo of the mismatch counter (29) becomes a logic level of "0", which is inverted by the inverter (31).
In response to the output F of the fifth AND gate (32) opens, each T-type flip-flop circuit (17)
(1B) (19) Output Qa, Qb, Qc of (20)
When SQd changes from (1, 1, 1, 0) to (1, 1, 1, 1), it immediately changes to (0, 0, 0, 0). That is, the frequency division ratio of the frequency dividing circuit (9) changes to 1/8. After that, when the light receiving element (4) receives light continuously at each timing clock T2, the light receiving pulse A is generated every cycle, so the mismatch number counter (29) unifies the count number by the above operation. Increase by increments.

When seven consecutive light reception pulses A are generated, the mismatch count counter (29) is started at the timing clock To immediately after this.
generates count-up output Q7, data transfer game)
(30) and open the first flip-flop circuit (24).
) is transferred to the second flip-flop circuit (25). As a result, the output Q2 of the second flip-flop circuit (25) becomes a logic level of "L" indicating the light receiving state, and the -number output circuit (26) is connected to the first and second flip-flop circuits (24) (25). Since the outputs Q1 and Q2 of are at the logic level of “1” indicating that they match,
The mismatch counter (29) is reset and the count-up output Q7 also disappears. Above count up output Q7
The generation of , the inversion of the second flip-flop circuit (25), and the reset of the mismatch counter (29) are all performed immediately after the timing clock To rises.

After the output Q2 of the second flip-flop circuit (25) changes to the logic level of "1" indicating the light receiving state, the mismatch counter (29) is reset and the output QO becomes " Since the logic level is 1'', the frequency division ratio of the frequency divider circuit (9) changes to 1716 again. If the light reception state continues, a coincidence output C is generated at this cycle, and the mismatch count counter (29) continues to be reset.

However, if the light is blocked and the received light pulse A does not occur,
A mismatch number counter (29) detects the mismatch between the logic level "0" of the first flip-flop circuit (24) and the logic level "1" of the second flip-flop circuit (25). ) starts counting at the opening timing TO.During this counting period, the output Qo of the mismatch counter (29) becomes a logic level of 0'', so by the above operation, the frequency division ratio of the frequency divider circuit (9) becomes l. /8. When a received light pulse A is generated due to noise caused by disturbance light or the like during the counting period, the frequency division ratio of the frequency dividing circuit (9) becomes 1/1B only immediately after that, and the mismatch count counter (29) is reset by the above operation. Ru. If the received light pulse A does not occur continuously during seven consecutive timing clocks T2, the above-mentioned mismatch count counter (29)
generates a count-up output Q7, the second flip-flop circuit (25) is inverted again and its output Q2 changes to a logic level of 10'' indicating a light shielding state.

In the detection operation of the photoelectric switch (33) as described above, the frequency of the timing clock T2 for transmitting and receiving light is doubled only when changing between the light receiving state and the light shielding state, and the frequency of the timing clock T2 for transmitting and receiving light is doubled only when changing between the light receiving state and the light shielding state, and the frequency of the timing clock T2 for transmitting and receiving light is doubled only when changing between the light receiving state and the light blocking state. Time is driven at a low frequency.

It should be noted that each component in the present invention is of course not limited to the circuit of the above embodiment. For example, the frequency division ratio of the frequency dividing circuit can be set arbitrarily, and the integrating circuit can also be configured such that the received light pulses are continuously Any device that determines whether light is received or blocked depending on whether or not it is input may be used, and a CR integrating circuit or the like may also be used.

The present invention provides a photoelectric switch that emits and receives light at a low frequency during normal times, and emits and receives light at a high frequency only when there is a change in light reception and light blocking, so that the average current consumption hardly increases. , the response speed can be increased. Therefore, the response speed of photoelectric switches, which are used to control the control current of a small electromagnetic switch by its output setting and extract its own operating current from its output contacts, can be increased, and its utility value can be improved. Of course, the load controlled by the photoelectric switch of the present invention is not limited to the above-mentioned small electromagnetic switch, and even though the response speed is increased, the current leakage at the time of interruption can be reduced, so it can be used as a control switch. Performance can be improved.

In addition, since the photoelectric switch of the present invention emits light at a high frequency only when there is a change in light blocking and light reception, the value of the pulse current flowing through the light emitting element is increased to increase the luminous intensity and improve the discrimination from ambient light. , the light projection distance can be extended. That is, L.E.
The maximum pulse current that can flow when a light emitting element such as D emits pulse light is determined by its duty ratio (energizing pulse width/energizing pause time), but it is possible to drive it at a high frequency (large duty ratio) for a short time. If the drive is normally performed at a low frequency (with a small duty ratio), the maximum pulse current need only be adjusted to the low frequency, and can be set to a large value.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a timing diagram thereof. FIG. 3 is a circuit diagram showing an example of use suitable for the photoelectric switch of the present invention. (4') - Light receiving element, (7) - Emitter element, (8) -
・Oscillation circuit, (9) --1~-frequency divider circuit, (10)
-Gate circuit, (11) -Integrator circuit, (12)・-Control circuit, (T2) -Timing clock, (Q2)
・−・Light reception judgment signal.

Claims (1)

[Claims] (1) An oscillation circuit, a frequency dividing circuit that divides the frequency of this oscillation output to generate a timing clock for light emission and reception, a light emitter that emits pulsed light according to the timing clock, and a light receiver that receives light from the light emitter. , a gate circuit that passes the output of the light-receiving element at the generation timing of the timing clock, and a light reception judgment when the output of the light-receiving element that has passed through the gate circuit is integrated and a predetermined number of times the output of the light-receiving element is continuously generated at each timing clock generation timing. In a photoelectric switch equipped with an integrating circuit that outputs a signal, after the integrating circuit starts integrating the output of the light receiving element and until outputting the determination signal, the frequency dividing circuit is controlled to set a timing clock for light emission and reception. A photoelectric switch characterized by being equipped with a control circuit that increases the frequency of the photoelectric switch.