JPH0352013A - Clock control system - Google Patents

Abstract

PURPOSE:To improve adjustment accuracy by adjusting the phase of a clock distributing circuit after the temperature of a cooled part in a processor or the temperature of cooling water becomes stable after the power source is turned on. CONSTITUTION:The temperature value of the cooling water when the junction temperature of semiconductors of clock distributing circuits 9 - 11 is set previously in a cooling water temperature detecting means 12 in a cooling controller 2 and after a processor 1 is powered on, the temperature of the cooling water is monitored to output a cooling water temperature detection signal to a service processor 4 when the preset value is reached. The service processor 4 outputs a phase adjustment command to the clock distributing circuits 9 - 11 after detecting the cooling water temperature detection signal. Consequently, while the junction temperature of the semiconductors of the clock distributing circuits 9 - 11 becomes stable, the phase of a clock signal is adjusted to improve the adjustment accuracy of the phase.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a clock control method for an electronic computer, and in particular,
This paper relates to a clock control method suitable for highly accurate phase alignment of clock signals of water-cooled processing equipment. [Prior art] In the conventional clock control system, a clock distribution circuit is equipped with a delay circuit to reduce variations in signal propagation time.
There are systems that manually correct the phase using a delay circuit before incorporating this clock distribution circuit into the device, and systems that allow the phase adjustment of the clock signal to be performed automatically after the clock signal is built into the device. As this type of conventional technology, for example, Japanese Patent Application Laid-Open No. 63-46
Examples include those described in Japanese Patent No. 529.

[Problems to be Solved by the Invention] The above-mentioned conventional technology does not take into account the junction temperature conditions of the semiconductor that constitutes the clock distribution circuit at the time of adjusting the phase of the clock signal. If the phase adjustment is performed automatically, the phase adjustment will be made while the semiconductor junction temperature is rising, and even after the adjustment is completed, the clock will change as the semiconductor junction temperature approaches a stable state. The signal propagation time in the distribution circuit changes, causing a phase shift in the clock signal. In particular, in water-cooled processing equipment, it takes time to raise the junction temperature of the semiconductor, so the phase shift becomes large.

Therefore, when the processing device enters the operating state, the clock signals remain out of phase, resulting in a problem that the operating margin of the processing device becomes small. Furthermore, when designing a processing device, it is necessary to take into consideration the phase shift of the clock signal as described above, which has the drawback of causing a decrease in performance.

An object of the present invention is to minimize the phase shift of a clock signal when a processing device is in operation, to ensure an operating margin of the processing device, and to further improve the accuracy of the phase of the clock signal! I! The objective is to provide a clock control method that enables I. [Means for Solving the Problems] In order to achieve the above object, the clock control method according to the present invention automatically adjusts the phase of a water-cooled logic unit and a clock signal! 1. A clock control method for a processing device, comprising a clock distribution circuit having a function of adjusting 1! After turning on the source. The phase adjustment of the clock distribution circuit is performed after waiting for the temperature of the cooled part in the processing device or the temperature of the cooling water to reach a stable state. Specifically, power is turned on, that is, power is supplied to the processing device from a power supply device, and cooling water is supplied from a cooling control device. The service processor also instructs the power supply device to supply power to the processing device, and instructs the cooling control device to supply cooling water to the processing device. The cooling control device is equipped with a cooling water temperature detection means that monitors the temperature of the cooling water and notifies the service processor when a stable state has been reached. After turning on the power to the power supply device, the service processor outputs an automatic phase adjustment command to the clock distribution circuit according to the detection output from the temperature detection means. [Function] In the clock control method of the present invention, the phase of the clock distribution circuit is not adjusted immediately after the processing device is powered on, but after confirming that the temperature of the cooling water has reached a stable state, Execute phase adjustment of the clock distribution circuit. Specifically, the cooling water temperature value when the junction temperature of the semiconductor of the clock distribution circuit reaches a stable state is set in advance in the cooling water temperature detection means in the cooling control device, and after the processing device is powered on, the cooling water temperature value is set in advance. Monitors the cooling water temperature and outputs a cooling water temperature detection signal to the service processor when it reaches a preset value. After detecting this cooling water temperature detection signal, the service processor outputs a phase adjustment command to the clock distribution circuit. As a result, the phase of the clock signal can be adjusted while the semiconductor junction temperature of the clock distribution circuit is stable, and the accuracy of phase adjustment can be improved. Preferably, the period after the power is turned on until the temperature of the cooling water reaches a stable state. Reset the processing device. [Example] An example of the present invention will be described below with reference to FIGS. 1 and 2. In FIG. 1, the service processor 4 is connected to a cooling control unit (CU) 2 and a power supply unit (CU) 2 when the system is powered on.
A power-on command is output to the PDU (PDU) 3 via power control lines 21 and 22. Cooling control device 2 and power supply device 3
When the power is turned on, each logical unit 5 to
7 are supplied with cooling water 30 to 32 and electric power 27 to 29.

Moreover, when power is supplied to the processing device 1, the master clock generation time Jl! 8 (MCLK) to the master clock signal 25 from the clock distribution circuit 9 in each logic unit 5 to 7.
~11 (CKD). Clock distribution circuit 9~
11 distributes a branch clock to each logic unit 5 to 7 based on the master clock signal 26, and
Upon receiving a phase adjustment command 25 from the service processor 4, the phase of the output clock is automatically adjusted. The service processor 4 also resets each of the logical units 5 to 7 using the reset line 24. A cooling water temperature detection means 12 in the cooling control device [2] detects the cooling water temperature to the service processor 4 when the temperature of the cooling water supplied to each logical unit 5 to 7 reaches a preset value. A detection signal 23 is output. Note that the value set in advance in the cooling water temperature detection means 12 is . This is the temperature value of the cooling water 30 to 32 when the junction temperature of the semiconductor of the clock distribution circuit reaches a stable state after the power is turned on. Next, the clock control operation at the time of powering on the system shown in FIG. 1 will be explained based on the flowchart shown in FIG.

First, the system is powered on by issuing a power-on command from the service processor 4 to the cooling control device 2 and the power supply device 3. As a result, the cooling control device 2 and the power supply device 3 are powered on, and each of the processing devices L is powered on. Cooling water 30-32 and electric power 27-29 are supplied to logical units 5-7 (lot-102). On the other hand, when the service processor 4 turns on the power to the processing device, each logical unit 5 to 7 is set to a reset state by reset@24 ((103). Next, the cooling water temperature detection means 12: After the power is turned on, when the temperature of the cooling waters 30 to 32 reaches a preset value, that is, the value when the semiconductor junction temperature of the clock distribution circuits 9 to 11 is in a stable state, a message is sent to the service processor 4. The service processor 4 outputs a cooling water temperature detection signal 23.After the power is turned on, the service processor 4 monitors and waits for a certain period of time until it receives this cooling water temperature detection signal 23 (104-
105) When the cooling water temperature detection signal 23 is detected, a phase adjustment command 25 is issued to the clock distribution circuits 9 to 11 (107) - If the detection signal 23 is not output for a certain period of time, error processing is performed (106).

Furthermore, upon receiving the phase adjustment command 25, the clock distribution circuits 9 to 11 automatically adjust the phase of the output clock signal! l! ! do.

On the other hand, after issuing the phase adjustment command 23, the service processor 4 waits for a sufficient time for the clock distribution circuits 9 to 11 to automatically adjust the phase of the output clock, and then releases the reset state of each logic unit 5 to 7. (108-10
9). In FIG. 1, the phase adjustment command 25 for the clock distribution circuits 9 to 11 is issued from the service processor 4, but this is just one example, and the phase adjustment command 25 for the clock distribution circuits 9 to 11 is issued directly from the processing device from the cooling water temperature detection means 12. Needless to say, it can also be handled by importing it into l. Furthermore, in order to know that the junction temperature of the semiconductors of the clock distribution circuits 9 to 11 has become stable, the temperature of the cooling water 30 to 32 is detected. It is also possible to extract the semiconductor junction temperature and generate a phase adjustment command signal. According to this embodiment, the phase adjustment of the output clock signal can be performed while the junction temperature of the semiconductor forming the clock distribution circuit is stable, which has the effect of improving the accuracy of the phase adjustment. [Effects of the Invention] According to the present invention, the phase adjustment of the output clock signal can be performed while the junction temperature of the semiconductor constituting the clock distribution circuit is stable, so that the adjustment accuracy is improved.
This has the effect of minimizing the phase shift of the clock signal while the processing device is operating, and further expanding the operating margin of the processing device. Further, in designing the processing device, it is not necessary to take into consideration the phase shift of the clock signal as described above, which has the effect of preventing performance degradation.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the present invention, and FIG. 2 is a flow chart showing the clock control operation when the system power of FIG. 1 is turned on. 1... Processing device, 2... Cooling control unit (CU),
3...Power supply unit (PDU), 5-7...Logic unit, 8...Master clock generation circuit, 9-1l...
・Clock distribution circuit, 12...Cooling water temperature detection means,
21-22...Power control line, 23...Cooling water temperature detection signal, 23.24...Reset line, 25...Phase adjustment command, 26...Master clock signal, 27-29
...Electric power, 30-32...Cooling water.

Claims (1)

[Scope of Claims] 1. A clock control method for a processing device including a water-cooled logic unit and a clock distribution circuit having a function of automatically adjusting the phase of a clock signal, comprising: A clock control method characterized in that, after power is turned on, the phase adjustment of the clock distribution circuit is performed after waiting for the temperature of a cooled part in the processing device or the temperature of cooling water to reach a stable state.