JPS599737A - Controlling circuit for use of bus - Google Patents

Abstract

PURPOSE:To improve the utilizing efficiency of a communication line, by providing a circuit for setting a bus utilizing right in accordance with a priority order decided in advance. CONSTITUTION:A controlling circuit 9 confirms whether a communication line lis used or not, by detecting circuits 2, 4 and 5. In case when the communication line is not used, the controlling circuit 9 sends out a bus using request signal to the communication line l from a sending-out circuit 1. In this case, a built-in timing circuit is started. The time required for making this timing circuit time-up is set to a different value at each device, and a device whose set time is short is made to have a high priority order. In case when a bus utilizing right obtaining signal is not detected within a set time of this timing circuit, its own bus utilizing obtaining signal is sent out from a sending-out circuit 3. In this way, a device of the highest priority can use the bus in accordance with the priority order, and the bus utilizing efficiency can be raised.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bus usage management circuit that can efficiently manage paths when a plurality of devices are connected to a communication line.

In a communication system in which each device is connected to a communication line in a path structure as shown in FIG. 1, each device monopolizes the bus and executes data communication after acquiring the right to use the path. In such cases, the management method for path usage rights includes data communication
There are two types of methods: a method in which the right to use the path is given and received (baton pass method), and a method in which the right to use the path is acquired by exchanging special signals prior to data communication. The latter method requires one or more management signal wires in addition to the normal signal wires, and when a path use request occurs, each device immediately responds if the path is not in use. Communication starts, but if multiple pieces of communication data collide on the path, it will be detected and the current communication will be terminated.After an appropriate amount of time has elapsed, communication will be started again, and if no collision is detected, communication will continue. There is a method (C8MA/CD method) in which communication is continued based on success.

In particular, in a communication system in which data is transferred using a single serial communication line, a control line for path management is required in addition to a normal signal line, which is an extremely large disadvantage. Also, cSM
The A/CD method requires a detection circuit to detect collisions, and the circuit becomes complicated, including timing adjustment, output level adjustment, and the like.

The present invention has been developed in consideration of these points. When a path use request is generated by multiple devices at the same time, only the device with the highest priority among them is processed according to a predetermined priority order. This is a path usage management circuit that has a simple configuration and is designed to improve communication line usage efficiency by making it possible to acquire the right to use the path at that point in time.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is an electrical configuration diagram showing an embodiment of the present invention. In the figure, l denotes a communication line, and 1 denotes a path use request signal sending circuit (hereinafter referred to as a first circuit) that sends a path use request signal to the communication line l.
2 is a path use request signal detection circuit (referred to as a sending circuit of
3 is a path acquisition signal transmission circuit (hereinafter referred to as a second transmission circuit) that sends a path acquisition signal to the signal line t, and 3 is on the communication line t. A path usage right acquisition signal detection circuit (hereinafter referred to as a second detection circuit) detects a path usage right acquisition signal, and 5 is a data communication signal detection circuit that detects that the signal on the communication line l is data Itami. (hereinafter referred to as the third detection circuit).

6 is a data communication transmitting circuit (hereinafter referred to as the third transmitting circuit) that sends out a data signal to signal line tK; 7 is a data receiving circuit that receives a data signal from signal line l; and 8 is a receiving circuit that receives the output of the data receiving circuit. The arithmetic processing circuit 9 is a control circuit that is connected to each circuit and performs various controls. Control circuit 8
, 9, for example, a microcomputer is used. Further, the control circuit 9 includes 241 circuits that can set the time according to a predetermined priority order. The circuits described above are included in each device shown in Figure 1 to ensure efficient operation of communication lines. The operation of the device configured in this way is as follows. It is.

Upon receiving the communication request signal, the control circuit 9 checks whether the communication line 1 is being used. The first to fifth detection circuits 2.4 check whether the communication line is being used or not.
．． 5 does. As these detection circuits, for example, mono-multiple circuits can be used. The pulse width of the pulse generated by each monomulti is made different from the monomulti, and the state of the communication line l is checked after a certain pulse width time has elapsed.
Determine the type of signal on communication line l. for example,
A signal as shown at Pl in FIG. 3 is used as the path use request signal, and a signal as shown at P2 in FIG. 3 is used as the path use right acquisition signal.

That is, Pl is the period T for generating the tone signal for the time width D.
The intermittent wave signal P2 is a signal in which tone waves continue over a period T. When each signal is defined in this way, each detection circuit is triggered at the first rising edge of the tone wave and generates a pulse. In the case of the first detection circuit 2, this pulse width is set to K, which is slightly larger than T. If a retriggerable monomulti is used, if there is a path request signal, the monomulti will be retriggered with the next tone wave, so the output of the detection circuit 2 will maintain the eleventh shape. From this,
It is possible to confirm that there is a path request signal. On the other hand, in the case of the second detection circuit 4, the monomulti pulse width is set to fall in a range greater than 1 and smaller than T. If there is a path acquisition signal, it is constantly re-triggered with a tone wave, so the output of the detection circuit 4 maintains a 111-like expansion, making it possible to confirm that there is a path acquisition signal. Conversely, the outputs of these detection circuits 2 and 4 are 101
In this case, there is no signal.

After confirming that the communication line l is not in use by the above-mentioned operation, the control circuit 9 connects the first sending circuit 1 to the PIK shown in FIG.
A path use request signal as shown is sent to the communication line l. When communication nt is in use, it waits until it becomes free. The control circuit 9 starts the built-in timer circuit at the same time as sending out the path use request signal. Until this timer circuit times up, it waits until a bus usage right acquisition signal from another device becomes available.

Here, by setting the time until the timer circuit times up to a different value for each device, the device with the shortest set time can be given the highest priority. If the path usage right acquisition signal is not detected within the set time of this timer circuit, the control circuit 9 sends out its own path usage right acquisition signal from the second transmission circuit 3. Instead, it waits for the time when other devices detect the signal to acquire the right to use the bus, and then executes data communication. Data communication is performed by transmitting data from the third transmitting circuit 6 to the communication line t.

The above operations are shown in a flowchart as shown in FIG.

As described above, the time width of the tie 1 circuit of each device is set to be short for each priority. The difference between these set values needs to be longer than the time required for all devices to detect the bus right acquisition signal after it is sent.

By setting the time width in this way, even if multiple devices send out bus use request signals at the same time after determining that signal line l is not in use, the device with a higher priority will send out the bus request signal first. Since a device with a lower priority detects the right-to-use signal and stops using the bus, only one device can obtain the right to use the bus. In this way, the signal line l can be used efficiently. Additionally, the circuit itself can be of a simple configuration, and no complicated circuit adjustment is required. Although the above description does not mention the number of signal lines l, the present invention is particularly suitable for use with one serial transmission line.
suitable.

As explained above in detail, according to the present invention, when bus use requests are generated by multiple devices at the same time, only the device with the highest priority at that time has the right to use the bus. It is possible to realize a bus usage management circuit with a simple configuration, which improves the efficiency of using communication lines by making it possible to acquire the bus.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a bus connection configuration, FIG. 2 is an electrical configuration diagram showing an embodiment of the present invention, FIG. 3 is a timing chart, and FIG. 4 is a flow chart. DESCRIPTION OF SYMBOLS 1... Path use request signal sending circuit, 2... Bus use request signal detection circuit, 3... Path use right acquisition signal sending circuit, 4... Bus use right acquisition signal detection circuit, 5... data communication signal detection circuit, 6... data communication transmission circuit,
7... Data receiving circuit, 8... Arithmetic processing circuit, 9.
...Control circuit. Kaya Figure 1 Figure 2 P. Third mouth

Claims (1)

[Claims] A circuit for detecting that another device is communicating, a circuit for outputting a path use request signal and a path use right acquisition signal, and a circuit for detecting a bus use request signal and a path use right acquisition signal. A bus usage management circuit consisting of a timer circuit that can set the time according to priority order, and a control circuit that controls each of these circuits.