JPH0351097B2 - - Google Patents
Info
- Publication number
- JPH0351097B2 JPH0351097B2 JP58141879A JP14187983A JPH0351097B2 JP H0351097 B2 JPH0351097 B2 JP H0351097B2 JP 58141879 A JP58141879 A JP 58141879A JP 14187983 A JP14187983 A JP 14187983A JP H0351097 B2 JPH0351097 B2 JP H0351097B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- connection
- chips
- bonding
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 11
- 238000010586 diagram Methods 0.000 description 13
- 238000004806 packaging method and process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
【発明の詳細な説明】
（技術分野）
本発明は、同一機能素子を多数隣接配置して実
装する半導体チツプの基板への実装方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for mounting a semiconductor chip onto a substrate, in which a large number of identical functional elements are arranged and mounted adjacently.
（従来技術）
従来、同一機能素子、例えばICチツプ等の半
導体チツプ（以下、単にチツプと称す）を、ボン
デイング技術を用いて基板上に多数並べて実装す
る構造、例えば、半導体チツプのサーマルヘツド
への実装では、前記チツプの接続端子相互の接続
を行う接続パターンは２層配線にて形成してい
た。(Prior art) Conventionally, a structure in which a large number of identical functional elements, such as semiconductor chips such as IC chips (hereinafter simply referred to as chips), are mounted side by side on a substrate using bonding technology, for example, mounting on a thermal head of a semiconductor chip, has been proposed. In mounting, the connection patterns for connecting the connection terminals of the chips were formed using two-layer wiring.
第１図は、前述したチツプでの２層配線を説明
する図で、図中、Ａ，Ｂ，Ｃは同一の機能を備え
たチツプで、接続端子１，２，……ｍ，が形成さ
れており、各々の同一機能の端子は図示するよう
に接続線，，…Ｍで接続されている。 Figure 1 is a diagram explaining the two-layer wiring in the chip mentioned above. In the figure, A, B, and C are chips with the same function, and connecting terminals 1, 2, ... m, are formed. The terminals having the same function are connected by connection lines, . . . , M as shown in the figure.
ここで、接続線，，…，Ｍに着目すると、
各チツプＡ，Ｂ，Ｃの接続端子１，２，…，ｍは
同一パターンの配列である為、対応する各チツプ
の同一機能の接続端子との接続の際にその接続線
に交叉するパターンが形成されるのが理解される
のである。したがつて、従来は、複数のチツプの
基板への実装の際には、前記交叉部分で他種の信
号線と接触するのを防ぐ為の工夫例えば、該当箇
所を２層にする等の工夫がなされていたのであ
る。 Here, if we focus on the connection lines,...,M, we get
Since the connection terminals 1, 2, ..., m of each chip A, B, C are arranged in the same pattern, the pattern that crosses the connection line when connecting with the connection terminal of the corresponding chip with the same function is It is understood that it is formed. Therefore, conventionally, when mounting multiple chips on a board, measures have been taken to prevent the crossing portions from coming into contact with other types of signal lines, such as making the relevant portions two-layered. was being done.
第２図〜第４図は、以上の問題点を考慮し、工
夫した従来の実装方法の一例を説明する図で、第
２図は基板、例えば図示しないサマールヘツド上
にボンデイング技術により搭載するチツプでの端
子配置の一例を示す図、第３図は第２図で示した
チツプと接続パターンの形成されたフイルムとを
ボンデイングによつて接続した図、第４図は第３
図の如く接続したチツプとフイルムとを図示しな
い基板、例えばサーマルヘツド上に実装した例を
示す図である。 Figures 2 to 4 are diagrams illustrating an example of a conventional mounting method devised in consideration of the above problems. Figure 2 shows a chip mounted on a board, for example a Samal head (not shown), using bonding technology. FIG. 3 is a diagram showing an example of the terminal arrangement of the chip shown in FIG. 2 and a film on which a connection pattern is formed by bonding, and FIG.
FIG. 3 is a diagram showing an example in which the chip and film connected as shown in the figure are mounted on a substrate (not shown), for example, a thermal head.
以上の図において、１１はチツプ、１２は接続
パターン１２ａを形成したフイルムキヤリアを示
し、１，２，…，ｍと１′，２′，…，m′は各々
チツプ１１の端子形成部分に配置し、形成された
接続の為の端子であり、前者は信号パツド、後者
はダミーパツドである。この信号パツド１，２，
…ｍとダミーパツド１′，２′，…，m′は、図示
する如く同一チツプ上で左右対称に配置、形成さ
れる。又、図中の太い破線は図示しない基板に形
成された接続パターンであり、実線は前記素子等
に形成された接続パターンおよびリードである。 In the above figures, 11 is a chip, 12 is a film carrier on which a connection pattern 12a is formed, and 1, 2, . . . , m and 1', 2', . These are terminals for connections made, the former being a signal pad and the latter being a dummy pad. This signal pad 1, 2,
. . m and dummy pads 1', 2', . . . , m' are arranged and formed symmetrically on the same chip as shown. Further, the thick broken lines in the figure are connection patterns formed on a substrate (not shown), and the solid lines are connection patterns and leads formed on the elements and the like.
そして、第２図に示す如き接続端子を配置形成
した端子形成部分を有するチツプを基板上に多数
並べ同一機能の端子相互を接続して行うチツプの
実装は、先ず第２図に示すチツプ１１と第３図に
示す如くあらかじめ接続パターン１２ａの形成さ
れたフイルムキヤリア１２とを接続する。この時
の接続は、フイルムキヤリア１２に形成された接
続パターン１２ａによつてチツプ１１上に信号パ
ツドとダミーパツド、例えば１と１′，２と２′，
…，ｍとm′とを接続する。この時の技術は、こ
の種の端子接続で広く用いられているボンデイン
グ技術のうちのTAB法のインナーボンデイング
が用いられる。次いで、以上第３図の如く接続し
たチツプ１１とフイルムキヤリア１２とを図示し
ない基板上の接続パターン、すなわち、第４図に
太い破線で示す接続パターン上にボンデイング技
術例えばTAB法のアウターボンデイングを用い
て接続することによりチツプ１１の基板への実装
を完了する。これにより、任意の場所で各々、信
号線を接続することにより第１図で説明した基板
上での２層配線と同等の構成が得られたことにな
るのである。 Chip mounting, which is carried out by arranging a large number of chips having terminal forming portions with connecting terminals arranged and formed on a board as shown in FIG. As shown in FIG. 3, a film carrier 12 on which a connection pattern 12a has been formed in advance is connected. At this time, connections are made between signal pads and dummy pads, such as 1 and 1', 2 and 2', on the chip 11 using a connection pattern 12a formed on the film carrier 12.
…, connect m and m′. The technique used at this time is inner bonding of the TAB method, which is one of the bonding techniques widely used for this type of terminal connection. Next, the chip 11 and film carrier 12 connected as shown in FIG. 3 are bonded using a bonding technique such as TAB outer bonding on a connection pattern on a substrate (not shown), that is, a connection pattern indicated by thick broken lines in FIG. By making the connections, the mounting of the chip 11 on the board is completed. As a result, a configuration equivalent to the two-layer wiring on the board described in FIG. 1 can be obtained by connecting the signal lines at arbitrary locations.
しかしながら、これまでの説明から判明するよ
うに、第２〜４図を用いて説明した従来の方法で
は、実装すべきチツプについてみると、接続パタ
ーン数の２倍のパツドを必要とし、したがつて、
チツプ面積を同じようにするとパツドピツチ、換
言するとボンデイングピツチが極めて狭くなつて
作業性、ボンデイング時の歩留り等の低下を招
き、又、前記欠点を防ぐ為にパツドピツチを広く
するとチツプ面積が大きくなる等の問題が生じて
いた。更に、信号パツドとダミーパツドとの接続
にフイルムキヤリアを用いる構成であるので、接
続の為のボンデイング作業は多く、又、ワイヤボ
ンデイング等の他の接続手段の採用、換言する
と、他の実装法への応用が困難である等の問題が
あつた。 However, as is clear from the above explanation, the conventional method explained using Figures 2 to 4 requires twice as many pads as the number of connection patterns when it comes to chips to be mounted. ,
If the chip area is kept the same, the pad pitch, or in other words, the bonding pitch, will become extremely narrow, resulting in a decrease in work efficiency and yield during bonding.In addition, if the pad pitch is widened to prevent the above-mentioned drawbacks, the chip area will become larger, etc. A problem had arisen. Furthermore, since the configuration uses a film carrier to connect the signal pad and dummy pad, there is a lot of bonding work required for connection, and it is also necessary to use other connection methods such as wire bonding, in other words, to use other mounting methods. There were problems such as difficulty in application.
（発明の目的）
本発明は、以上述べたいくつかの問題点を考慮
してなされたものであつて、従来必要としていた
フイルムキヤリア、およびダミーパツドを用いず
に、各チツプの同一機能の端子相互の接続を実現
する実装方法を提供することを目的とするもの
で、ボンデイング作業の減少を図り、チツプ面積
を増すことなく充分なパツドピツチを確保、換言
すると、充分なボンデイングピツチを確保した作
業性の優れた実装方法を提供するものである。(Object of the Invention) The present invention has been made in consideration of the above-mentioned problems, and it is possible to interconnect terminals of the same function on each chip without using a film carrier or a dummy pad, which were conventionally required. The purpose of this is to provide a mounting method that realizes a bonding process that reduces bonding work and ensures sufficient pad pitch without increasing the chip area. It provides an excellent implementation method.
（発明の構成）
すなわち、本発明は上記目的を達成する為に、
接続端子の配置の異つたチツプを用い、しかもチ
ツプに配置形成する接続端子は、チツプを基板に
実装した場合に、隣り合つたチツプのそれと左右
対称となるように配置形成し、基板上の接続パラ
ーンにより隣り合うチツプの同一機能の接続端子
相互を接続する構成としたものである。以下、図
面を用いて本発明を説明する。(Structure of the invention) That is, in order to achieve the above object, the present invention has the following features:
Chips with different connection terminal arrangements are used, and the connection terminals arranged and formed on the chip are arranged and formed so that when the chip is mounted on a board, they are symmetrical with those of adjacent chips, and the connections on the board are The configuration is such that connection terminals of adjacent chips having the same function are connected to each other by a paran. The present invention will be explained below using the drawings.
（発明の実施例）
第５図は、本発明に係る第１の実施例を示す図
で、図中、D1，D2，…，E1，E2，…は同一の機
能を備えたチツプであつて、その端子形成部分に
は接続端子である信号パツド１，２，…，ｍ−
１，ｍが配置形成されている。この時の前記信号
パツドは、チツプＤ−，Ｅ−で異つており、各々
のチツプを交互に配列した場合に、隣り合うチツ
プＤ−またはＥ−のそれと互いに左右対称になる
ように配置形成されている。又、図中での太い破
線は、図示しない基板上に形成した接続パター
ン、ここでは信号線のパターンであり、図示する
如く形成されている。すなわち、隣接チツプの同
一機能の信号パツト相互を接続する信号線のパタ
ーンは、対応の信号パツドの接続の際に他の信号
線のパターンと交叉することなく形成されている
のである。例えば、第５図において、チツプD1，
E1，D2に配置形成された各信号パツド相互の接
続についてみると、信号パツド１の接続では、チ
ツプD1とE1との間は１番外側に形成された最長
パターンを、チツプE1とD2との間は逆に１番内
側に形成された最短パターンを介して各々行なわ
れており、又、信号パツドｍの接続では、チツプ
D1とE1との間は１番内側に形成された最短パタ
ーンを、チツプE1とD2との間は逆に１番外側に
形成された最長パターンを介して各々行なわれて
いるのである。したがつて、交互に配したチツプ
Ｄ−とＥ−の同一機能の信号パツド相互の接続に
際し、その信号線のパターンに他の信号線のパタ
ーンが交叉する部分が生じることなく、第１図で
示した端子接続部分の２層配線と同等の配線が行
えたことになるのである。(Embodiment of the invention) FIG. 5 is a diagram showing a first embodiment of the present invention, in which D 1 , D 2 , ..., E 1 , E 2 , ... have the same function. It is a chip, and its terminal forming portion has signal pads 1, 2,..., m- which are connection terminals.
1, m are arranged and formed. At this time, the signal pads are different for chips D- and E-, and when each chip is arranged alternately, they are arranged and formed so as to be symmetrical with those of the adjacent chip D- or E-. ing. Further, the thick broken lines in the figure are connection patterns formed on a substrate (not shown), in this case signal line patterns, which are formed as shown in the figure. That is, the pattern of signal lines connecting signal pads of the same function on adjacent chips is formed without intersecting other signal line patterns when connecting the corresponding signal pads. For example, in FIG. 5, chips D 1 ,
Looking at the connection between the signal pads arranged and formed on E 1 and D 2 , in the connection of signal pad 1, between chips D 1 and E 1 , the longest pattern formed on the outermost side is connected to chip E. 1 and D2 are connected via the shortest pattern formed on the innermost side, and the signal pad m is connected via the chip.
Between D 1 and E 1 , the shortest pattern formed on the innermost side is used, and between chips E 1 and D 2 , on the other hand, the longest pattern formed on the outermost side is used. be. Therefore, when connecting signal pads of the same function on chips D- and E- arranged alternately, the signal line pattern shown in FIG. This means that the wiring equivalent to the two-layer wiring of the terminal connection portion shown was completed.
このように、以上述べた第５図では、これまで
述べた接続パターンを有する基板（図示せず）、
例えばサーマルヘツド上に、信号パツド１，２，
…，ｍ−１，ｍを有するチツプＤ−とＥ−の２種
のチツプを交互に並べ、ボンデイングによりその
信号線のパターンと、対応の信号パツドとを接続
する実装方法により得た半導体チツプの基板への
実装状態が示されているのである。 Thus, in FIG. 5 described above, a board (not shown) having the connection pattern described above,
For example, on the thermal head, signal pads 1, 2,
..., m-1, m, two types of chips, D- and E-, are arranged alternately and their signal line patterns are connected to the corresponding signal pads by bonding. The mounting state on the board is shown.
（発明の効果）
以上、詳細に説明したように、本発明によれ
ば、接続端子である信号パツドの配置の異つた半
導体チツプ、すなわち、交互に並べた場合にその
端子形成部分の信号パツドが、隣り合う半導体チ
ツプの信号パツドと左右対称となるように該信号
パツドを配置形成した半導体チツプを用いる構成
としたので、交叉部分のない接続パターンを有す
る基板が得られ、しかも、フイルムキヤリア、ダ
ミーパツドを用いることなく実現出来るので、半
導体チツプの小型化が図れ、したがつて、半導体
チツプの基板上への高密度実装が可能となり、
又、従来構成の半導体チツプと較べてみると、既
述の如くダミーパツドが不要な為、端子ピツチ、
換言すると大きなボンデイングピツチが得られ、
ボンデイング工程での生産性、歩留り等の向上が
期待出来るのである。更に、フイルムキヤリアを
用いる構成ではないので、半導体チツプの実装に
ワイヤーボンデイグ法等の採用も可能になる等、
優れた効果が期待できるのである。(Effects of the Invention) As described above in detail, according to the present invention, when semiconductor chips with different arrangement of signal pads, which are connection terminals, are arranged alternately, the signal pads of the terminal forming portions are arranged alternately. Since the configuration uses a semiconductor chip in which the signal pads are arranged and formed so as to be left and right symmetrical with the signal pads of adjacent semiconductor chips, a board having a connection pattern with no crossing parts can be obtained, and furthermore, a film carrier and a dummy pad can be used. Since it can be realized without using a semiconductor chip, it is possible to miniaturize the semiconductor chip, and therefore, it is possible to implement high-density mounting of the semiconductor chip on the substrate.
Also, compared to semiconductor chips with conventional configurations, as mentioned above, there is no need for dummy pads, so the terminal pitch,
In other words, a large bonding pitch can be obtained,
Improvements in productivity, yield, etc. in the bonding process can be expected. Furthermore, since the configuration does not use a film carrier, it is possible to use wire bonding methods for mounting semiconductor chips, etc.
Excellent effects can be expected.
第１図はこの種の実装の際に必要とされる２層
配線を説明する図、第２〜４図は従来の実装の一
例を説明する図で、第２図は実装する半導体チツ
プでの端子配置の一例を示す図、第３図は第２図
に示した半導体チツプと配線パターンを形成した
フイルムキヤリアとを接続した図、第４図は第３
図での半導体チツプとフイルムキヤリアとを複数
基板上に実装した場合の状態を示す図、第５図は
本発明に係る一実施例を示す図である。
１，２，…，ｍ−１，ｍは信号パツド、D1，
D2，…，E1，E2，…はチツプである。
Figure 1 is a diagram explaining the two-layer wiring required for this type of packaging, Figures 2 to 4 are diagrams explaining an example of conventional packaging, and Figure 2 is a diagram explaining the two-layer wiring required for this type of packaging. Figure 3 is a diagram showing an example of terminal arrangement; Figure 3 is a diagram showing the connection between the semiconductor chip shown in Figure 2 and a film carrier on which a wiring pattern is formed; Figure 4 is a diagram showing an example of the terminal arrangement.
FIG. 5 is a diagram showing a state in which a plurality of semiconductor chips and film carriers are mounted on a plurality of substrates, and FIG. 5 is a diagram showing an embodiment of the present invention. 1, 2, ..., m-1, m are signal pads, D 1 ,
D 2 ,..., E 1 , E 2 ,... are chips.
Claims (1)
半導体チツプを複数並べる実装方法において、 特定の端子配列を有する第１種類のICチツプ
と、 この第１種類のICチツプと左右対称の端子配
列を有する第２種類のICチツプとを交互に配置
し、 基板上に形成される接続パターンにより、これ
ら第１種類のICチツプと第２種類のICチツプと
の同一機能の端子相互を順次接続することを特徴
とする、 半導体チツプの基板への実装方法。[Claims] 1. In a mounting method in which a plurality of semiconductor chips with the same function are arranged on a connection pattern formed on a substrate, a first type of IC chip having a specific terminal arrangement; A second type of IC chip with a symmetrical terminal arrangement is arranged alternately, and a connection pattern formed on the substrate allows the first type of IC chip and the second type of IC chip to have terminals with the same function mutually. A method for mounting semiconductor chips on a substrate, characterized by sequentially connecting semiconductor chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14187983A JPS6034023A (en) | 1983-08-04 | 1983-08-04 | Mounting of semiconductor chip on substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14187983A JPS6034023A (en) | 1983-08-04 | 1983-08-04 | Mounting of semiconductor chip on substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6034023A JPS6034023A (en) | 1985-02-21 |
| JPH0351097B2 true JPH0351097B2 (en) | 1991-08-05 |
Family
ID=15302283
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14187983A Granted JPS6034023A (en) | 1983-08-04 | 1983-08-04 | Mounting of semiconductor chip on substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6034023A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5600363A (en) * | 1988-12-28 | 1997-02-04 | Kyocera Corporation | Image forming apparatus having driving means at each end of array and power feeding substrate outside head housing |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS582037A (en) * | 1981-06-29 | 1983-01-07 | Oki Electric Ind Co Ltd | Mounting method for ic and the like |
| JPS5862076A (en) * | 1981-10-12 | 1983-04-13 | Oki Electric Ind Co Ltd | Manufacture of double layered wiring part of thermal head |
-
1983
- 1983-08-04 JP JP14187983A patent/JPS6034023A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS582037A (en) * | 1981-06-29 | 1983-01-07 | Oki Electric Ind Co Ltd | Mounting method for ic and the like |
| JPS5862076A (en) * | 1981-10-12 | 1983-04-13 | Oki Electric Ind Co Ltd | Manufacture of double layered wiring part of thermal head |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6034023A (en) | 1985-02-21 |
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