JPH08148641A - Layout method and wire bonding method for semiconductor chip - Google Patents

Layout method and wire bonding method for semiconductor chip

Info

Publication number
JPH08148641A
JPH08148641A JP6280328A JP28032894A JPH08148641A JP H08148641 A JPH08148641 A JP H08148641A JP 6280328 A JP6280328 A JP 6280328A JP 28032894 A JP28032894 A JP 28032894A JP H08148641 A JPH08148641 A JP H08148641A
Authority
JP
Japan
Prior art keywords
bonding
pad
chip
wire
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6280328A
Other languages
Japanese (ja)
Inventor
Koji Matsubara
浩二 松原
Kazunori Kuki
一徳 九鬼
Shigeru Nakao
滋 中尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Priority to JP6280328A priority Critical patent/JPH08148641A/en
Publication of JPH08148641A publication Critical patent/JPH08148641A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To enable high density packaging by arranging chips, that are to be mounted on a board in a matrix, with their positions shifted, and by laying them out in a staggered pattern a large number of Au wires to connect the pads on the chips and those on the board. CONSTITUTION: Pads 2A, 2B,... are formed on the edge of a first chip 1A, and an opposed second chip 1B is placed with its position shifted by a distance equal to 1/2 of the interval of the pads. Pads 2A, 2B,... are formed on the edge of the second chip 1B. A distance required for maintaining the reliability of wire bonding is allowed between the first and second chips 1A, 1B, and bonding pads 4A, 4B,... are formed there in a staggered pattern. After the pad 2A on the first chip 1A and the bonding pad 4A are bonded together, the pad 2A on the second chip 1B and the bonding pad 4B are bonded together. Alternately bonding wires, as mentioned above, will enable high density packaging.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体チップの高密度搭
載を可能とする半導体チップの配置方法とワイヤーボン
ディング方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip arranging method and a wire bonding method which enable high density mounting of semiconductor chips.

【０００２】大量の情報を迅速に処理する必要から、半
導体集積回路は大容量化が行われているが、大容量化は
チップ面積の増大と云うよりも、単位素子の小形化によ
り行われていることから、単位素子を形成する電極や配
線などの微小化が進んで最小線幅はサブミクロン（Sub-
micron) に達している。Semiconductor integrated circuits have been increased in capacity because of the need to process a large amount of information quickly. However, increased capacity is achieved not by increasing the chip area but by reducing the size of unit elements. Therefore, the miniaturization of the electrodes and wiring that form the unit element has progressed, and the minimum line width is
micron) has been reached.

【０００３】このように半導体チップの小形化は進んで
いるが、ワイヤーボンディング接続法をとる場合はワイ
ヤーと半導体チップとの接触や、ワイヤーボンダーの操
作などの問題から半導体チップと回路基板のボンディン
グパッドとの間隔は余り縮小できないと云う問題があ
り、そのために半導体チップの高密度搭載には限界があ
った。As described above, the miniaturization of semiconductor chips is progressing. However, when the wire bonding connection method is adopted, the bonding pads between the semiconductor chip and the circuit board are caused by problems such as contact between the wire and the semiconductor chip and operation of the wire bonder. There is a problem in that the distance between and can not be reduced so much, which limits the high-density mounting of semiconductor chips.

【０００４】[0004]

【従来の技術】図４は従来の半導体チップの搭載方法と
ワイヤーボンディング方法を示す平面図（Ａ）と断面図
（Ｂ）であり、理解を容易にするために半導体チップ１
の周辺には４個づつ計16個のボンディング用のパッド２
を備えており、これに対応して多層セラミックなどより
形成される回路基板３の上に４個づつ計16個のボンディ
ングパッド４が形成されており、回路基板３の上に半導
体チップ１がマトリックス状に配列して搭載されている
場合を示している。2. Description of the Related Art FIG. 4 is a plan view (A) and a sectional view (B) showing a conventional semiconductor chip mounting method and wire bonding method.
There are 16 bonding pads 2 in total, 4 for each.
Corresponding to this, a total of 16 bonding pads 4 are formed on the circuit board 3 formed of a multilayer ceramic or the like, and the semiconductor chips 1 are arranged on the circuit board 3 in a matrix. It shows a case where they are mounted in a state of being arrayed.

【０００５】すなわち、半導体チップ（以下略してチッ
プ）１は接着材や共晶合金などを用いて回路基板（以下
略して基板）３の所定位置に接着固定させた後、ボンダ
ーによりチップ１のパッド２と基板３の上にパターン形
成されているボンディングパッド４とを金（Ａu ）線５
を用いてボンディングしている。That is, a semiconductor chip (hereinafter abbreviated as chip) 1 is bonded and fixed to a predetermined position of a circuit board (hereinafter abbreviated as substrate) 3 using an adhesive material or a eutectic alloy, and then a pad of the chip 1 is bonded by a bonder. 2 and a bonding pad 4 patterned on the substrate 3 with a gold (Au) wire 5
Is used for bonding.

【０００６】こゝで、ボンディングはワイヤーボンダー
を用いて行われているが、基板３の上にパターン形成さ
れているボンディングパッド４とチップ１との間隔、お
よび、対向して隣接するボンディングパッド４との間隔
には制限がある。Here, the bonding is performed using a wire bonder, but the distance between the bonding pad 4 formed on the substrate 3 and the chip 1 and the bonding pad 4 facing and adjoining each other. There is a limit to the interval between and.

【０００７】図４（Ｂ）はこれを説明するもので、左側
の第１のチップ１Ａの１番目のパッド２Ａと基板３の上
に形成されている１番目のボンディングパッド４Ａとを
Ａu線６を用いてワイヤーボンディングする場合、第１
のチップ１Ａと１番目のボンディングパッド４Ａとの間
隔αが狭すぎる場合は、Ａu 線６が第１のチップ１Ａの
角に接触する危険性があり、また、間隔αが広すぎる場
合はＡu 線６が垂れ下がって基板３に接触する危険性が
あり、そのため、間隔αの値として１ mm 以上３ mm 以
下が必要とされている。FIG. 4B illustrates this by connecting the first pad 2A of the first chip 1A on the left side and the first bonding pad 4A formed on the substrate 3 with the Au wire 6 and the second bonding pad 4A. When wire-bonding using
If the distance α between the chip 1A and the first bonding pad 4A is too small, there is a risk that the Au wire 6 will contact the corner of the first chip 1A, and if the distance α is too wide, the Au wire 6 There is a risk that 6 may hang down and come into contact with the substrate 3, and therefore the value of the interval α is required to be 1 mm or more and 3 mm or less.

【０００８】次に、基板上の第１のボンディングパッド
４Ａに熱圧着法によりボンディングを行ったワイヤーボ
ンダーはそのまゝの延長方向に移動してＡu 線６を引き
ちぎる操作が行われることから、第２のチップ１Ｂの１
番目のボンディングパッド４Ｂが接近して存在し、ま
た、既にワイヤーボンディングが行われている場合には
Ａu 線６を切断する危険性がある。Next, since the wire bonder bonded to the first bonding pad 4A on the substrate by the thermocompression bonding method is moved in the usual extension direction to tear off the Au wire 6, 1 of 2 chips 1B
There is a risk of cutting the Au wire 6 when the second bonding pad 4B is present close thereto and wire bonding has already been performed.

【０００９】これらのことから、図４（Ａ）に示すよう
に、マトリックス状に搭載してあるチップ１を囲んでパ
ターン形成されているボンディングパッド４は隣接する
チップ１のボンディングパッド４とボンディング操作の
際に接触が生じないように必要とする間隔をとってパタ
ーン形成する必要があり、これらのことから、高密度装
着には限界があった。From these facts, as shown in FIG. 4A, the bonding pads 4 formed in a pattern surrounding the chips 1 mounted in a matrix form a bonding operation with the bonding pads 4 of the adjacent chip 1. In this case, it is necessary to form a pattern with a necessary interval so that contact does not occur at the time, and therefore, there is a limit to high-density mounting.

【００１０】[0010]

【発明が解決しようとする課題】集積度が向上した半導
体集積回路の高密度装着法として、はんだボールを使用
するフリップチップ・タイプの装着法が実用化されてい
るが、ワイヤーボンディング方式をとる従来の装着法に
あっても高密度な装着法を実現したい。そこで、この方
法を見出すことが課題である。A flip-chip type mounting method using solder balls has been put into practical use as a high-density mounting method for a semiconductor integrated circuit having an improved degree of integration. I want to realize a high-density mounting method even with the mounting method of. Therefore, the challenge is to find this method.

【００１１】[0011]

【課題を解決するための手段】上記の課題はチップのパ
ッドと基板のパッドをボンディングするワイヤが相互に
入り込むよう隣接するチップをずらせると共に、従来よ
りも接近させて配置し、第１のチップの１番目のパッド
と基板上の１番目のボンディングパッドとをワイヤーボ
ンディングした後、隣接する第２のチップの１番目のパ
ッドと基板の２番目のボンディングパッドとをワイヤー
ボンディングするようにし、この操作を繰り返すことに
より解決することができる。SUMMARY OF THE INVENTION The above-mentioned problems are caused by shifting adjacent chips so that the wires for bonding the pads of the chip and the pads of the substrate enter into each other, and arranging them closer to each other than the conventional one. After wire-bonding the first pad of the substrate and the first bonding pad on the substrate, the first pad of the adjacent second chip and the second bonding pad of the substrate are wire-bonded. It can be solved by repeating.

【００１２】[0012]

【作用】本発明は基板上にマトリックス状に配列して装
着するチップを相互にずらせて配置することによって、
チップと基板の両方のパッドを結ぶ多数のＡu 線が互い
に同一線上になく、互い違いに入り込むよう形成するこ
とにより、高密度装着を可能にするものである。According to the present invention, by arranging the chips to be mounted in a matrix on the substrate so as to be displaced from each other,
By forming a large number of Au lines connecting pads of both the chip and the substrate so that they are not on the same line but in a staggered manner, high density mounting is possible.

【００１３】図１（Ａ）は本発明に係る配置法を示す平
面図、また、同図（Ｂ）は断面図である。以下、理解を
容易にするために、図４の従来と同じ番号をとって本発
明を説明する。FIG. 1A is a plan view showing an arrangement method according to the present invention, and FIG. 1B is a sectional view. In order to facilitate understanding, the present invention will be described below by using the same numbers as in the related art of FIG.

【００１４】本発明は隣接するチップをパッドの相互の
間隔の1/2 づつずらせることにより、今までパッドの形
成ができなかった領域に隣接するチップのパッドを形成
するものである。すなわち、図１（Ｂ）に示すように第
１のチップ１Ａの周辺に設けられている１番目のパッド
２Ａとボンディングする基板３の上の１番目のボンディ
ングパッド４Ａは第１のチップ１Ａからαの距離だけ隔
たった位置にあり、この距離を縮めることはできない
が、このαの位置に本発明は第２のチップ１Ｂの１番目
のパッド４Ｂを設け、これと、第２のチップ１Ｂの１番
目のパッド２Ａをワイヤーボンディングするものであ
る。According to the present invention, the pads of the chips adjacent to the regions where the pads could not be formed so far are formed by shifting the adjacent chips by 1/2 of the interval between the pads. That is, as shown in FIG. 1B, the first bonding pad 4A on the substrate 3 to be bonded with the first pad 2A provided around the first chip 1A is the same as the first chip 1A from the first chip 1A. However, according to the present invention, the first pad 4B of the second chip 1B is provided at the position of α, and this is not The second pad 2A is wire-bonded.

【００１５】図１（Ａ）はボンディングパッドの相互の
間隔の1/2 づつずらせて配置した４個のチップについて
の配列と、チップと基板のパッドとを相互にワイヤーボ
ンディングした状態を示している。FIG. 1 (A) shows an arrangement of four chips which are arranged so as to be displaced by 1/2 of the mutual spacing of the bonding pads and a state in which the chips and the pads of the substrate are wire-bonded to each other. .

【００１６】このように、今までワイヤーボンディング
の信頼性保持のために確保が必要であった空所に隣接チ
ップのボンディングパッドを設けることによりチップ装
着面積を縮小することができる。As described above, the chip mounting area can be reduced by providing the bonding pads of the adjacent chips in the vacant spaces which have been required to secure the reliability of wire bonding.

【００１７】[0017]

【実施例】【Example】

実施例１：図２は本発明に係るワイヤーボンディング方
法を示す平面図であって、第１のチップ１Ａの周辺に１
番目のパッド２Ａ，２番目のパッド２Ｂ，３番目のパッ
ド３Ｃ・・・と設けてあり、一方、対向する第２のチッ
プ１Ｂはパッドの間隔の1/2 づれて装着してあり、この
周辺には１番目のパッド２Ａ，２番目のパッド２Ｂ，３
番目のパッド３Ｃ・・・と設けてある。Embodiment 1 FIG. 2 is a plan view showing a wire bonding method according to the present invention, in which 1 is provided around the first chip 1A.
The second pad 2A, the second pad 2B, the third pad 3C, ... Are provided, while the opposing second chips 1B are mounted at 1/2 of the pad interval, and around this area. Is the first pad 2A, the second pad 2B, 3
The third pad 3C is provided.

【００１８】また、二つのチップ１Ａ，１Ｂの間にはそ
れぞれワイヤーボンディングの信頼性保持に必要な２ m
m の距離をとって１番目のボンディングパッド４Ａ，２
番目のボンディングパッド４Ｂ，３番目のボンディング
パッド４Ｃ・・・が互い違いに入り組んでパターン形成
されている。Further, between the two chips 1A and 1B, 2 m, which is necessary for maintaining reliability of wire bonding, is provided.
The first bonding pad 4A, 2 with a distance of m
The third bonding pad 4B, the third bonding pad 4C, ... Are alternately interdigitated and patterned.

【００１９】こゝで、従来のワイヤーボンディングはそ
れぞれチップ毎に行われていたが、本発明に係るチップ
配列法のように互い違いに入り組んでワイヤーを張る場
合は先にボンディングしてあるワイヤにボンダーが触
れ、切断を生ずる恐れがある。Heretofore, the conventional wire bonding has been carried out for each chip. However, in the case where the wires are arranged in a staggered manner as in the chip arrangement method according to the present invention, the bonder is bonded to the previously bonded wire. May touch and cause disconnection.

【００２０】そこで、隣接する二つのチップについて、
順次にワイヤーボンディングを行う、すなわち、第１の
チップ１Ａの１番目のパッド２Ａと基板上に設けられて
いる１番目のボンディングパッド４Ａとをボンディング
した後、第２のチップ１Ｂの１番目のパッド２Ａと基板
上に設けられている２番目のボンディングパッド４Ｂと
をボンディングする。Therefore, regarding two adjacent chips,
Wire bonding is performed sequentially, that is, after bonding the first pad 2A of the first chip 1A and the first bonding pad 4A provided on the substrate, the first pad of the second chip 1B is bonded. 2A and the second bonding pad 4B provided on the substrate are bonded.

【００２１】そして、次に、第１のチップ１Ａの２番目
のパッド２Ｂと基板上に設けられている２番目のボンデ
ィングパッド４Ｃとをボンディングした後、第２のチッ
プ１Ｂの２番目のパッド２Ｂと基板上に設けられている
４番目のボンディングパッド４Ｄとをボンディングす
る。Then, after bonding the second pad 2B of the first chip 1A and the second bonding pad 4C provided on the substrate, the second pad 2B of the second chip 1B is bonded. And the fourth bonding pad 4D provided on the substrate are bonded.

【００２２】このように交互にワイヤーボンディングを
行うことにより信頼性の高いボンディングを行うことが
できる。 実施例２：図３はチップ周辺に設けてあるパッドと回路
基板上に設けてあるボンディングパッドをワイヤーボン
ディングすると共にリードフレームにもワイヤーボンデ
ィングした状態を示す平面図である。By alternately performing wire bonding in this manner, highly reliable bonding can be performed. Example 2 FIG. 3 is a plan view showing a state in which the pads provided around the chip and the bonding pads provided on the circuit board are wire-bonded and also to the lead frame.

【００２３】すなわち、第１のチップ１Ａと第２のチッ
プ１ＢはそれぞれＡu 線６が交互に入り組むようにワイ
ヤーボンディングを行うが、第１のチップ１Ａからの配
線は２個のビアホール８と第２のチップ１Ｂの下を通る
基板内配線９によりボンディングパッド４に導かれ、リ
ードフレーム10とワイヤーボンディングすることにより
高密度装着を行った例である。That is, the first chip 1A and the second chip 1B are wire-bonded so that the Au wires 6 are alternately interdigitated, but the wiring from the first chip 1A has two via holes 8 and a second chip. In this example, the high-density mounting is performed by being guided to the bonding pad 4 by the wiring 9 in the substrate passing under the chip 1B and wire-bonded to the lead frame 10.

【００２４】[0024]

【発明の効果】本発明は半導体チップをボンディングパ
ッドの間隔の1/2 ピッチずらせて装着すると共に、ボン
ディングパッドを相互に入り込ませ形成するもので、本
発明の実施により高密度装着が可能となる。According to the present invention, the semiconductor chips are mounted by shifting the pitch of the bonding pads by 1/2 pitch, and the bonding pads are formed so as to be interdigitated with each other. By implementing the present invention, high-density mounting becomes possible. .

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明に係る半導体チップの配置とワイヤー
ボンディング方法を示す平面図（Ａ）と断面図（Ｂ）で
ある。FIG. 1 is a plan view (A) and a cross-sectional view (B) showing an arrangement of semiconductor chips and a wire bonding method according to the present invention.

【図２】 本発明に係るワイヤーボンディング方法を示
す平面図である。FIG. 2 is a plan view showing a wire bonding method according to the present invention.

【図３】 リードフレームへのワイヤーボンディング方
法を示す平面図である。FIG. 3 is a plan view showing a method of wire bonding to a lead frame.

【図４】 従来の半導体チップの配置とワイヤーボンデ
ィング方法を示す平面図（Ａ）と断面図（Ｂ）である。FIG. 4 is a plan view (A) and a sectional view (B) showing a conventional semiconductor chip arrangement and wire bonding method.

【符号の説明】[Explanation of symbols]

１ 半導体チップ ２ パッド ３ 回路基板 ４ ボンディングパッド ６ Ａu 線 ８ ビアホール 10 リードフレーム 1 semiconductor chip 2 pad 3 circuit board 4 bonding pad 6 Au wire 8 via hole 10 lead frame

フロントページの続き (72)発明者 中尾 滋 愛知県春日井市高蔵寺町二丁目1844番２ 富士通ヴィエルエスアイ株式会社内Continued Front Page (72) Inventor Shigeru Nakao 1844-2, Kozoji-cho, Kasugai-shi, Aichi Prefecture Fujitsu Vielle SII Co., Ltd.

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 複数の半導体チップを回路基板上にマト
リックス状に配置して装着した後、該装着位置を囲んで
設けてあるボンディングパッドと該半導体チップのパッ
ドとをそれぞれワイヤーボンディングして回路接続を行
う半導体チップの配置方法において、 前記回路基板上に隣接して配置する半導体チップの装着
位置を相互にずらせると共に、該回路基板上の前記ボン
ディングパッドを互いに隣接する各々の半導体チップの
ボンディング領域内に入り込ませて配置することを特徴
とする半導体チップの配置方法。1. A plurality of semiconductor chips are arranged and mounted on a circuit board in a matrix form, and a bonding pad provided surrounding the mounting position and a pad of the semiconductor chip are respectively wire-bonded to form a circuit connection. In the method for arranging semiconductor chips, the mounting positions of the semiconductor chips adjacent to each other on the circuit board are shifted from each other, and the bonding pads on the circuit board are adjacent to each other. A method of arranging a semiconductor chip, characterized in that the semiconductor chip is arranged so as to be inserted inside. 【請求項２】 請求項１記載の配置方法をとって回路基
板上に配置されている第１の半導体チップと第２の半導
体チップについて、 回路基板上に設けられている第１のボンディングパッド
と該ボンディングパッドに対応する第１の半導体チップ
のパッドをワイヤーボンディングする第１の工程と、 前記回路基板に設けられている第２のボンディングパッ
ドと該ボンディングパッドに対応する第２の半導体チッ
プのパッドをワイヤーボンディングする第２の工程と、 該第１の工程と第２の工程を繰り返す第３の工程を含む
ことを特徴とするワイヤーボンディング方法。2. The first semiconductor chip and the second semiconductor chip arranged on the circuit board by the arrangement method according to claim 1, and a first bonding pad formed on the circuit board. A first step of wire bonding a pad of a first semiconductor chip corresponding to the bonding pad, a second bonding pad provided on the circuit board, and a pad of a second semiconductor chip corresponding to the bonding pad A wire bonding method comprising: a second step of wire-bonding the wire; and a third step of repeating the first step and the second step.
JP6280328A 1994-11-15 1994-11-15 Layout method and wire bonding method for semiconductor chip Withdrawn JPH08148641A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6280328A JPH08148641A (en) 1994-11-15 1994-11-15 Layout method and wire bonding method for semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6280328A JPH08148641A (en) 1994-11-15 1994-11-15 Layout method and wire bonding method for semiconductor chip

Publications (1)

Publication Number Publication Date
JPH08148641A true JPH08148641A (en) 1996-06-07

Family

ID=17623482

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6280328A Withdrawn JPH08148641A (en) 1994-11-15 1994-11-15 Layout method and wire bonding method for semiconductor chip

Country Status (1)

Country Link
JP (1) JPH08148641A (en)

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