JPH0350835A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize a p-MOSFET which increases the density of components and the speed of a semiconductor LSI by adding a small amount of n-type impurities to a polycrystalline silicon gate first, and successively adding p-type impurities so as to change a great part of polycrystalline silicon gate into p. CONSTITUTION:An SiO2 gate insulating film 2 is formed on the top of an n-type silicon substrate 1, and moreover a polysilicon film 3 to become a gate electrode is grown thereon. An SiO2 film 4 is stacked, and P<+> of n-type impurities is implanted. Furthermore, the SiO2 film 4 is removed, and a resist film 5 is formed, and besides a polysilicon film 3 is formed in the shape of a gate electrode. An SiO2 film 6 is grown, and ion implantation is done using BF2<+> to the p-type impurity source, so as to change the polysilicon film 3 into P<+>-type, and at the same time ion implantation for source 7 and drain formation areas is done into the substrate 1 on both sides of it. A MOS transistor is completed by the formation of a passivation film 9 and the opening of a contact hole and the making of a metallic electrode 10 piercing the hole, succeeding to the heat treatment.

Description

Detailed Description of the Invention <Industrial Application Field> The present invention provides a P-channel Δ10S type field effect transistor (
The present invention relates to a manufacturing method for P-8105FET).

<Conventional technology> Ultra LSIs represented by DRAM, SRAM, etc.
The number of records and ministers increased at a rate of four times a year.
Although it is expected that the technology will continue to develop in the future, the miniaturization of semiconductor elements used in LSIs has become the most important issue in order to improve the degree of integration within this limited chip area and to increase the speed of signal processing. , technology for miniaturizing seedwood has been developed.

On the other hand, complementary MOS) transistor LS has divine features such as low power consumption and high noise tolerance.
2MO5FETs that make up I (C-MO5LSI)
In order to reduce and simplify the manufacturing process, polycrystalline silicon doped with n-type impurities (p-polysilicon) is susceptible to contamination by alkali metal ions such as Na, etc. Polycrystalline silicon doped with the same n-type impurity (n-polysilicon) was used for the gate voltage.

<Problem to be solved by the invention> When a gate of n-polysilicon is formed in a P-MOSFET as in the past, the channel /L/ of the FET is
This is not a surface channel type, which is formed from the interface in the substrate in contact with the gate oxide layer made of n-polysilicon, but a so-called buried channel type, which is formed in the substrate away from the interface.

Even if the characteristics of LSIs using buried channel MO5FETs as described above are improved by miniaturizing the process,
It is known that the characteristics of the buried channel type P-MO5FET are significantly degraded due to the short channel effect in which the actual channel length is shortened.

The above embedded channel type P-M OS F E
The deterioration in characteristics due to the short channel effect when T is miniaturized can be prevented by using a surface channel type P-MO8FET with p-polysilicon as the gate electrode, but
-Polysilicon+7)'7'-)1119, the above-mentioned problem of contamination by alkali metal ions cannot be avoided. In order to prevent contamination caused by alkali metals, a method has been proposed in which the silicon gate is coated with a silicon nitride film, but it is said that covering the p-polysilicon gate with a silicon nitride film requires more complicated steps. A problem occurs.

An object of the present invention is to provide a method for manufacturing a surface channel type P-MO8FET having a p-polysilicon gate without the need for adding complicated steps and without problems of deterioration due to contamination with alkali metal ions.

Means for Solving the Problems> The method of the present invention for achieving the above objects uses an N-MO transistor whose gate electrode is made of polysilicon doped with n-type impurities.
SFET has strong resistance to alkali metal contamination:
It was developed by focusing on the fact that there is no deterioration due to contamination, and a small amount of P-type impurity is added to the p-polysilicon that becomes the gate electron microscope of surface channel type P-MO5FET, which greatly changes its conductivity. This is a method in which n-type impurities are added to a certain degree. By adding a small amount of n-type impurity, it is possible to create a product that is resistant to dialkali metal ion contamination.
- It has become possible to fabricate polysilicon gates. <Function> The p-polysilicon of the present invention to which a small amount of n-type impurity is added can also be used as the gate electrode layer of a P MOSFET.
It is possible to provide high resistance to contamination by alkali metal ions such as - MO3FET can be manufactured.

<Example> Embodiments of the present invention will be described with reference to the drawings.

Example of Effect Measurement In the first example of the present invention, the amount of n-type impurity added was changed.
We fabricated a metal-insulating film-semiconductor (MIS) diode using seed p-polysilicon and evaluated its high-frequency capacity.
The effect of the present invention was measured from the relationship between the dose of n-type impurity and the resistance of the p-polysilicon film to alkali metal contamination from the shift amount of the flat band potential (Vfb) through the custom-made measurement of voltage (high-rise ec-v). It is something to do.

The outline process of the MIS diode of this embodiment for measuring the effect is shown in cross section in FIGS. 6 to 9. In this example, an ion implantation method was used to add an n-type impurity to the flp-polysilicon film, but other methods such as thermal diffusion or addition during film formation can also be used to add the impurity. be.

Figure 6 shows that a silicon oxide (S102) film 2 with a thickness of 100A is formed on the upper surface of a P-type silicon substrate 1 by thermal oxidation, and then a polysilicon film 3, which also serves as the gate electrode material, is formed by chemical vapor deposition. 3000^ deposited by CVD method.

The following figure 7 shows that a thin 5i02 film 4 for protection during ion implantation is formed on the polysilicon film 3, and phosphorus ions (P), which will become n-type impurities, are heated at an accelerating voltage of 60 kV using the sample number shown in Table 1. Ions were implanted at a dose corresponding to .

Table 1 Subsequently, in order to make the polysilicon film 3 P-type, boron fluoride ions (BF2) were used as a source, and ion implantation and activation heat treatment were performed at 5 x 1015 doses/cm at an accelerating voltage of 40 kV.

Then, S i 02 '14 k is removed by hydrofluoric acid treatment, a resin pattern 5 is formed, and an ftr mask K is removed.
Ion etching (RIE)? m8 by f
After forming the polysilicon electrode 3 in the shape shown in the figure, the resist film 5 was removed to complete the fabrication of the MIS diode of the ninth factor. The fabricated MIS diodes with various P doses were immersed in about 0.1% NaOH, then washed with water and washed with water for 2 hours.
The material was subjected to severe Na contamination treatment by drying at 00°C.

FIG. 10 is a table showing the shift amount of Vfb according to high frequency C-■ custom measurements of various MIS diodes before and after the Na contamination treatment using NaOH.

From FIG. 10, it can be seen that the shift of Vfb of each MIS diode -B becomes smaller as the dose of P+ added to the polysilicon film 3 increases;
1014Dose/c4K! Therefore, the shift amount of Vfb is small (it can be seen that the influence of Na+ contamination is suppressed).

Embodiments of the Invention An embodiment of the invention describes the method of the invention '6P-MOSFET
The manufacturing process is shown in Figures 1 to 5. Although this example shows the manufacturing process of one transistor, it is possible to use it for LSI using a normal method.

Figure 1 shows a state in which an 8102 gate insulating film 2 of about 10 OA is formed on top of an n-type silicon substrate 1z by thermal oxidation, and then a polysilicon film 3, which will become the gate electrode, is grown to 3000 Å by low-pressure CVD. , is a bear. Subsequently, 5i021-4 was added at 10OA by CVD to protect the ion implantation.
Then, the n-type impurity P+2! -2nd state of injecting 5X10"Dose/cd at an accelerating voltage of 60kv
Shown in the figure.

Furthermore, the 5i02 film 4 was removed by hydrofluoric acid treatment, a resist film 5 was formed by photolithography, and the polysilicon film 3 was shaped into a gate electrode by RIE, as shown in FIG. Furthermore, as shown in Figure 4, 51 of about 10OA
02Mo6 was grown by CVD, and BF2 was used as an n-type impurity source.
5 x 1015D at an accelerating voltage of 40kV using
ose/c+# ion implantation is performed to form a polysilicon film 3.
At the same time, ions are implanted into the substrate 11 on both sides of the source 7 and the drain type. After this ion implantation, following a heat treatment to activate the impurity, a passivation film 9 is formed, a contact hole is opened, and a metal electrode 10 is formed to pass through the hole, completing the MOS transistor as shown in Figure 5. be. The above embodiments are used to form a resist pattern of the resist film 4.
Although II lithography was used, other methods capable of ultra-CD processing using electron beams, X-rays, etc. can also be used.

By using the above method, the P-M-O3FET whose gate is formed with a p-type polysilicon film doped with n-type impurities becomes a surface channel type, and has a short channel effect until the gate length is reduced to 0.5 μm or less. No deterioration of device characteristics occurred. This is a MOS used for a polysilicon tegate with only n-type impurities added without adding n-type impurities.
There is no deterioration in electrical characteristics compared to FET, and
No deterioration in characteristics due to contamination with alkali metal ions occurred.
By using a MOSFET gate, the resistance to alkali metal ion contamination can be increased by a short distance, and there is no deterioration in device characteristics due to the conventional short channel effect, so high integration can be achieved by micro-processing. C-MO8
A high-performance LSI P-MO3FET can be constructed.

[Brief explanation of drawings]

FIG. 7, FIG. 8, and FIG. 9 show MI for measuring the effect of the present invention.
FIG. 10 is a cross-sectional view showing the manufacturing process of the S-configuration diode, and is a graph showing the effects of the present invention. 1.11...Silicon substrate, 2. ', 12...
S102WOa%, 3...Polysilicon film,
4, 6... Protective S 02 film, 5... Resist film, 7... Source region, 8... Drain region, 9... Passivation film, 10... Metal electrode.

Claims (1)

[Claims] 1. P-channel MOS with polycrystalline silicon gate
In manufacturing a type field effect transistor, first a small amount of n-type impurity is added to the polycrystalline silicon gate, and then a p-type impurity is added to make most of the polycrystalline silicon gate P-type. A method for manufacturing a semiconductor device, characterized by: