JPH0350835A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0350835A JPH0350835A JP18828489A JP18828489A JPH0350835A JP H0350835 A JPH0350835 A JP H0350835A JP 18828489 A JP18828489 A JP 18828489A JP 18828489 A JP18828489 A JP 18828489A JP H0350835 A JPH0350835 A JP H0350835A
- Authority
- JP
- Japan
- Prior art keywords
- film
- type
- gate
- polysilicon
- sio2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 5
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 36
- 239000012535 impurity Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims description 13
- 230000005669 field effect Effects 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 abstract description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 238000005468 ion implantation Methods 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052681 coesite Inorganic materials 0.000 abstract description 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 229910052682 stishovite Inorganic materials 0.000 abstract description 5
- 229910052905 tridymite Inorganic materials 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 238000002161 passivation Methods 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract 4
- 238000011109 contamination Methods 0.000 description 14
- 230000000694 effects Effects 0.000 description 9
- 230000006866 deterioration Effects 0.000 description 7
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- 229910001413 alkali metal ion Inorganic materials 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 229910052783 alkali metal Inorganic materials 0.000 description 3
- 150000001340 alkali metals Chemical class 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000010306 acid treatment Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- -1 phosphorus ions Chemical class 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910015900 BF3 Inorganic materials 0.000 description 1
- 101100081489 Drosophila melanogaster Obp83a gene Proteins 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、大規模実情回路(LSI)への鳥密度化に適
したPチャンネルのΔ10S型電界効果トランジヌタ(
P−八l05FET)の」ジ造方法に関するものである
。Detailed Description of the Invention <Industrial Application Field> The present invention provides a P-channel Δ10S type field effect transistor (
The present invention relates to a manufacturing method for P-8105FET).
〈従来の技rrir >
DRAM、SRAM等で代表される超LSIは、はぼ3
年に4倍の割合でその記・臣容量などを増大しておシ、
今後も引続いて発展すると考えられるが、この限られた
チップ面積への集積度向上と、信号処理の高速化などの
ため、LSIに用いる半導体素子の微細化が最も重要な
課題になっていて、種檀の微細化技術が開発されている
。<Conventional technology> Ultra LSIs represented by DRAM, SRAM, etc.
The number of records and ministers increased at a rate of four times a year.
Although it is expected that the technology will continue to develop in the future, the miniaturization of semiconductor elements used in LSIs has become the most important issue in order to improve the degree of integration within this limited chip area and to increase the speed of signal processing. , technology for miniaturizing seedwood has been developed.
弔
一方、低電力消費電力が少ない、雑音余裕度が大きいな
ど神々の特徴をもつ相補型M OS )ランジスタLS
I (C−MO5LSI )を構成する2MO5FET
は、製造工程数を少なくし簡略化する、n型不純物を添
加した多結晶シリコン(pポリシリコン)がNa な
どのアルカリ金属イオンによる汚染に対して弱い等の理
由から、そのN−MOSFETのゲートと同じn型不純
物を添加した多結晶シリコン(n−ポリシリコン)をそ
のゲート電擺に用いていた。On the other hand, complementary MOS) transistor LS has divine features such as low power consumption and high noise tolerance.
2MO5FETs that make up I (C-MO5LSI)
In order to reduce and simplify the manufacturing process, polycrystalline silicon doped with n-type impurities (p-polysilicon) is susceptible to contamination by alkali metal ions such as Na, etc. Polycrystalline silicon doped with the same n-type impurity (n-polysilicon) was used for the gate voltage.
〈発明が1解決しようとする課題〉
従来のように、P−MOSFETにn−ポリシリコンの
ゲートヲ形成すると、そのFETのチャンネ/L/は、
n−ポリシリコンを作製したゲート酸化暎に接した基板
中に界面から形成する表面チャンネル型でなく、その界
面から離れた基板中に形成するいわゆる埋め込みチャン
ネル型になる。<Problem to be solved by the invention> When a gate of n-polysilicon is formed in a P-MOSFET as in the past, the channel /L/ of the FET is
This is not a surface channel type, which is formed from the interface in the substrate in contact with the gate oxide layer made of n-polysilicon, but a so-called buried channel type, which is formed in the substrate away from the interface.
以上のような埋め込みチャンネル型MO5FETを用い
るLSIは、工程の微細化による特性改善を図っても、
実質的なチャンネル長が短がくなる短チャンネル効果に
より、その埋め込みチャンネル型P−MO5FETの特
性が顕著に低下することが知られている。Even if the characteristics of LSIs using buried channel MO5FETs as described above are improved by miniaturizing the process,
It is known that the characteristics of the buried channel type P-MO5FET are significantly degraded due to the short channel effect in which the actual channel length is shortened.
以上の埋め込みチャンネル型P −M OS F E
Tを微細化したときの短チャンネル効果による特性低下
は、p−ポリシリコンをゲート電極にした表面チャンネ
ル型P−MO8FETにすれば防ぐことが可能だが、p
−ポリシリコン+7)’7’−)1119成すると、前
記のアルカリ金属イオンによる汚染の問題が避けられな
い。このアルカリ金属による汚染’e防<”ため、その
シリコンゲートを窒化シリコン膜で被覆する方法も提案
されているがp−ポリシリコンゲートを窒化シリコン膜
で被覆するには煩雑な工程が増加するという問題が発生
する。The above embedded channel type P-M OS F E
The deterioration in characteristics due to the short channel effect when T is miniaturized can be prevented by using a surface channel type P-MO8FET with p-polysilicon as the gate electrode, but
-Polysilicon+7)'7'-)1119, the above-mentioned problem of contamination by alkali metal ions cannot be avoided. In order to prevent contamination caused by alkali metals, a method has been proposed in which the silicon gate is coated with a silicon nitride film, but it is said that covering the p-polysilicon gate with a silicon nitride film requires more complicated steps. A problem occurs.
本発明は複雑な工程を追加する必要がなく、アルカリ金
属イオンの汚染による劣化問題のないp−ポリシリコン
のゲートをもつ表面チャンネル型P−MO8FETの製
造方法を提供することを目的としている。An object of the present invention is to provide a method for manufacturing a surface channel type P-MO8FET having a p-polysilicon gate without the need for adding complicated steps and without problems of deterioration due to contamination with alkali metal ions.
く課題を解決するための手段〉
以上の目的を達成する本発明の方法は、n型不純物を添
加したポリシリコンをゲート電極の材料にしたN−MO
SFETがアルカリ金属の汚染:・で強い耐性をもち、
その汚染による劣化がないことに着目することで開発し
たもので、表面チャンネル型P−MO5FETのゲート
電顕になるp−ポリシリコンに添加したP型不純物に量
が少なく、その導電性を大きく変えない程度のn型不純
物を添加しておく方法である。以上の少量のn型不純物
の添加によジアルカリ金属イオンの汚染に耐性の烏いp
−ポリシリコンゲートの作製が可能になった0
〈作 用〉
本発明のn型不純物も少量添加したp−ポリシリコンは
、P MOSFETのゲート電層にしても、Na
等のアルカリ金属イオンの汚染に対し高い耐性をもたせ
ることが可能となり、従って、半導体LSIの集積度向
上、高速化を図る微に@加工カできるp−ポリシリコン
のゲートをもった表面チャンネル型P−MO3FETの
作製ができる。Means for Solving the Problems> The method of the present invention for achieving the above objects uses an N-MO transistor whose gate electrode is made of polysilicon doped with n-type impurities.
SFET has strong resistance to alkali metal contamination:
It was developed by focusing on the fact that there is no deterioration due to contamination, and a small amount of P-type impurity is added to the p-polysilicon that becomes the gate electron microscope of surface channel type P-MO5FET, which greatly changes its conductivity. This is a method in which n-type impurities are added to a certain degree. By adding a small amount of n-type impurity, it is possible to create a product that is resistant to dialkali metal ion contamination.
- It has become possible to fabricate polysilicon gates. <Function> The p-polysilicon of the present invention to which a small amount of n-type impurity is added can also be used as the gate electrode layer of a P MOSFET.
It is possible to provide high resistance to contamination by alkali metal ions such as - MO3FET can be manufactured.
〈実施例〉 本発明の実施例を図面を参照して説明する。<Example> Embodiments of the present invention will be described with reference to the drawings.
効果測定の実施例
本発明の第1実施例は、n型不純物の添加量を変えた4
種のp−ポリシリコン喚を用いた金属−絶縁膜一半導体
(M I S )ダイオード作製し、その高周波容量−
電圧(高層ec −v )特注の測定からフラットバン
ド電位(Vfb )のシフト量からn型不純物のドーズ
量と、該p−ポリシリコン膜のアルカリ金属汚染の耐性
の関係から本発明の効果を測定するものである。Example of Effect Measurement In the first example of the present invention, the amount of n-type impurity added was changed.
We fabricated a metal-insulating film-semiconductor (MIS) diode using seed p-polysilicon and evaluated its high-frequency capacity.
The effect of the present invention was measured from the relationship between the dose of n-type impurity and the resistance of the p-polysilicon film to alkali metal contamination from the shift amount of the flat band potential (Vfb) through the custom-made measurement of voltage (high-rise ec-v). It is something to do.
この効果測定用実施例のMISダイオードは、その概要
プロセスの断面を第6図から第9図で示している。この
実施例でflp−ポリシリコン膜へのn型不純物添茄イ
オン注入法を用いたが、この不純物添加は熱拡散法、又
は膜形成時の添加法など他の添加方法を用いることが可
能である。The outline process of the MIS diode of this embodiment for measuring the effect is shown in cross section in FIGS. 6 to 9. In this example, an ion implantation method was used to add an n-type impurity to the flp-polysilicon film, but other methods such as thermal diffusion or addition during film formation can also be used to add the impurity. be.
第6図はP型シリコン基板1の上面を熱酸化法により膜
厚100Aの酸化シリコン(s 102)嘆2を形成し
、続いてゲート@極材料にもなるポリシリコン膜3を化
学気相成長法(CVD)によ択3000^堆積している
。Figure 6 shows that a silicon oxide (S102) film 2 with a thickness of 100A is formed on the upper surface of a P-type silicon substrate 1 by thermal oxidation, and then a polysilicon film 3, which also serves as the gate electrode material, is formed by chemical vapor deposition. 3000^ deposited by CVD method.
次の第7図はポリシリコン膜3の上に薄いイオン注入時
の保護用5i02膜4を形成し、n型不純物になる燐イ
オン(P )を60 kVの加速電圧により第1表の試
料番号に対応するドース量でイオン注入した。The following figure 7 shows that a thin 5i02 film 4 for protection during ion implantation is formed on the polysilicon film 3, and phosphorus ions (P), which will become n-type impurities, are heated at an accelerating voltage of 60 kV using the sample number shown in Table 1. Ions were implanted at a dose corresponding to .
第1表
続いてポリシリコン膜3をP型化するためフッ化ホウ素
イオン(BF2 )をソースにして、40kVの加速
電圧による5 X 1015Dose/cmのイオン注
入と活性化熱処理をした。Table 1 Subsequently, in order to make the polysilicon film 3 P-type, boron fluoride ions (BF2) were used as a source, and ion implantation and activation heat treatment were performed at 5 x 1015 doses/cm at an accelerating voltage of 40 kV.
緯いてフッ酸処理によりS i 02 ’14 k除去
し、レジヌトパターン5の形成と、そしftrマスクK
した戻応惟イオンエツチング(RIE)?fによりm8
図に示した形状のポリシリコン電極3にした上、レジス
ト膜5を除去することで第9因のMISダイオードの作
製全行った。作製した各種P ドズ量のMISダイオー
ドには、約0.1%のNaOHに浸漬した後、水洗と2
00℃での乾燥をするという苛酷なNa の汚染をす
る処理をした。Then, S i 02 '14 k is removed by hydrofluoric acid treatment, a resin pattern 5 is formed, and an ftr mask K is removed.
Ion etching (RIE)? m8 by f
After forming the polysilicon electrode 3 in the shape shown in the figure, the resist film 5 was removed to complete the fabrication of the MIS diode of the ninth factor. The fabricated MIS diodes with various P doses were immersed in about 0.1% NaOH, then washed with water and washed with water for 2 hours.
The material was subjected to severe Na contamination treatment by drying at 00°C.
以上のNaOHによるNa 汚染処理の処理前と処理
後の各種M I Sダイオードの高周波C−■特注測定
によるVfbのシフト量を表にしたのが第10図である
。FIG. 10 is a table showing the shift amount of Vfb according to high frequency C-■ custom measurements of various MIS diodes before and after the Na contamination treatment using NaOH.
第10図から、各M I SダイオードのVfbのシフ
ト−Bば、そのポリシリコン膜3に添加したP+のドー
ズ量が多くなると小さくなり、そのドーズ量が5 X
1014Dose/c4 K !るとVfbのシフト量
は小さ(Na+汚染の影響が抑制されていることが分る
。From FIG. 10, it can be seen that the shift of Vfb of each MIS diode -B becomes smaller as the dose of P+ added to the polysilicon film 3 increases;
1014Dose/c4K! Therefore, the shift amount of Vfb is small (it can be seen that the influence of Na+ contamination is suppressed).
本発明の実施例
本発明の実施例は、本発明の方法’6P−MOSFET
に適用したもので、その作製の工程を第1図から男5図
迄に示している。この実施例は1個のトランジスタの作
製工程を示したが、通常の方法でLSIに用いることは
可能である。Embodiments of the Invention An embodiment of the invention describes the method of the invention '6P-MOSFET
The manufacturing process is shown in Figures 1 to 5. Although this example shows the manufacturing process of one transistor, it is possible to use it for LSI using a normal method.
第1図は、n型シリコン基板1zの上置に熱酸化法によ
る約10OAの8102ゲート絶縁膜2を形成した上に
、ゲート電極になるポリシリコン膜3を減圧CVDによ
り3000^成長させた状、熊である。続いてイオン注
入の保護としてCVDにより5i021嘆4を10OA
堆積し、続いて、n型不純物のP+2!−60kvの加
速電圧で5X10”Dose/cd注入する状態ヲ第2
図に示している。Figure 1 shows a state in which an 8102 gate insulating film 2 of about 10 OA is formed on top of an n-type silicon substrate 1z by thermal oxidation, and then a polysilicon film 3, which will become the gate electrode, is grown to 3000 Å by low-pressure CVD. , is a bear. Subsequently, 5i021-4 was added at 10OA by CVD to protect the ion implantation.
Then, the n-type impurity P+2! -2nd state of injecting 5X10"Dose/cd at an accelerating voltage of 60kv
Shown in the figure.
更に、フッ酸処理で5i02膜4を除去し、ホトリソグ
ラフィでレジスト膜5の形成を行った上、RIEにより
ポリシリコン膜3をゲート電極の形状にしたのが第3図
である。更に続いて第4図のように、約10OAの51
02模6をCVDで成長させ、n型不純物源にBF2
を用いて40kVの加速電圧で、5 X 1015D
ose/c+#のイオン注入を行ないポリシリコン膜3
をP+型にすると同時にその両側の基板11中にソース
7とドレイン形戎頑域のイオン注入′fj:行っている
。このイオン注入後、その不純物を活性化させる熱処理
に続いて、パシベーション4膜9の形成コンタクトホー
ルの開口とそのホールを貫通する金寓電極10の作製で
MOSトランジスタが完成したのが第5図である。以上
の実施例はレジスト膜4のレジストパターン形成にホ)
IIソグラフィを用いたが、他の電子ビームやX線な
どを用いた超CD、 、41加工が可能な方法を用いる
こともできる。Furthermore, the 5i02 film 4 was removed by hydrofluoric acid treatment, a resist film 5 was formed by photolithography, and the polysilicon film 3 was shaped into a gate electrode by RIE, as shown in FIG. Furthermore, as shown in Figure 4, 51 of about 10OA
02Mo6 was grown by CVD, and BF2 was used as an n-type impurity source.
5 x 1015D at an accelerating voltage of 40kV using
ose/c+# ion implantation is performed to form a polysilicon film 3.
At the same time, ions are implanted into the substrate 11 on both sides of the source 7 and the drain type. After this ion implantation, following a heat treatment to activate the impurity, a passivation film 9 is formed, a contact hole is opened, and a metal electrode 10 is formed to pass through the hole, completing the MOS transistor as shown in Figure 5. be. The above embodiments are used to form a resist pattern of the resist film 4.
Although II lithography was used, other methods capable of ultra-CD processing using electron beams, X-rays, etc. can also be used.
以上の方法によシ、n型不純物を添加したp型ポリシリ
コン膜でゲートを形成したP−M−O3FETは、表面
チャンネル型になり、そつゲート長を0.5μm以下に
するまで短チャンネル効果による素子特性の低下はおき
なかった。壕だ、これはn型不純物を添加しないn型不
純物のみ添加したポリシリコンテゲートに用いたMOS
FETと比較して電気的特性での低下がなく、かつ、
アルカリ金属イオンの汚染による特性の低下は生じなか
ったO
〈発明の効果〉
本発明の如くp型ポリシリコン膜にn型も添加してP
M OS F E Tのゲートにすることでアルカリ
金属イオン汚染の耐性を擺めで高くすることができ、か
つ、従来の短チャンネル効果による素子特性の低下もな
いので、微、18加工により高集積化されたC−MO8
LSIの高性能P−MO3FETを構成することができ
る。By using the above method, the P-M-O3FET whose gate is formed with a p-type polysilicon film doped with n-type impurities becomes a surface channel type, and has a short channel effect until the gate length is reduced to 0.5 μm or less. No deterioration of device characteristics occurred. This is a MOS used for a polysilicon tegate with only n-type impurities added without adding n-type impurities.
There is no deterioration in electrical characteristics compared to FET, and
No deterioration in characteristics due to contamination with alkali metal ions occurred.
By using a MOSFET gate, the resistance to alkali metal ion contamination can be increased by a short distance, and there is no deterioration in device characteristics due to the conventional short channel effect, so high integration can be achieved by micro-processing. C-MO8
A high-performance LSI P-MO3FET can be constructed.
第7図、第8図及び第9図は本発明の効果測定用M I
S構成ダイオードの作製工程を示す断面図、第10図
は本発明の効果を示すグラフ図である。
1.11・・・シリコン基板、 2.’、12・・・
S 102WOa %、 3・・・ポリシリコン膜、
4,6・・・保護S
02
膜、
5・・・レジスト膜、
7・・・ソ
ース領域、
8・・・ドレイン領域、
9・・・パシベ
ーション膜、
10・・・金属電極。FIG. 7, FIG. 8, and FIG. 9 show MI for measuring the effect of the present invention.
FIG. 10 is a cross-sectional view showing the manufacturing process of the S-configuration diode, and is a graph showing the effects of the present invention. 1.11...Silicon substrate, 2. ', 12...
S102WOa%, 3...Polysilicon film,
4, 6... Protective S 02 film, 5... Resist film, 7... Source region, 8... Drain region, 9... Passivation film, 10... Metal electrode.
Claims (1)
型電界効果トランジスタの製造に於て、前記多結晶シリ
コンゲートに先ずn型不純物を少量添加し、続いてp型
不純物を添加することにより、前記多結晶シリコンゲー
トの大部分をP型化することを特徴とする半導体装置の
製造方法。1. P-channel MOS with polycrystalline silicon gate
In manufacturing a type field effect transistor, first a small amount of n-type impurity is added to the polycrystalline silicon gate, and then a p-type impurity is added to make most of the polycrystalline silicon gate P-type. A method for manufacturing a semiconductor device, characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP18828489A JPH0350835A (en) | 1989-07-19 | 1989-07-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP18828489A JPH0350835A (en) | 1989-07-19 | 1989-07-19 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
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JPH0350835A true JPH0350835A (en) | 1991-03-05 |
Family
ID=16220947
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP18828489A Pending JPH0350835A (en) | 1989-07-19 | 1989-07-19 | Manufacture of semiconductor device |
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JP (1) | JPH0350835A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1012874A (en) * | 1996-06-27 | 1998-01-16 | Nec Corp | Manufacture of field effect transistor |
-
1989
- 1989-07-19 JP JP18828489A patent/JPH0350835A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1012874A (en) * | 1996-06-27 | 1998-01-16 | Nec Corp | Manufacture of field effect transistor |
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