JPH0350300B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a memory access control device, and particularly to a memory access control device that accesses bank memories in multiple ways.

2. Description of the Related Art In electronic computers, in order to shorten memory read time, an interleaving mechanism is provided to access memory. That is, in the interleave mechanism, the storage area of the memory is divided into blocks, for example, even addresses and odd addresses, and each block is accessed simultaneously to read data, thereby shortening the read time. However, even if such an interleaving mechanism is provided, if multiple accesses are made to the same memory address (bank), the second data access will not be processed until the first access is completed. I end up having to wait. For this reason, even if an attempt is made to read data based on other address information, the processing will be hindered by the address information that has been made to wait.

Problems to be Solved by the Invention FIG. 6 is a diagram showing a conventional non-ring buffer. In order to solve the above-mentioned problems, it is conceivable to provide non-ring buffer memories 61 to 64 for each interleaved bank, as shown in FIG. When multiple accesses are made to the same bank, address information from the second access is stored in the buffer memory of the corresponding bank, making it possible to read data based on other address information. However, as shown in FIG. 6, if buffer memories 61 to 64 are provided for each bank, it is necessary to provide buffers with a number of stages greater than the average number of accesses for each bank, which is uneconomical.

Therefore, the main object of the present invention is to provide a memory access control device that includes a ring-shaped buffer, can reduce the number of buffer memory stages, and can perform multiple accesses to the memory.

Means for Solving the Problems A memory access control device according to the present invention includes:
It is constructed by connecting a buffer memory, a packet compression means, a packet merging means, an address comparison means, and a data distribution means in a ring shape. The buffer memory temporarily stores a plurality of packet data in which address information, information representing writing or reading, and write data are expressed over at least two words in a word-by-word order, and the packet compression means reads the data word-by-word from the buffer memory. The packet merging means has compressed the data into a packet consisting of at least two words, and the empty determination means has determined that the packet merging means has not received packet data from the outside, and the packet compression means has compressed the packet. at least 2 from the compressed buffer memory, depending on
Outputs word-structured packet data. The address comparison means compares the address information included in the given packet data with the address information included in the packet data selected immediately before, and determines whether they match. The packet diversion means temporarily stores the packet data including the address information in the buffer memory in response to the determination of address match, outputs the packet data including the address information in response to the determination of mismatch, and outputs the packet data including the address information. One of the multiple memories included in the bank memory is accessed based on the packet data.

Function The memory access control device according to the present invention has the following features:
When address information for specifying the same number address of the memory is output, while accessing the memory based on the first address information, the same number address information, information indicating writing or reading, and write data are included. Write packet data to buffer memory. The memory is accessed by outputting packet data containing address information specifying another address, and the packet data containing address information temporarily stored in the buffer memory is read out to access the same numbered address in the memory. Therefore, when accessing the same number address,
Until the first access is completed, access to other addresses is not hindered, and the number of stages can be reduced as a buffer memory.

Embodiment FIG. 1 is a schematic block diagram showing the overall structure of an embodiment of the present invention. First, the overall configuration of an embodiment of the present invention will be described with reference to FIG. The memory access control device according to this embodiment includes a ring buffer 1, a confluence detection section 2, an address detection section 3, a branch detection section 4, and a bank memory 5. The ring buffer 1, confluence detection section 2, address detection section 3, and branch flow detection section 4 are connected in a ring shape.

The ring buffer 1 uses, for example, a first-in-first-out memory, and has a function of inputting data waiting for memory access from the branch detection section 4 and outputting it to the confluence detection section 2.
The number of stages of this ring buffer 1 can be set arbitrarily.
The capacity can be determined depending on the scale of memory access at any given time. A confluence detection section 2 detects data input from the data transmission path and data input from the ring buffer 1, and if there is data input from the ring buffer 1, the packet data from the ring buffer 1 is input with priority. This is to prevent packet data from overflowing into the ring buffer 1.

The address detection section 3 detects the address information of the packet data output from the confluence detection section 2, and sets a flag to send the packet data to the ring buffer 1 when the same bank is accessed continuously. The shunt detection section 4 detects whether the packet data given from the address detection section 3 is written into the ring buffer 1 or given to the bank memory 5. Bank memory 5 includes a plurality of memories, and is accessed multiple times based on data from shunt detection section 4.

FIG. 2 is a block diagram of the merging detection section shown in FIG. 1. The configuration of the merging detection section 2 will be explained with reference to FIG. 2. The confluence detector 2 is composed of a packet compression section 21, a confluence section 22, an empty determination section 23, and an AND gate 24. Packet compression section 21
compresses the word-by-word data packets read asynchronously from the ring buffer 1 into consecutive two-word data packets. That is, in this embodiment, the data consists of two words, the first word of packet data includes address information and read/write designation information, and the second word of packet data includes write data. There is. Then, packet data is read out word by word asynchronously from the ring buffer 1. That is, packet data is not necessarily read out continuously from the ring buffer 1 at regular intervals, but packet data may be read out at certain intervals. In that case, before the leading data read from the ring buffer 1 and the following data reach the merging section 22 and are aligned, the packet data sent from the transmission path reaches the merging section 22, and the two packets are mixed together. There is a risk of getting hot. Therefore, the packet compression section 21 always compresses the packet data so that it has a two-word structure, and provides the two-word structure of the packet data to the merging section 22.

The empty determination unit 23 detects that the transmission path is empty, that is, that no data is being transmitted through the transmission path. When the vacancy determination unit 23 determines that the transmission unit is in the vacancy state, it applies an “H” signal to one input terminal of the AND gate 24. AND gate 2
The other input terminal of 4 is supplied with an "H" signal that is output when the packet compression section 21 compresses the packet. Therefore, when the packet compression unit 21 has compressed the packet data and the empty determination unit 23 determines that the transmission path is empty, the AND gate 24 transmits the “H” signal to the converging unit. Give to 22. The confluence section 22 is an AND gate 24
When an "H" signal is applied from the ring buffer 1, the two-word packet data read from the ring buffer 1 and compressed by the packet compression section 21 is output.

FIG. 3 is a block diagram of the address detection section shown in FIG. 1. The two-word n-bit packet data outputted from the confluence detection section shown in FIG. 2 is latched in a data latch 31, and if the packet data can be transferred, a flag 32 indicating this is set. Note that the timing at which the packet data is latched in the data latch 31 is based on the pulse signal C ₁ transmitted to the C element (Coincidence Element) 33. This pulse signal _C1 is given from the above-mentioned merging detection section 2 when the enable signal UK outputted from the C element 33 is given to the above-mentioned merging detection section 2. , pulse signal C ₁ and enable signal
Explanation for the UK is omitted.

The bank address latch 34 latches m-bit address information included in the n-bit data output immediately before the data output from the confluence detection section 2. This bank address latch 3
4, for example, a master-slave flip-flop. The n-bit data latched in the data latch 31 is given to the data latch 36, and the m-bit address information included in the data is sent to the bank address comparator 35.
given to. The bank address comparator 35 is supplied with the flag 32 and the address information contained in the immediately preceding data latched in the bank address latch 34.

Although the comparison judgment conditions of the address detection section 3 differ depending on the field of application in which this embodiment is used, one example will be briefly explained. When the flag 32 is reset, the bank address comparator 35
The address information given from the data latch 31 and the immediately previous address information latched in the bank address latch 34 are compared to determine whether or not they match. If it matches, flag 3
7, and if they do not match, the flag 37 is reset.

Similarly, if the flag 32 is set, the bank address comparator 35 resets the flag 37 and outputs it without performing any comparison, that is, even if it matches the previous address information.

The pulse signal C ₁ transmitted to the C element 33 is transmitted to the C element 38, and the pulse signal C ₁ is applied to the data latch 36 as a clock pulse.
The data latch 36 latches the output data of the data latch 31 based on the clock pulse and supplies it to the shunt detection section 4.

FIG. 4 is a block diagram of the shunt detection section shown in FIG. 1. The branch detection section 4 is a branch condition register 41
, EXOR gate 42 and mask bit register 4
3, AND gates 44 and 45, a branching section 46, and an empty determination section 47. Branch condition register 4
1 stores branch conditions in advance using several bits. This branch condition is a hardware-based condition that indicates whether or not the packet data output from the address detection section 3 should be branched to the ring buffer 1. The branch condition stored in the branch condition register 41 is applied to one input terminal of the EXOR gate 42, and the packet data from the address detection section 3 is applied to the other input terminal.

EXOR gate 42 determines whether several bits included in the packet data match the branch condition from branch condition register 41. EXOR
The output of gate 42 is applied to one input terminal of AND gate 44, and the mask bit from mask bit register 43 is applied to the other input terminal of AND gate 44. These mask bits are used to mask bits other than the bits indicating branch conditions in the packet data. AND gate 44 performs bit masking with the output of EXOR gate 42 and the mask bit from mask bit register 43.

The emptiness determination unit 27 determines whether data can be transmitted to the ring buffer 1, that is, whether it is in an empty state. Then, the sky determination section 47
When it determines that it is empty, it outputs an “H” signal.
It is applied to one input terminal of AND gate 45. The output of the AND gate 44 is applied to the other input terminal of the AND gate 45 . AND gate 45 is empty judgment section 4
“H” signal is given from AND gate 4
When a match signal is given from 4, a branch signal is given to branch section 46. When the branching unit 46 receives the branching signal from the AND gate 45, it writes the input packet data to the ring buffer 1, and
When the branch signal is not applied, the packet data is output to the bank memory 5.

FIG. 5 is a block diagram of the bank memory shown in FIG. 1.

Next, the bank memory 5 will be explained with reference to FIG. When a data packet is provided to the bank memory 5 from the branch detection section 4 shown in FIG. 4 described above without being branched to the ring buffer 1, the packet data is provided to the register 501. The register control unit 502 controls the register 501
If it is possible to write, a permission signal AK ₀ is output to the shunt detection section 4. This register control unit 502 includes
A pulse signal C ₀ is given from the shunt detection section 4 .
Note that in the above-mentioned shunt detection unit 4, for the sake of brevity, a description of the handshake transmission control of the pulse signal C ₀ and permission signal AK ₀ is omitted; however, the pulse signal C ₀ is The permission signal AK ₀ is transmitted through the shunt detection unit 4.
is given to the address detection section 3 via the shunt detection section 4.

When the register control unit 502 of the bank memory 5 receives the pulse signal C ₀ , it writes packet data into the register 501 . The packet data written in register 501 is given to branch control section 503. This branch control unit 503 branches packet data sequentially written to the register 501 asynchronously. In the bank memory 5 shown in FIG. 5, the branch control unit 3 is configured to be able to branch the packet data sequentially written into the register 501 into four parts, and furthermore, it branches each packet data according to the address information in the packet. Tsute Bank 5
31, 532, 533 or 534.

Each bank 531, 532, 533 and 534
A register 51 is provided on the input side corresponding to each of the
1, 512, 513 and 514, and register control units 521, 522, 523 and 524 are provided. Register control unit 521, 522, 52
3 and 524 are respectively corresponding banks 53
If it is possible to write data to 1, 532, 533, and 534, or if data can be read, a permission signal is sent to the shunt detection unit 4 via the branch control unit 503 and the register control unit 502. And register control units 521, 522, 5
23 and 524 store each packet data branched by the branch control unit 503 in the registers 511, 512, and 513 if data can be written or read in the corresponding bank.
and 514, respectively. Each register 51
Packet data written to banks 1, 512, 513 and 514 are provided to banks 531, 532, 533 and 534.

Each bank 531, 532, 533 and 534
registers 511, 512, 513 and 51
Data is written or read based on the address information and read/write designation information included in the packet data written in each of the packets. Registers 551, 552, and
553 and 554, register control unit 541,
542, 543 and 544 are provided. Register control units 541, 542, 543 and 54
4 writes memory data read from banks 531, 532, 533 and 534 into registers 551, 552, 553 and 554, respectively.

Each register 551, 552, 553 and 55
The memory data written in
given to. The merging control unit 504 merges the memory data in a predetermined order. The combined memory data is provided to register 506. A register control unit 505 is provided in association with the register 506. When the register control unit 505 is given a permission signal UK ₂ indicating that packet data can be transmitted to the output transmission line, it writes the packet data output from the merging control unit 504 to the register 506, and transmits the packet data to the output transmission line. to create.

Next, with reference to FIGS. 1 to 5, a specific operation of an embodiment of the present invention will be described.
In the initial state, the ring buffer 1 is cleared and the first packet data is given to the merging detection section 2 from the transmission path. In the merging detection section 2, the empty determination section 23 determines whether or not packet data is being transmitted from the transmission path. When the confluence detection unit 2 determines that packet data is being transmitted,
AND gate 24 is closed. Since the AND gate 24 is closed, the merging section 22 provides the address detection section 3 with the packet data transmitted from the transmission path. In the address detection section 3, a data latch 31 latches packet data.

In the initial state, the flag 32 is reset and no address information is latched in the bank address latch 34, so the bank address comparator 35 resets the flag 37.
Further, the packet data latched in the data latch 31 is latched in the data latch 36, and is provided to the shunt detection section 4. In the shunt detection section 4,
The EXOR gate 42 determines whether several bits included in the input packet data match the branch condition stored in the branch condition register 41. In this case, the flag 37 has been reset and the branch conditions do not match, so the EXOR gate 42 closes the AND gate 44. Since the AND gate 44 is closed, the AND gate 45 is also closed, and the branch section 46 does not branch the packet data given from the address detection section 3 to the ring buffer 1, but supplies it to the memory bank 5.

In the memory bank 5, a register 501 stores input packet data under the control of a register control section 502. The packet data stored in register 501 is branched by branch control section 503 and given to register 511, for example. The register 511 stores the packet data and provides it to the bank 531 under the control of the register control section 521. Bank 531 writes the second word of write data based on the address information and read/write designation information included in the first word of the given packet data.

If the reading/writing specification information for the first word is reading, 1
Based on the word address information, memory data is read from the corresponding address. The read memory data is written into the register 551 under the control of the register control section 541. The memory data written in the register 551 is given to the register 506 via the merging control unit 504, and the register control unit 5
05, it is written into the register 506 and output.

While accessing the bank 531 mentioned above,
When packet data for accessing the same bank 531 is provided from the transmission path to the merging detection section 2, the packet data is provided to the address detection section 3 in the same manner as described above. Packet data applied to the address detection section 3 is latched in a data latch 31. Bank address latch 3
Address information included in the first packet data is latched in 4. The bank address comparator 35 compares the address information included in the second packet data latched in the data latch 31 with the first address information latched in the bank address latch 34, and if it determines that they match, it sets a flag 37. Set.

Further, the packet data latched in the data latch 31 is latched in the data latch 36. Then, the packet data latched in the data latch 36 and the flag 37 are given to the confluence detection section 4. In the confluence detection section 4, the branching section 46 branches the packet data to the ring buffer 1 based on the fact that the flag 37 output from the address detection section 3 is set.

That is, when data for accessing the same bank is input, subsequent data is saved in ring buffer 1.

Next, when packet data is given to the confluence detection section 2 in order to access the bank 533, for example, the packet data is sent from the confluence detection section 2 via the address detection section 3 and the branch detection section 4 in the same manner as described above. and is applied to the bank memory 5. In other words, since the second packet data for accessing bank 531 is branched to ring buffer 1, the subsequent packet data input immediately accesses bank 533 without having to wait for the second packet data. I can do it.

By repeating the above-described operation, the packet data sent from the transmission path is sequentially applied from the confluence detection section 2 to the bank memory 5 via the address detection section 3 and the branch detection section 4. When packet data for accessing the same bank is input, it is branched to link buffer 1.

On the other hand, the packet data branched to the ring buffer 1 is sequentially shifted to the output side and given to the confluence detection section 2 again. At this time, packet data is stored and read out for each word in the ring buffer 1.

In the confluence detection section 2, the packet data read out for each word is compressed by the packet compression section 21 into packet data consisting of two words, and the compressed data is provided to the confluence section 22. Then, when the empty determination section 23 determines that no packet data is transmitted on the transmission path and the packet compression section 21 compresses the packet, the AND gate 24 is opened and the "H" signal is transmitted to the confluence section. 22. In response, the merging section 22 provides the packet data compressed by the packet compression section 21 to the address detection section 3.

When allowing packet data that has passed through ring buffer 1 to be accessed preferentially to bank memory 5,
In the address detection section 3, the packet data is latched in the data latch 31, and the packet data is latched in the data latch 31.
5, the flag 37 is reset regardless of whether the address information included in the packet data latched in the data latch 31 matches the previous address information latched in the bank address latch 34. And data latch 3
The packet data latched at 1 is latched by the data latch 36 and given to the shunt detection section 4.

In the shunt detection unit 4, the EXOR gate 42 determines that the flag bit included in the packet data has been reset and does not match the branch condition stored in the branch condition register 41.
AND gate 44 is closed. AND gate 44 performs bit masking based on the mask bits stored in mask bit register 43. Since the branch conditions do not match, the branch signal is not given from the AND gate 45 to the branch unit 46, so the packet data is transmitted to the transmission line and stored in the bank memory 5.
can be accessed.

In the above explanation, memory bank 5 is used only when the evacuated packet goes around ring buffer 1.
I did not allow access to the ring buffer 1.
In this embodiment, it is also possible to perform bank address comparison without giving priority to read packet data from the transmission line over packet data from the transmission path, that is, regardless of the state of the flag 32 input to the address detection section 3.

Effects of the Invention As described above, according to the present invention, the buffer memory, the data merging means, the address comparing means, and the data distributing means are connected in a link form, and packet data for accessing the same memory in the bank memory is provided. In some cases, the packet data is branched to the buffer memory, and the subsequently input packet data is given to the bank memory for access, so that packet data for accessing the same memory makes the access of the subsequent packet data wait. access time can be shortened. Furthermore, the packet data branched to the buffer memory can be input again to the data merging means, and can be applied to the bank memory via the address comparing means and data branching means to access a predetermined memory, so that the number of buffer memory stages can be reduced.

Furthermore, when packet data is temporarily stored in all areas of the buffer memory and is overflowing, if packet data is input from the outside, the packet data will not be input from the packet merging means to the address comparison means unless the same number address is specified. Therefore, the processing of the packet data is not made to wait forever.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing the overall structure of an embodiment of the present invention. FIG. 2 is a block diagram of the merging detection section shown in FIG. 1. Figure 3 is the first
FIG. 3 is a block diagram of the address detection section shown in the figure.
FIG. 4 is a block diagram of the shunt detection section shown in FIG. 1. FIG. 5 is a block diagram of the bank memory shown in FIG. 1. FIG. 6 is a diagram showing a conventional non-ring buffer. In the figure, 1 is a ring buffer, 2 is a confluence detection section, 3 is an address detection section, 4 is a branch detection section, and 5
is a bank memory, 21 is a packet compression section, 22 is a merging section, 23, 47 is an empty judgment section, 24, 44, 4
5 is an AND gate, 31 and 36 are data latches,
32 and 37 are flags, 34 is a bank address latch, 35 is a bank address comparator, 41 is a branch condition register, 43 is a mask bit register, 46
is a branch part, 501, 506, 511 to 51
4,551 to 554 are registers, 502,5
05,521 to 524,541 to 544
531 is a register control unit, 504 is a confluence control unit, and 531 is a register control unit;
to 534 indicate banks.

Claims (1)

[Scope of Claims] 1. A memory access control device for multiple accessing a memory, which includes a plurality of packet data in which address information, information representing writing or reading, and write data are expressed over at least two words. a buffer memory for sequentially temporarily storing word-by-word data; a packet compression means for compressing the data read word-by-word from the buffer memory into the at least two-word packet; and whether or not the packet data is provided from the outside. an empty determination means for determining whether or not the packet data is compressed; a packet merging means for outputting at least word-structured packet data from the buffer memory; and comparing address information included in the packet data merged by the packet merging means with address information included in the packet data merged immediately before. an address comparing means for determining a match based on the address comparison means; and when the address comparing means determines that the address information matches, packet data including the address information is temporarily stored in the buffer memory, and a mismatch is determined. a bank that includes a plurality of memories and that accesses any one of the plurality of memories based on the packet data output from the packet shunt means. A memory access control device comprising a memory. 2. The address comparing means includes a data latch that temporarily stores the packet data output from the packet merging means, and an address latch that temporarily stores address information included in packet data output immediately before the packet data output from the packet merging means. and address determining means for determining whether address information temporarily stored in the data latch matches address information temporarily stored in the address latch. . 3. The packet diversion means includes: a branching condition setting means for setting a branching condition for branching the packet data to the buffer memory; and whether the packet data matches the branching condition set by the branching condition setting means. A branching condition discriminating means for discriminating whether or not the branching conditions match, and a branching means for branching the packet data to the buffer memory in response to the branching condition discriminating means discriminating whether the branching conditions match. 2. The memory access control device according to claim 1. 4. The bank memory includes a plurality of memories, a branching means for distributing and accessing packet data given by the packet distribution means to any of the plurality of memories, and a branching means for distributing and accessing packet data provided by the packet distribution means to any of the plurality of memories; 2. The memory access control device according to claim 1, further comprising a merging means for merging and outputting data read out.