JPH0349700U - - Google Patents
Info
- Publication number
- JPH0349700U JPH0349700U JP10943189U JP10943189U JPH0349700U JP H0349700 U JPH0349700 U JP H0349700U JP 10943189 U JP10943189 U JP 10943189U JP 10943189 U JP10943189 U JP 10943189U JP H0349700 U JPH0349700 U JP H0349700U
- Authority
- JP
- Japan
- Prior art keywords
- constant current
- transistor pair
- differential transistor
- terminals
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Landscapes
- Electronic Switches (AREA)
Description
第１図は本考案に係るトラツク・ホールド回路
の一実施例を示す構成回路図、第２図は第１図回
路の要部を示す等価回路図、第３図は第１図のト
ラツク・ホールド回路の切換特性を示すタイムチ
ヤート、第４図は第１図回路の変形例を示す要部
等価回路図、第５図は従来のトラツク・ホールド
回路を示す構成回路図、第６図は第５図回路の要
部の等価回路図、第７図は第５図回路の切換特性
を示すタイムチヤートである。
Ｖｉｎ……入力信号、Ｄ１〜Ｄ４……ブリツジ
用ダイオード、ＣＨ……ホールドキヤパシタ、Ｑ
１，Ｑ２……差動トランジスタ対、Ｄ９，Ｄ１０
……スイツチ用ダイオード、Ｑ３……第１の定電
流回路用トランジスタ、Ｑ４……第２の定電流回
路用トランジスタ、Ｑ５……第３の定電流回路用
トランジスタ、Ｒ３……第１の定電流回路用抵抗
、Ｒ４……第２の定電流回路用抵抗、Ｒ５……第
３の定電流回路用抵抗、ＶＢＢ……定電流回路用
バイアス電圧。
Figure 1 is a configuration circuit diagram showing an embodiment of the track and hold circuit according to the present invention, Figure 2 is an equivalent circuit diagram showing the main parts of the circuit in Figure 1, and Figure 3 is the track and hold circuit of Figure 1. A time chart showing the switching characteristics of the circuit, Fig. 4 is an equivalent circuit diagram of the main part showing a modification of the circuit in Fig. 1, Fig. 5 is a configuration circuit diagram showing a conventional track and hold circuit, and Fig. 6 is a FIG. 7 is an equivalent circuit diagram of the main part of the circuit shown in FIG. 5, and FIG. 7 is a time chart showing the switching characteristics of the circuit shown in FIG. V in ...Input signal, D1 to D4 ...Bridge diode, CH...Hold capacitor, Q
1 , Q 2 ... Differential transistor pair, D 9 , D 10
... Diode for switch, Q 3 ... Transistor for first constant current circuit, Q 4 ... Transistor for second constant current circuit, Q 5 ... Transistor for third constant current circuit, R 3 ... Transistor for constant current circuit 1 resistance for constant current circuit, R 4 ... resistance for second constant current circuit, R 5 ... resistance for third constant current circuit, VBB ... bias voltage for constant current circuit.
Claims (1)
信号をホールドキヤパシタで追従・保持するよう
に構成したトラツク・ホールド回路において、ダ
イオードブリツジのアノード側とカソード側に関
連してコレクタ端子がそれぞれ接続し前記ダイオ
ードブリツジのスイツチ動作を制御する差動トラ
ンジスタ対と、この差動トランジスタ対のそれぞ
れのエミツタ端子にそれぞれのアノード端子が接
続しカソード端子同士が接続する２つのダイオー
ドと、この２つのダイオードのカソード端子に接
続する第１の定電流回路と、前記差動トランジス
タ対のそれぞれのエミツタ端子に接続する第２、
第３の定電流回路とを備え、第２、第３の定電流
回路により差動トランジスタ対に所定のバイアス
電流を流し差動トランジスタ対がリニア動作する
ように構成したことを特徴とするトラツク・ホー
ルド回路。 In a track/hold circuit configured to follow and hold an input signal with a hold capacitor by the switch operation of a diode bridge, collector terminals are connected to the anode side and cathode side of the diode bridge, respectively, and A differential transistor pair that controls the switch operation, two diodes whose anode terminals are connected to the emitter terminals of this differential transistor pair, and whose cathode terminals are connected to each other, and the cathode terminals of these two diodes are connected to each other. a first constant current circuit to be connected, and a second constant current circuit to be connected to each emitter terminal of the differential transistor pair;
a third constant current circuit, and is configured such that the second and third constant current circuits apply a predetermined bias current to the differential transistor pair so that the differential transistor pair operates linearly. hold circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10943189U JPH0349700U (en) | 1989-09-19 | 1989-09-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10943189U JPH0349700U (en) | 1989-09-19 | 1989-09-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0349700U true JPH0349700U (en) | 1991-05-15 |
Family
ID=31658028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10943189U Pending JPH0349700U (en) | 1989-09-19 | 1989-09-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0349700U (en) |
-
1989
- 1989-09-19 JP JP10943189U patent/JPH0349700U/ja active Pending
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