JPS5952735U

JPS5952735U - matrix circuit

Info

Publication number: JPS5952735U
Application number: JP14788882U
Authority: JP
Inventors: 篠田　匡暢
Original assignee: 日本電気アイシ−マイコンシステム株式会社
Priority date: 1982-09-29
Filing date: 1982-09-29
Publication date: 1984-04-06

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来のマトリックス回路の一例の回路図、第２
図は本考案の第１の実施例の回路図、第３図は本考案の
第２の実施例の回路図である。１．２・・・・・・入力端、３．４・・・・・・緩衝増
幅器、５・・・・・・電源、６・・・・・・出力端子、
７・・・・・・低電位端、８゜９・・・・・・ＮＰＮ　
ｔ−ランジスタ、１０．１１・・・・・・抵抗、１２・
・・・・・負荷抵抗、１３・・・・・・スイッチ、１４
゜１５・・・・・・抵抗、１６．１７・・・・・・緩衝
増幅器、１８゜１９・・・・・・ＮＰＮ　）ランジスタ
、２０〜２５・・・・・・抵抗、２６・・・・・・バイ
アス電源、２１．２８・・・・・・抵抗、２９〜３２・
・・・・・定電流源。Figure 1 is a circuit diagram of an example of a conventional matrix circuit, and Figure 2 is a circuit diagram of an example of a conventional matrix circuit.
The figure is a circuit diagram of a first embodiment of the present invention, and FIG. 3 is a circuit diagram of a second embodiment of the present invention. 1.2...Input terminal, 3.4...Buffer amplifier, 5...Power supply, 6...Output terminal,
7...Low potential end, 8゜9...NPN
t-transistor, 10.11... Resistor, 12.
...Load resistance, 13...Switch, 14
゜15...Resistor, 16.17...Buffer amplifier, 18゜19...NPN) transistor, 20-25...Resistor, 26... ...Bias power supply, 21.28...Resistor, 29-32.
... Constant current source.

Claims

[Scope of utility model registration request]

a buffer amplifier whose input end is connected to the high potential end of the bias power supply via a first resistor; and a buffer amplifier having the same circuit as the buffer amplifier and whose input end is connected to the high potential end of the bias power supply via a second resistor. a first transistor having a base connected to the output terminal of the buffer amplifier and an emitter connected to the low potential terminal of the bias power supply via a third resistor or a constant current source; a second transistor having a base connected to an output terminal, an emitter connected to a low potential terminal of the bias power supply via a fourth resistor or a constant current source, and a top/lid connected to another power supply; a fifth resistor connected between the emitters of the first and second transistors; and at least two switches each having a movable contact and at least two fixed contacts. A movable contact of one of the switches connects to the other power source through a load resistor, another movable contact connects to the other power source, and a first fixed contact of each switch connects to the other power source through a load resistor. a matrix comprising a group of switches all connected to the collectors of the first transistors of the first circuit block, and an output terminal led out from the connection point between the load resistor and the movable contact. circuit.