JPH0348327A - Serial access memory device - Google Patents

Abstract

PURPOSE:To simplify the constitution of the serial access memory device by providing the device with plural address conversion circuits for adding constant data to address data inputted from plural address counters based upon plural address conversion command signals inputted from an input means and for outputting the added data to plural address decoders. CONSTITUTION:Address conversion circuits 12, 13 are connected between reading and writing address counters 8, 9 and reading and writing address decoders 10, 11. The circuits 12, 13 add the constant data to address data inputted from the counters 8, 9 based upon address conversion command signals S1, S2 inputted from the input means 14 in an LCD controller 4 and output the added data to the decoders 10, 11. Since the serial access memory device is provided with the means 12, 13 for adding the constant data to the address data of the address counters 8, 9 which are to be outputted to field memories based upon external commands, the number of field memories can be reduced while holding the simple constitution of the LCD controller 4 or an address bus and the whole constitution can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a real access memory device used in a crystal display or plasma display of a personal computer or the like.

<Prior art> In recent years, personal computers have been equipped with a liquid crystal display (hereinafter abbreviated as LC1) in addition to the CRi" display.
Display cameras using the camera are now available. L C D
Display by CRT is an interlaced method in which even and odd scanning lines are alternately scanned (interlaced scanning), and y4 is a non-interlaced method in which scanning lines are sequentially scanned, so it is difficult to display on a computer. Is it necessary to rearrange the generated interlaced image data in memory?

A conventional personal computer equipped with such an LCD is shown in FIG. 4. This personal computer uses interlaced 8-bit image data generated by the computer itself! ), CI
In addition to directly outputting it to IT2 for display, it also outputs the storage address signal A (
1 4 bits) and fill in the gap! Via the LCD controller 2I which alternately generates the storage address signal 8 for the image data of the odd lines of the field! This is written into the ILAM 22 as frame image data D, read out sequentially in a non-interlaced manner, and displayed on the LCI 3. However, in this personal computer, the LCD controller [l-ra 2I has 11AM2 2
Yoshigome for, read address! This requires a fairly large-scale address generation circuit and a 14-bit address bus, making the configuration complicated.
A device using a serial access memory as shown in FIG. 5 has been proposed.

This personal computer has four real access field memories 23a instead of the above 11AM22.
, 2 3b. 2 4a and 2 4b are provided, and among the 1 frames of image data output from the LCD controller 25, the data Di of even and odd lines in the upper half of the screen is stored in the memory 23, respectively, based on the control signal C.
The data Di of the even-numbered lines and the odd-numbered lines in the lower half of the screen are written in the memories 24a and 24b, respectively.
Similarly, when reading data, even numbers . Odd line data D. are read out alternately and simultaneously, and the screen of the LCD 3 is divided into upper and lower halves and simultaneously scanned sequentially, thereby reducing the scanning time by half and preventing flickering of the displayed image. In other words, the upper and lower halves of the image data of even fields are stored in the memory 23 respectively.
a, 23b, and the upper half of the screen of the image data around 11 of the odd field. The lower halves are memories 24a. 24b. With this configuration, 1. The address generation circuit of the CD controller 25 can be simplified and the number of bits of the address bus can be reduced.

<Problems to be Solved by the Invention> However, while the above-mentioned conventional personal computers have the above-mentioned advantages, they require separate field memories for even and odd fields, and each field memory is located in the upper half of the screen. This has the disadvantage that it has to be divided into a lower half and a lower half, and as many as four serial access field memories 23a, 23b, 24a, and 24b are required.

Therefore, it is an object of the present invention to add constant data to the address data of the address counter output to the field memory based on an external command. By providing four stages, we provide a serial access memory device that can simplify the configuration by reducing the number of field memories while maintaining a simple configuration of the LCD controller and address bus.゜It's about that.

Means for Solving the Problems> In order to achieve the above object, the serial access memory device of the present invention provides a serial access memory device that uses a clock signal 47) t! The address conversion command is used to write data via a write port and read data via a read port to an address in the memory array indicated by an address signal that is counted up by an address counter and decoded by an address decoder. An input means for inputting a signal is provided between the address counter and the address decoder, and constant data is added to the address data input from the address counter based on an address conversion command signal input from the input means. The present invention is characterized in that it includes an address conversion circuit that outputs the address to the second address decoder.

Effect> Now suppose that interlaced image data of interlaced scanning is input to the write port of the memory array. Then, the input means outputs an address conversion command signal only when the input image data is odd field data. If the address conversion command signal is not input, the address conversion circuit outputs the address data counted up by the address counter to the address decoder as is, so the even field image data is arranged in the memory array according to the address decoded by the decoder. are written sequentially starting from the first address. On the other hand, if an address conversion command signal is input, the address conversion circuit adds constant data corresponding to, for example, 1/2 of the capacity of the memory array to the address data counted up by the address counter and outputs it to the address decoder. , odd-numbered fields of image data are sequentially written from the center address of the memory array. Conversely, when reading image data written to the memory array via the read port, the input means is 1.
An address conversion command signal is output aside from horizontal scanning, and the address conversion circuit (the address counter counts up) and adds the above constant data to the address data only when the address conversion command signal is received, and the address decoder outputs the address conversion command signal. Since the image data of even and odd fields is read out alternately one line at a time from the start address and tp center address of the memory array, non-interlaced display is performed on L, CD, etc. using this image data. .

Example Hereinafter, the present invention will be explained in detail by means of illustrated embodiments.

FIG. 1 is a block diagram of a personal computer including an embodiment of the serial access memory device of the present invention. This personal computer has the same computer body I as described in FIG. It is equipped with Cl'r2 and LCD3, and is also capable of writing interlaced image data generated by the computer main body l. An LCD controller 4 includes an input means (to be described later) for controlling reading and inputting an address conversion command signal, and a first controller 4 which stores image data of the upper and lower halves of the screen of the LCD 3, respectively. Second memories 5f, 5g and an address counter (not shown). It comprises a serial access memory device R6 including an address decoder and an address conversion circuit to be described later.

As shown in FIG. 2, the serial access memory device d6 includes a timing controller 7 that controls each part during a read or write operation based on various signals from the LCD controller 4, and a timing controller 7 that controls each section during a read or write operation. The read/write address counters 8 and 9 increment the address, and the address data from both address counters are decoded and read from the memory array 5.
Read that specifies the write address. The write address decoders 20 and IJ are provided between both address counters and both address decoders, and address counters 8 and 9 are provided based on address conversion command signals S,, S, from input means l4 in the LCD controller 4. The address decoder 10 adds constant data to the address data input from the address decoder 10,
II is provided with address conversion circuits 12 and 13 having outputs of 4.

The timing controller 7 receives various signals input from the LCI controller 4 (serial read clock SRCK for read operation, reset read RS' for initialization of read address).
I'R, Read operation enable RE, Serial write clock SWCK during write operation corresponding to these. Reset write IIS1''W, write enable WE.

The memory device 6 also stores interlaced image data DiO to Din input from the LCD controller 4.
a buffer 15 for receiving the image data, a data register 16 for temporarily holding the image data from this buffer and outputting it for writing to the memory array 5, and a data register 16 for temporarily holding the non-interlaced image data read from the memory array 5. Shift data register 17 and both image data D from this data register. It is provided with a buffer l8 for sending data from 0 to Don to the LCD controller 4.

The first and second memories 5', 5s shown as being divided in FIG. 1 are actually made up of a single memory array 5 shown in FIG. The second half area b is allocated to the image data of the even field, and the second half area b is allocated to the image data of the odd field, and the first half 5f' of the first half area a is allocated to the image data of the odd field.
a and the first half 5fb of the second half area b are even. Corresponding to the first memory 5r storing image data of odd fields, the second half 5sa of the first half area a and the second half ``14'' after the second half area b
5sb is even on the bottom half of the screen. It corresponds to the second memory 5s that stores image data of odd fields.

The input means 14, which is a logic element in the LCD controller 4, is used when the image data to be written is of an odd field or if the image data to be read. In order to output an address conversion command signal S, which becomes 'H' when the line of image data is an odd line and becomes 'L' otherwise (even field, even line), non-interlaced image data is required. LCI) 3
An address conversion command signal S, which becomes "I-1" when displayed by 4, is output.

On the other hand, when the address conversion command signal is S,1 "1■" and S,1 "1■", the address conversion circuit 13 converts the capacity of the memory array 5 into the address data counted up by the write address counter 9. The address of the address corresponding to 172 (center address) is added and this is output to the address decoder 11.

Further, the address conversion circuit l2 that operates when reading image data outputs an address conversion command signal S1 of 82="" because it is inverted by 4 degrees every horizontal scan, sl=""
The address decoder 10 directly receives a series of address data input from the read address counter 8 when the read address counter 8 is low.
It is output to S1-“I-■” and is temporarily held.
”, a signal S3 is issued to the read address counter 8 to prohibit counting, and then each of the center addresses is added to the series of address data held, and this is output to the address decoder 10, and the SI returns to “ When the count reaches "L", the count prohibition signal S is canceled and the operation returns to the above-mentioned first operation, which is repeated.

Regarding the operation of the serial access memory device 6 having the above configuration, please refer to the timing chart in FIG. 3. {1 I will explain next.

The input means 14 of the serial access memory device 6 receives "L" depending on whether the image data is interlaced, an even field, or an odd field. 1I1 This level changes 3rd
When an address conversion command signal S1 as shown in FIG.
, is given.

First, write starts with serial write clock SWCK (
(See Figure 3(a))
This is done when S T W goes to "H" level as shown in FIG.
3, outputs a signal for initialization. Next, if the address conversion command signal SI is at "L" level corresponding to an even field, the address conversion circuit 13 outputs the increment shift address data of the write address counter 9 as it is to the write address recorder 11, and outputs the increment shift address data of the write address counter 9 as it is to the odd field. If the corresponding level is 11, address data obtained by adding n/2 (center address) to the address data is output to the atlas recorder 11. At this time, the image data DiO to Din are as shown in FIG. 3(a). ) is input to the buffer 15 in synchronization with the serial line 1 clock SWCK, sent to the data register 16, temporarily held, and sequentially written to the address of the memory array 5 specified by the address recorder I1.

In this case, the read enable signal REi is at level 11 (see Figure 3(c)), and the image data of the even field that is input first is for the first line, as shown in Figure 3(d). Data is at address 0 to ([1), followed by k
The data for the summer field up to the line is 1~(a+k-
The image data of the odd field that is continuously written to address 1) and input next is n/2 to (n/2
10 mk - 1) addresses successively. Therefore, even field image data is sequentially and consecutively written from address 0 to the first half area a of the memory array 5, and odd field image data is sequentially and continuously written from address n/2 to the second half area b. .

On the other hand, serial read clock SRGK (
Set read signal 1' {
STR and read enable signal RE are shown in Figure 3(g).
, (h), the read address counter is initialized to either 8 or 0. Next, the address conversion circuit 12 receives a reset read signal RS.
The address data of the read address counter 8 is transferred to the address decoder 1 for reading until TR reaches the 1■'' level and the read enable signal RE reaches the “L” level.
Output to 0 and hold it. Then, from the addresses O to (i-1) of the memory array 5 indicated by the address decoder 10 that decoded this address data, the data as shown in FIG. As shown in (i), the first line of image data of the even field is read out.

Next, when the reset read signal R S i'R reaches the "11" level and the read enable signal rtE reaches the "I7" level, the address conversion circuit 12 converts n/2 ( Add the central address) and use this as an address decoder! Along with the output shift to 0, a count prohibition signal S3 is output to the read address counter to stop incrementing the address data. Then, n/2 is added to the memory array 5 indicated by the address decoder 10 that decoded the address data.
From addresses n/2 to (n/2 + mk - 1) of
Image data for a line is read out.

By repeating the above operations, even and odd fields are read out alternately one horizontal line at a time, resulting in image data D for one frame. 0~■). n is stored in the buffer yl8 via the data register 17, and outputted from there to the LCD 3 via the SLCD controller 4 (ijjl in FIG. 1) for non-interlaced display.

In this way, in the above embodiment, the computer main body can be operated by the serial access memory device 6 having a simple configuration including a single memory array 5 and address conversion circuits 12 and 13.
Since the interlaced image data from the computer is captured and non-interlaced image data is generated, the configuration is greatly simplified compared to the conventional example using RJAM, which requires a complicated address generation circuit. Moreover, the number of memory ICs can be reduced by unifying the serial access memory.

Note that it goes without saying that the present invention is not limited to the illustrated embodiment.

<Effects of the Invention> As is clear from the above description, the serial access memory device of the present invention has write board-1 and port-1: between the address counter that counts up the address of the memory array having the board and the address decoder. , is provided with an address conversion concave path that adds constant data to the address data input from the address counter and outputs it to the address decoder based on the address conversion command signal input from the input means. =Address generation circuit 1 is required 4
The structure can be greatly simplified compared to the conventional example using a RAM, and the number of memory ICs required for one system can be reduced by unifying the memory array.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a personal computer equipped with an embodiment of the present invention, FIG. 2 is a detailed block diagram of the serial access memory device of FIG. 1, FIG. 3 is a diagram showing the operation timing of the device, and FIG. Figure 4. FIG. 5 is a block diagram of a conventional serial access memory device. 1... Computer body, 3... LCI), 4
...LC I) controller, 5... memory array, 6... serial access memory device, 8... read address counter, - write address counter, 0.11... address decoder, 2, I3...address conversion circuit, 4...input means, . S1: Address conversion command signal.

Claims (1)

[Claims] (1) Write data via the write port to the memory array address indicated by the address signal counted up by the address counter and decoded by the address decoder in accordance with the clock signal, and write data via the read port. In a serial access memory device to be read, an input means for inputting an address conversion command signal is provided between the address counter and the address decoder, and the address conversion command signal is input from the address counter based on the address conversion command signal inputted from the input means. A serial access memory device comprising an address conversion circuit that adds constant data to input address data and outputs the result to the address decoder.