JPH0347778B2 - - Google Patents

Info

Publication number
JPH0347778B2
JPH0347778B2 JP58037501A JP3750183A JPH0347778B2 JP H0347778 B2 JPH0347778 B2 JP H0347778B2 JP 58037501 A JP58037501 A JP 58037501A JP 3750183 A JP3750183 A JP 3750183A JP H0347778 B2 JPH0347778 B2 JP H0347778B2
Authority
JP
Japan
Prior art keywords
gaasfet
gate
dfet
circuit
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58037501A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59163858A (ja
Inventor
Yasuo Igawa
Akimichi Hojo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP58037501A priority Critical patent/JPS59163858A/ja
Publication of JPS59163858A publication Critical patent/JPS59163858A/ja
Publication of JPH0347778B2 publication Critical patent/JPH0347778B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0952—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using Schottky type FET MESFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Logic Circuits (AREA)
JP58037501A 1983-03-09 1983-03-09 ＧａＡｓ論理集積回路 Granted JPS59163858A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58037501A JPS59163858A (ja) 1983-03-09 1983-03-09 ＧａＡｓ論理集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58037501A JPS59163858A (ja) 1983-03-09 1983-03-09 ＧａＡｓ論理集積回路

Publications (2)

Publication Number Publication Date
JPS59163858A JPS59163858A (ja) 1984-09-14
JPH0347778B2 true JPH0347778B2 (enrdf_load_stackoverflow) 1991-07-22

Family

ID=12499269

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58037501A Granted JPS59163858A (ja) 1983-03-09 1983-03-09 ＧａＡｓ論理集積回路

Country Status (1)

Country Link
JP (1) JPS59163858A (enrdf_load_stackoverflow)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS546760A (en) * 1977-06-17 1979-01-19 Fujitsu Ltd Logic circuit
FR2449369A1 (fr) * 1979-02-13 1980-09-12 Thomson Csf Circuit logique comportant une resistance saturable

Also Published As

Publication number Publication date
JPS59163858A (ja) 1984-09-14

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