JPH0346771B2 - - Google Patents

Info

Publication number
JPH0346771B2
JPH0346771B2 JP4545081A JP4545081A JPH0346771B2 JP H0346771 B2 JPH0346771 B2 JP H0346771B2 JP 4545081 A JP4545081 A JP 4545081A JP 4545081 A JP4545081 A JP 4545081A JP H0346771 B2 JPH0346771 B2 JP H0346771B2
Authority
JP
Japan
Prior art keywords
temperature
bridge
capacitor
resistor
full bridge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP4545081A
Other languages
Japanese (ja)
Other versions
JPS57160037A (en
Inventor
Shunji Shiromizu
Ryuzo Noda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP4545081A priority Critical patent/JPS57160037A/en
Publication of JPS57160037A publication Critical patent/JPS57160037A/en
Publication of JPH0346771B2 publication Critical patent/JPH0346771B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01LMEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L9/00Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
    • G01L9/02Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means by making use of variations in ohmic resistance, e.g. of potentiometers, electric circuits therefor, e.g. bridges, amplifiers or signal conditioning
    • G01L9/04Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means by making use of variations in ohmic resistance, e.g. of potentiometers, electric circuits therefor, e.g. bridges, amplifiers or signal conditioning of resistance-strain gauges
    • G01L9/045Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means by making use of variations in ohmic resistance, e.g. of potentiometers, electric circuits therefor, e.g. bridges, amplifiers or signal conditioning of resistance-strain gauges with electric temperature compensating means

Description

【発明の詳細な説明】 この発明は圧力変換器に係り、特に素子の温度
補償法とその周辺回路との結合法を考慮した圧力
変換器に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pressure transducer, and more particularly to a pressure transducer that takes into consideration a method of compensating the temperature of an element and a method of coupling it with a peripheral circuit.

半導体の拡散抵抗層をゲージ抵抗とし、このゲ
ージ抵抗を用いてブリツジ回路を構成した圧力検
出装置では温度変動に対する補償が重要な課題で
ある。例えば第1図にに示すように圧力に感応し
て互いに異符号の抵抗変化を示すゲージ抵抗R1
R2とR3,R4とを用いて構成された従来のフルブ
リツジ回路では、ゲージ抵抗R1,R2に対してそ
れぞれ直列に補償抵抗rs1,rs2を挿入し、且つ並
列に補償抵抗rP1,rP2をそれぞれ接続してブリツ
ジの零点補償を行つている。そしてこれらの補償
抵抗rs1,rs2,rP1,rP2の各抵抗値を適当に設定
することによつて所望温度範囲内においてゲージ
抵抗R1とR2の見掛上の温度係数をゲージ抵抗R3
とR4の温度係数と同じくすることができ、これ
によつて温度に対する零点補償を行わんとしてい
る。
In a pressure detection device in which a semiconductor diffused resistance layer is used as a gauge resistor and a bridge circuit is constructed using this gauge resistor, compensation for temperature fluctuations is an important issue. For example, as shown in Fig. 1, gauge resistance R 1 exhibiting resistance changes of opposite signs in response to pressure,
In a conventional full bridge circuit configured using R 2 and R 3 and R 4 , compensation resistors rs 1 and rs 2 are inserted in series with gauge resistors R 1 and R 2 , respectively, and compensation resistors are inserted in parallel. Bridge zero point compensation is performed by connecting rP 1 and rP 2 respectively. By appropriately setting the resistance values of these compensation resistors rs 1 , rs 2 , rP 1 , and rP 2 , the apparent temperature coefficients of the gauge resistances R 1 and R 2 can be determined within the desired temperature range. Resistance R 3
can be made the same as the temperature coefficient of R4 , and we are trying to perform zero point compensation for temperature.

然乍ら上記従来の零点温度補償には次のような
大きな問題があつた。即ち、上記零点温度補償だ
けではゲージ抵抗の圧力感度の補償を行い得ず、
例えば第2図に示すようにブリツジ駆動電圧VB
を可変して圧力感度補償を行う必要が生じた。こ
の圧力感度補償はサーミスタ等の感温抵抗素子
RTを介して基準電圧VEを温度に応動した電圧VB
としてブリツジに印加したり、あるいは増幅器
Ampの利得と感温抵抗素子RTによつて可変設定
してブリツジ駆動電圧VBを可変せんとするもの
であり、これによりゲージ抵抗R1〜R4の圧力感
度温度特性に合致した温度補償を行うものであ
る。ところが、この温度補償を行つた場合、駆動
電圧VBが温度によつて変化する為に圧力感度の
補償と零点の補償とが同時に変動し、その結果実
際上の調整が非常に困難で最適調整が殆んど不可
能であつた。また第2の問題点として、ゲージ抵
抗と並列に固定抵抗が接続されるので、ブリツジ
出力の直線性が低下し、高感度な検出ができなく
なる問題があつた。
However, the above conventional zero point temperature compensation has the following major problems. In other words, the pressure sensitivity of the gauge resistance cannot be compensated for only by the above-mentioned zero point temperature compensation.
For example, as shown in Figure 2, the bridge drive voltage V B
It became necessary to compensate for pressure sensitivity by varying the This pressure sensitivity compensation is performed using a temperature-sensitive resistance element such as a thermistor.
A temperature-dependent voltage V B of the reference voltage V E via RT
as a bridge or as an amplifier.
The purpose is to vary the bridge drive voltage VB by setting it variably using the gain of the amplifier and the temperature-sensitive resistor RT, thereby providing temperature compensation that matches the pressure sensitivity temperature characteristics of the gauge resistors R1 to R4 . It is something to do. However, when this temperature compensation is performed, since the drive voltage V B changes depending on the temperature, the pressure sensitivity compensation and the zero point compensation change at the same time, and as a result, it is very difficult to make an actual adjustment, and it is difficult to make an optimal adjustment. was almost impossible. A second problem is that since a fixed resistor is connected in parallel with the gauge resistor, the linearity of the bridge output decreases, making highly sensitive detection impossible.

そこで本発明者らは零点温度補償の新規なる方
法をハーフブリツジ回範に適用する場合につき提
供した。(特願昭54−126552)この補償方法は次
のような原理からなる。
Therefore, the present inventors have provided a new method for zero-point temperature compensation when applied to the half-bridge circuit. (Japanese Patent Application No. 54-126552) This compensation method is based on the following principle.

ブリツジに組まれるおのおのの歪抵抗の値と、
温度係数が全く等しければ、温度による変化は互
いに相殺されるはずである。しかし、実際にはp
形拡散層の温度係数は常温近傍でも3000〜
3500ppm/℃と非常に大きく、しかも温度係数自
体が温度に関する高次項をもつて変化する。
The value of each strain resistance assembled in the bridge,
If the temperature coefficients were exactly equal, changes due to temperature should cancel each other out. However, in reality p
The temperature coefficient of the shaped diffusion layer is 3000~ even at room temperature.
It is extremely large at 3500 ppm/°C, and the temperature coefficient itself changes with higher-order terms related to temperature.

半導体拡散抵抗の温度に対する変化は2次曲線
的であるため、零点の温度に対する変動は複雑な
曲線状のパターンを呈する。
Since the change in semiconductor diffused resistance with respect to temperature is quadratic, the change in zero point with respect to temperature exhibits a complicated curved pattern.

第3図に示すように、ブリツジ回路の歪抵抗間
に温度係数を持たない固定抵抗を挿入する。ハー
フブリツジのダミー抵抗側の1/2点から見たH点
とL点の電位(オフセツト電圧△VH,△VL)を
例えば低温の−20℃から80℃の高温までたどる
と、第4図に模式的に示すように、△VHと△VL
の中間のある状態(△VX)で、温度変動の曲率
が反転する状態が存在する。第2図で示したよう
に、圧力感度の温度変動をブリツジ印加電圧を動
かして補償する方法では、温度(T)とブリツジ
駆動電圧(VBT)とが比例関係のもとに対応して
いる。温度のかわりにブリツジ駆動電圧をもとに
して、第3図のブリツジの各点の電位変化を示し
たのが第5図である。
As shown in FIG. 3, a fixed resistor having no temperature coefficient is inserted between the strain resistors of the bridge circuit. If we trace the potentials (offset voltages △V H , △V L ) at points H and L (offset voltages △V H , △V L ) seen from the 1/2 point on the dummy resistor side of the half bridge from a low temperature of -20°C to a high temperature of 80°C, we can see Figure 4. As schematically shown in , △V H and △V L
There is a state in which the curvature of temperature fluctuation is reversed in a certain state ( ΔV As shown in Figure 2, in the method of compensating temperature fluctuations in pressure sensitivity by moving the bridge applied voltage, the temperature (T) and the bridge drive voltage (V BT ) correspond in a proportional relationship. . FIG. 5 shows potential changes at each point of the bridge in FIG. 3 based on bridge drive voltage instead of temperature.

ブリツジのダミー側の中点電位は1/2VBTの直
線となる。いま歪抵抗間にある固定抵抗の中点を
Xとすると、△VHと△VL曲線の間に低温、中温、
高温の3点を通る直線(破線△VX)が存在する
はずである。ダミー側の中点の勾配は1/2で変化
するので、もしYなる点を仮定すると、△VX
破線とYVBT(2点破線)とを平行させるX,Yの
値が存在するはずである。このときのX点とY点
の電位差δVはVBTの変化(温度変化)によらず一
定となる。
The midpoint potential on the dummy side of the bridge is a straight line of 1/2V BT . If the midpoint of the fixed resistance between the strain resistances is X, then between the △V H and △V L curves there are
There should be a straight line (broken line △V x ) passing through the three high temperature points. The slope of the midpoint on the dummy side changes by 1/2, so if we assume a point Y, there must be values of X and Y that make the broken line of △V X parallel to YV BT (two-point broken line). It is. At this time, the potential difference δV between point X and point Y remains constant regardless of changes in V BT (temperature changes).

この関係はH点、L点の電位をVBTに関する2
次式で近似することによつて説明できる。いま低
温、中温、高温のブリツジ駆動電圧をVBT(L),
VBT(C),VBT(H)、ダミー側1/2点とH,L各点
間の電位差をそれぞれ△VH(L)、△VH(C)、△
VH(H)、△VL(L)、△VL(C)、△VL(H)とす
る。歪抵抗側に挿入する抵抗の任意点、ダミー低
抗側の任意点とを比でとり、それぞれX,Yとす
る。アース点から見たH,L点の電位△VH
(VBT)、△VL(VBT)は、 △VH(VBT)−1/2VBT =AV2 BT+(B−1/2)VBT+C =△VH(L)、△VH(C)、△VH(H)
…(1) △VL(VBT)−1/2VBT =aV2 BT+(b−1/2)VB+C =△VL(L)、△VL(C)、△VL(H)
…(2) で表わされる。ここでA,B,C,a,b,cは
VBTに関する2次式の係数である。
This relationship shows that the potentials at points H and L are 2 with respect to V BT .
This can be explained by approximating with the following equation. Now, the bridge drive voltages at low temperature, medium temperature, and high temperature are V BT (L),
V BT (C), V BT (H), the potential difference between the dummy side 1/2 point and each point H and L, respectively, are △V H (L), △V H (C), △
Let V H (H), △V L (L), △V L (C), and △V L (H). An arbitrary point on the resistor inserted on the strain resistance side and an arbitrary point on the dummy low resistance side are taken as a ratio, and are designated as X and Y, respectively. Potential at points H and L seen from the ground point △V H
(V BT ), △V L (V BT ) are, △V H (V BT ) - 1/2V BT = AV 2 BT + (B - 1/2) V BT +C = △V H (L), △ V H (C), △V H (H)
...(1) △V L (V BT ) - 1/2V BT = aV 2 BT + (b - 1/2) V B +C = △V L (L), △V L (C), △V L ( H)
...(2) Here A, B, C, a, b, c are
V is a coefficient of a quadratic equation regarding BT .

△VHと△VLの差をδVとすると(1)−(2)から、 δV(VBT)=〔(A−a)X+a〕(VBT2〔(B−
b)X+(b−Y)〕 VBT+(C−c)X+C …(3) となる。δV(VBT)がVBTによらず一定になるため
には、VBTに関する2次、1次の項が零になる必
要がある。これを満足する条件は、 X=−a/(A−a),Y=(Ab−aB)/(A−a)
、 V=(Ac−Ca)/(A−a) …(4) となる。この条件を満足させることによつてオフ
セツト電圧δVがVBTによらず一定となり、外部温
度に依存しない補償条件が求まる。
If the difference between △V H and △V L is δV, then from (1)-(2), δV (V BT ) = [(A-a)X+a] (V BT ) 2 [(B-
b)X+(b-Y)] VBT +(C-c)X +C ...(3). In order for δV(V BT ) to be constant regardless of V BT , the second-order and first-order terms regarding V BT need to become zero. The conditions that satisfy this are: X=-a/(A-a), Y=(Ab-aB)/(A-a)
, V=(Ac-Ca)/(A-a)...(4). By satisfying this condition, the offset voltage ΔV becomes constant regardless of VBT , and a compensation condition that does not depend on the external temperature can be found.

以上詳述したような方法で、極めて高精度な零
点温度補償が可能である。しかし、従来の手法の
最大の欠点は、温度補償されるブリツジがハーフ
ブリツジに限られることであつた。言うまでもな
く、ハーフブリツジはフルブリツジに比べて、出
力が半分であり、増巾回路の側から見ると、信号
のSN比の点でも損である。また、半導体の同一
基板に拡散した歪ゲージをブリツジに組むため、
基板と個々の歪ゲージに対して異つた逆バイアス
電圧が加わる。同一基板に拡散された歪ゲージで
も逆バイアス電圧が異ると、抵抗の温度係数が異
つてしまうため、逆バイアス電圧に依存した零点
ドリフトを生じてしまう。これに比べて、ハーフ
ブリツジを相対させたフルブリツジ方式では、出
力が倍になるだけでなく、上述の零点温度ドリフ
トの逆バイアス電圧依存性が相殺される利点があ
る。
With the method described in detail above, extremely highly accurate zero point temperature compensation is possible. However, the biggest drawback of the conventional method is that the temperature compensated bridge is limited to a half bridge. Needless to say, a half bridge has half the output as a full bridge, and from the perspective of the amplification circuit, it is also a loss in terms of signal-to-noise ratio. In addition, in order to assemble strain gauges diffused on the same semiconductor substrate into a bridge,
Different reverse bias voltages are applied to the substrate and the individual strain gauges. Even if strain gauges are diffused in the same substrate, if the reverse bias voltage is different, the temperature coefficient of resistance will be different, resulting in zero point drift depending on the reverse bias voltage. In comparison, the full bridge method in which half bridges are placed opposite each other not only doubles the output, but also has the advantage that the above-mentioned dependence of the zero point temperature drift on the reverse bias voltage is canceled out.

本発明の目的はこのような欠点を完全に解決す
る新しい、零点温度ドリフト補償法を用いた変換
器を提供することにある。
The object of the present invention is to provide a new converter using a zero-point temperature drift compensation method that completely overcomes these drawbacks.

まず第6図から説明する。第6図は第3図で説
明したx,yの条件をフルブリツジに対して求め
る場合の回路構成である。左側の歪ゲージに対す
る条件をx,yとし、右側の歪ゲージに対する条
件をx′,y′とする。ダミー抵抗はx,x′を決める
ために必要なだけであり、最終的には不要にな
る。今第3図の回路において求めたx,y,x′,
y′に対応する各点の電位(アースから見た)を△
Vx、△V′x、ダミーから見て一定電位になる条件
での電位をδV,δV′とすると、第7図のようにな
る。これからわかるようにフルブリツジの出力、
つまりx,x′間の出力は△Vx−△V′xとなり、
VBTと比例関係にある。これをさらにわかり易く
書きなおしたのが第8図である。△Vx−△V′x
ブリツジの印加電圧に比例する成分ZVBTと一定
電位δVxx′の成分から成り立つている。このよう
にして生じた2つの成分は以上に述べるような回
路構成によつて除去することができる。
First, explanation will be given starting from FIG. FIG. 6 shows a circuit configuration when determining the x and y conditions explained in FIG. 3 for a full bridge. Let the conditions for the left strain gauge be x, y, and the conditions for the right strain gauge be x', y'. The dummy resistor is only needed to determine x and x', and will eventually become unnecessary. Now, x, y, x′, found in the circuit of Figure 3,
The potential (as seen from ground) at each point corresponding to y′ is △
If V x , △V′ x , and the potentials under the condition that the potentials are constant when viewed from the dummy are δV and δV′, the result will be as shown in FIG. As you can see, the output of Full Bridge,
In other words, the output between x and x′ is △V x −△V′ x ,
It is proportional to V BT . Figure 8 is a redrawn version of this to make it easier to understand. △V x −△V′ x consists of a component ZV BT proportional to the voltage applied to the bridge and a constant potential δV xx ′ component. The two components thus generated can be removed by the circuit configuration described above.

第9図において、圧力に応じて抵抗の増減を示
すゲージ抵抗Rp,R′p,Ro,R′oがフルブリツジ
81に構成され、温度に対応して変化する電源
VBTによつて駆動される。またフルブリツジ81
と並列に固定抵抗R1,R2、可変抵抗R3および電
源δVxx′が直列して結線されている。該ブリツジ
の出力は、電源VBTの変化に対して直線的変化を
示す条件に挿入された可変抵抗r1,r2の比x,
x′によつて決められている。該出力の一方はコン
デンサC2へ、他の一方はアナログスイツチSA3
介してコンデンサC1へ結合されている。前記可
変抵抗R3の出力端子は前記ブリツジの出力にお
ける変化成分ZVBTとなるように選定されてアナ
ログスイツチSA1を介してコンデンサC1、さらに
コンデンサC2へと配設されている。また可変抵
抗R3は固定抵抗R2、一定電圧δVxx′と直列に結合
され、ブリツジの一端とともにアナログスイツチ
SA3に配設されている。ここでアナログスイツチ
SA1およびSA2は駆動パルスPによつて同位相で
開閉され、SA3はインバータIによつて反転され
て駆動される。動作は次のように2シフトで行わ
れる。
In FIG. 9, gauge resistances R p , R' p , R o , R' o that show resistance increases and decreases according to pressure are configured in a full bridge shape 81 , and a power source that changes according to temperature.
Driven by V BT . Also full bridge 81
Fixed resistors R 1 , R 2 , variable resistor R 3 , and power supply ΔV xx ' are connected in series in parallel with . The output of the bridge is determined by the ratio x of the variable resistors r 1 and r 2 inserted under the condition that it shows a linear change with respect to the change in the power supply V BT ,
It is determined by x′. One of the outputs is coupled to capacitor C2 and the other to capacitor C1 via analog switch SA3 . The output terminal of the variable resistor R 3 is selected to be a variable component ZV BT in the output of the bridge and is connected via an analog switch SA 1 to a capacitor C 1 and then to a capacitor C 2 . Also, variable resistor R 3 is coupled in series with fixed resistor R 2 and constant voltage δV xx ', and together with one end of the bridge, an analog switch is connected.
Located in SA 3 . analog switch here
SA 1 and SA 2 are opened and closed in the same phase by the drive pulse P, and SA 3 is inverted and driven by the inverter I. The operation is performed in two shifts as follows.

(1) SA1,SA2がonで、SA3がoffのとき、 可変抵抗R3の出力端子から電位ZVBT
δVxx′がコンデンサC1にチヤージされる。
(1) When SA 1 and SA 2 are on and SA 3 is off, the potential ZV BT + from the output terminal of variable resistor R 3
δV xx ′ is charged to the capacitor C 1 .

(2) SA1,SA2がoffで、SA3がonになると、 ブリツジ81の出力端子からは圧力出力と温
度ドリフト成分の合成値がC1にチヤージされ
た電荷と重畳されてC2へチヤージされる。
(2) When SA 1 and SA 2 are off and SA 3 is on, the composite value of pressure output and temperature drift component is superimposed on the charge charged to C 1 from the output terminal of bridge 81 and sent to C 2 . Charged.

ここでC1には1)により既にZVBT+δVxx′がチ
ヤージされているが、この値は、ブリツジ81
出力の温度ドリフト成分であるから、互に相殺さ
れてC2には圧力出力のみがチヤージされる。す
なわち温度ドリフトを消去された圧力出力が外部
出力となつて現われる。
Here, C 1 has already been charged with ZV BT + δV xx ' due to 1), but since this value is a temperature drift component of the output of the bridge 81 , they cancel each other out, and C 2 has only the pressure output. is charged. That is, the pressure output from which temperature drift has been eliminated appears as an external output.

以上詳述した例は、ブリツジ回路内に固定抵抗
を挿入して、積極的に零点温度変動を補償する場
合である。この補償条件を得るには、積極的に低
温、中温、高温の条件に素子を曝して、x,x′を
求めなければならない。そのかわり、一たび条件
を求めれば、0.1%フルスケール以上の高精度を
得ることができる。このような高精度補償とは別
に、数%フルスケール程度で良いから、常温のみ
の調整できるなら低コスト化の用途がある。この
場合にはブリツジ回路内には固定抵抗を挿入しな
いで、最初から内部結線した素子を製作する方法
をとる。ICの製法と同じく、規格に合格するも
のだけを自動検査装置で選別する方法である。こ
のような場合のブリツジのオフセツト電圧を相殺
する場合にも、本発明は有効である。第10図は
その一例を示す回路構成である。
The example detailed above is a case where a fixed resistor is inserted into the bridge circuit to actively compensate for zero point temperature fluctuations. In order to obtain this compensation condition, x and x' must be determined by actively exposing the element to low, medium, and high temperature conditions. Instead, once the conditions are determined, high accuracy of 0.1% full scale or higher can be obtained. Apart from such high-precision compensation, it can be used to reduce costs if only a few percent of the full scale can be adjusted, and only room temperature can be adjusted. In this case, a fixed resistor is not inserted into the bridge circuit, and an internally connected element is manufactured from the beginning. Similar to the manufacturing method for ICs, this method uses automatic inspection equipment to select only those that pass the standards. The present invention is also effective in canceling out the bridge offset voltage in such cases. FIG. 10 shows a circuit configuration showing an example thereof.

この図において、圧力に感ずる歪ゲージRp
R′p,Ro,R′oを組んだフルブリツジ回路91には
固定抵抗が挿入されていない。ブリツジは温度と
連動する電源VBTによつて駆動され、これと並列
に固定抵抗R1,R2、可変抵抗R3を直列にしたブ
リーダ抵抗92が結線されている。今、ブリツジ
回路91の出力が圧力出力△P(P)の他に零点
出力(オフセツト電圧)δVpと重畳されたもので
あるとする。ブリーダ92の可変抵抗R3を比ω
に調節し、R3×ω×VBT=δVpにセツトする。切
換連動スイツチSM1,SM2はこの場合、下で閉じ
る。クロツクパルスPにより、アナログスイツチ
SA1,SA2,SA5,SA7がonになると、可変抵抗
R3から出たδVp電圧が、コンデンサC1にチヤージ
される。この場合、アナログスイツチSA3
SA4,SA6はパルス波形がインバータIで反転さ
せられるため、off状態にある。次にSA1,SA2
SA5,SA7がoffになり、SA3,SA4,SA6がonに
なると、ブリツジ91の出力△P+δVpは、先に
チヤージされたC1の電位に重畳される。このと
き、先にC1にチヤージされたδVpと、ブリツジ出
力の△P+δVpとは極性が異るため、 −δVp+△P+δVp→△P となる。つまり、圧力出力のうちの一定電位成分
を相殺することができる。ここで出た△Pは差動
増幅器OP1で増幅され、次段の演算増幅器OP2
再び増幅される。
In this figure, the strain gauge R p that feels pressure,
No fixed resistor is inserted in the full bridge circuit 91 that combines R' p , R o , and R' o . The bridge is driven by a temperature-dependent power supply V BT , and a bleeder resistor 92 is connected in parallel with the power supply V BT in which fixed resistors R 1 , R 2 and variable resistor R 3 are connected in series. Assume now that the output of the bridge circuit 91 is the pressure output ΔP(P) and the zero point output (offset voltage) δV p superimposed. The variable resistance R 3 of the bleeder 92 is compared to ω
and set R 3 ×ω×V BT = δV p . In this case, the interlocking switches SM 1 and SM 2 close at the bottom. Analog switch is activated by clock pulse P.
When SA 1 , SA 2 , SA 5 , and SA 7 are turned on, the variable resistance
The δV p voltage from R 3 is charged to capacitor C 1 . In this case, analog switch SA 3 ,
Since the pulse waveforms of SA 4 and SA 6 are inverted by the inverter I, they are in an off state. Next, SA 1 , SA 2 ,
When SA 5 and SA 7 are turned off and SA 3 , SA 4 and SA 6 are turned on, the output ΔP+δV p of the bridge 91 is superimposed on the previously charged potential of C 1 . At this time, since δV p previously charged to C 1 and ΔP+δV p of the bridge output have different polarities, -δV p +ΔP+δV p →ΔP. In other words, the constant potential component of the pressure output can be canceled out. The ΔP produced here is amplified by the differential amplifier OP1 , and then again amplified by the next stage operational amplifier OP2 .

ここでオフセツト電圧成分δVpの極性が異り、
△P−δVpの場合には、第9図の切換連動スイツ
チSM1,SM2を上にして、ブリーダ92による出
力の極性を反転させれば、同じ相殺効果を得るこ
とができる。
Here, the polarity of the offset voltage component δV p is different,
In the case of ΔP-δV p , the same canceling effect can be obtained by turning the interlocking switches SM 1 and SM 2 of FIG. 9 upward and reversing the polarity of the output from the bleeder 92 .

以上詳述したように、本発明に係る手法を用い
れば、圧力検出用のブリツジ回路内に固定抵抗を
挿入する場合も、しない場合もそれによつて生ず
るオフセツト電圧を消すことが可能である。従来
法ではオフセツト電圧の極性が異る場合、2電源
化が必要であたつが、本発明は1電源で良いなど
の利点がある。
As described in detail above, by using the method according to the present invention, it is possible to eliminate the offset voltage caused by whether or not a fixed resistor is inserted into the bridge circuit for pressure detection. In the conventional method, when the polarity of the offset voltage is different, it is necessary to use two power supplies, but the present invention has the advantage that only one power supply is required.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図はそれぞれ従来装置の例を示す
構成図、第3図本発明者らが既に提案したハーフ
ブリツジ形零点補償法を説明するためのブリツジ
構成図、第4図、第5図は補償動作の説明図、第
6図は第3図をフルブリツジに拡張した場合の構
成図、第7図、第8図はフルブリツジの動作説明
図、第9図はフルブリツジに本発明に係る零点温
度補償法を適用した回路構成の一例図、第10図
は本発明の他の構成例である。
FIGS. 1 and 2 are block diagrams showing examples of conventional devices, respectively; FIG. 3 is a bridge block diagram for explaining the half-bridge zero point compensation method already proposed by the inventors; and FIGS. 4 and 5. 6 is an explanatory diagram of the compensation operation, FIG. 6 is a configuration diagram when FIG. 3 is extended to a full bridge, FIGS. 7 and 8 are explanatory diagrams of the operation of a full bridge, and FIG. 9 is a diagram of the zero point temperature according to the present invention in a full bridge. FIG. 10, which is an example of a circuit configuration to which the compensation method is applied, is another configuration example of the present invention.

Claims (1)

【特許請求の範囲】[Claims] 1 一対の駆動電圧印加端子および一対の出力端
子を有し、圧力に感応して異符号の抵抗変化を示
す一対のゲージ抵抗片を並列に結線して構成した
フルブリツジ回路と、このフルブリツジ回路の駆
動電圧印加端子間に温度変化に応動して駆動電圧
を可変設定して印加する電源回路と、前記駆動電
圧から接地電位までの任意の電位を所得できるよ
う前記フルブリツジ回路の駆動電圧印加端子間に
接続された可変抵抗および複数の固定抵抗から成
るブリーダ抵抗と、このブリーダ抵抗により取得
された電位をチヤージするための第1のコンデン
サと、この第1のコンデンサの両端に前記ブリー
ダ抵抗からの取得電位を選択的に供給する第1お
よび第2のアナログスイツチと、前記フルブリツ
ジ回路の一方の出力端子と、前記第1のコンデン
サとの一端との間に接続された第2のコンデンサ
と、前記フリブリツジ回路の他方の出力端子と前
記第1のコンデンサの他端との間に接続され前記
第1および、第2のアナログスイツチに対して相
補的に開閉される第3のアナログスイツチとを具
備したことを特徴とする圧力検出装置。
1. A full bridge circuit that has a pair of drive voltage application terminals and a pair of output terminals, and is configured by connecting a pair of gauge resistor pieces in parallel that exhibit resistance changes of opposite signs in response to pressure, and the drive of this full bridge circuit. A power supply circuit that variably sets and applies a drive voltage between the voltage application terminals in response to temperature changes, and a connection between the drive voltage application terminals of the full bridge circuit so that any potential from the drive voltage to the ground potential can be obtained. a bleeder resistor consisting of a variable resistor and a plurality of fixed resistors, a first capacitor for charging the potential acquired by the bleeder resistor, and a potential acquired from the bleeder resistor across both ends of the first capacitor. a second capacitor connected between one output terminal of the full bridge circuit and one end of the first capacitor; A third analog switch connected between the other output terminal and the other end of the first capacitor and opened and closed in a complementary manner to the first and second analog switches. pressure detection device.
JP4545081A 1981-03-30 1981-03-30 Pressure detection device Granted JPS57160037A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4545081A JPS57160037A (en) 1981-03-30 1981-03-30 Pressure detection device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4545081A JPS57160037A (en) 1981-03-30 1981-03-30 Pressure detection device

Publications (2)

Publication Number Publication Date
JPS57160037A JPS57160037A (en) 1982-10-02
JPH0346771B2 true JPH0346771B2 (en) 1991-07-17

Family

ID=12719672

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4545081A Granted JPS57160037A (en) 1981-03-30 1981-03-30 Pressure detection device

Country Status (1)

Country Link
JP (1) JPS57160037A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61259134A (en) * 1985-05-14 1986-11-17 Sumitomo Electric Ind Ltd Semiconductive pressure sensor
JP6237453B2 (en) * 2014-03-05 2017-11-29 株式会社デンソー Physical quantity detection device

Also Published As

Publication number Publication date
JPS57160037A (en) 1982-10-02

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