JPH0346316A - Formation of resist pattern - Google Patents

Abstract

PURPOSE:To form a pattern size without a difference on a whole region inside a memory cell part by a method wherein, when a resist pattern is laid out, a dummy region which does not have a function as an electric circuit is formed in a vacant region inside a second circuit pattern region in such a way that a latent-image density of a resist film as a whole becomes uniform. CONSTITUTION:The following are provided: a first process to form a resist film on a semiconductor wafer, a second process to form a latent image in the resist film by an exposure operation; a third process to transform the latent image into a resist pattern. When a first circuit pattern region and a second circuit pattern region 103, 104 are formed in this case, dummy regions 104b which do not have a function as an electric circuit are formed in vacant regions near the first circuit pattern region 103 in such a way that a latent-image density of the resist film as a whole becomes a uniform state; after that, the third process is executed. When the dummy regions 104b are formed near a periphery of the memory cell part 103 in this manner, it is possible to prevent that an error is caused in a pattern size between the central part of cell blocks 103a and the cell blocks 103a near the periphery of the memory cell part 103.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for forming a resist pattern formed using a photolithography process as a manufacturing process for semiconductor integrated circuits and the like.

(Prior Art) Conventionally, such fields include, for example, the one shown in FIG. The configuration will be explained below using figures.

FIG. 2 is a schematic configuration diagram showing one configuration example of a resist pattern used in a conventional memory LSI.

This resist pattern 1 is formed on the surface of a semiconductor wafer so as to make effective use of its area, and a plurality of chip parts 3 are arranged in a lattice shape with a slide line part 2 as a boundary. Inside each chip section 3, a memory cell section 4 and a circuit pattern section 5 are provided, respectively.

The memory cell section 4 has cell blocks (not shown) made up of repeated fine patterns, and the cell blocks are regularly arranged.

Moreover, the circuit pattern of the memory cell section 4 is highly dense and uniformly formed. The circuit pattern section 5 provided around the memory cell section 4 has a plurality of circuit patterns, and each of the circuit patterns is arranged without particular regularity, and some of them are very large in size, and the pattern density is low. is also low.

Figures 3 (1) to (5) are manufacturing process diagrams showing a conventional resist pattern forming method.
(Each step will be explained with reference to 5>.

(A> Process of FIG. 3(1) Heat treatment is performed to remove adsorbed materials such as silicon on the semiconductor wafer 10. As a result, S
An oxide insulating film 11 such as i02 is formed.

(B) Process shown in Figure 3 (2) A resist film 12 is applied on the oxide insulating film 11.

Subsequently, in order to remove the organic solvent remaining in the applied resist film 12, heat treatment is performed at about 80° C. in a dry atmosphere.

(C) Process of FIG. 3(3) An original image corresponding to the resist pattern 1 as shown in FIG. 2 is transferred as a light-blocking image onto the surface of a transparent glass plate or the like to create a photomask 13. Next, this photomask 1
3 is placed on the surface of the resist film 12, and ultraviolet light 13a is irradiated from above the photomask 13 (exposure). As a result of this exposure, the portions of the resist film 12 exposed to the ultraviolet light 13a become polymerized. As a result, a latent image corresponding to the resist pattern 1 as shown in FIG. 2 is formed in the resist film 12.

(D> A developing solution such as an organic solvent is sprayed onto the resist film 12 on which the process latent image of FIG. The parts that remain undissolved and are not exposed to light melt, forming a resist pattern.

(E) At the end of the process shown in FIG. 3(5), the portions not covered with the resist film 12 are removed by etching to obtain a resist pattern 1 as shown in FIG. 2.

By the way, the memory cell part 4 is MO8FE, which requires pattern dimensional accuracy sufficient to satisfy ultra-precision.
It may have a T-type transistor structure, and the pattern size is required to be formed without any difference throughout the memory cell section 4.

(Problems to be Solved by the Invention) However, the above method for forming a resist pattern has the following problems. This will be explained below using figures.

FIGS. 4(a) and 4(b) are diagrams showing the dissolved state of the resist film 12 during the development process in the step of FIG. 3 (4>).

4(a) shows the dissolved state of the resist film 12 in the central part of the memory cell section 4 shown in FIG. 2(A), and FIG. It shows the melted state of the resist film 12 in a corner portion of the memory cell portion 4 and the chip portion 3 shown in (B). A resist film 12 having a latent image formed in the step of FIG. 3 (3>) is formed on the semiconductor wafer 10, and a resist film 12 having a latent image formed in the step of FIG. A developing solution 12a is placed in the tank.

By the way, there is a large difference in pattern density between parts (A) and (B) in FIG. In other words, the pattern density is high in the (A> part), and much lower in the (B) part.
Although the area No. 2 is small, most of the resist film 12 in the part (B) is dissolved by development. As a result, the developer 12a
The concentration of the dissolved resist film 12b therein is low in the (A> part) and considerably high in the (B) part, (A).

A slight difference in density occurs in part (B). This results in
The developing ability of the developer in contact with part (B) decreases, and there is a dimensional difference in the resist pattern between the cell block of memory cell part 4 in part (A>) and the cell block near part (B). There was a possibility that this might occur.

This problem was not a problem when forming resist patterns with dimensions of around 1 μm, but
This is an important problem that cannot be ignored in resist pattern formation for LSI, which requires dimensional accuracy of about 0.8 μm.

The present invention provides a method for forming a resist pattern that solves the problem of the prior art in that a difference in pattern density causes a difference in concentration of a developer, resulting in a difference in pattern dimensions. .

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a first step of forming a resist film on a semiconductor wafer, and a predetermined resist film provided on each of a plurality of chip parts on the semiconductor wafer. A latent image having a first circuit pattern region having a pattern density of In the method for forming a resist pattern, the method includes a second step of forming the latent image in the resist film, and a third step of converting the latent image into a resist pattern using a developer, wherein the first and second circuit pattern regions After forming a dummy region having no function as an electric circuit in an empty region near the first circuit pattern region so that the latent image density of the entire resist film becomes substantially uniform during formation, The structure is such that the third step is performed.

(Function) According to the present invention, since the resist pattern forming method is configured as described above, the dummy region functions to make the latent density of the entire resist film substantially uniform. This works to eliminate the difference in concentration of the developer and the difference in size of the resist pattern.

Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a schematic configuration diagram of a resist pattern used in a memory LSI showing an embodiment of the present invention.

This resist pattern 100 is formed on the surface of a semiconductor wafer, and a plurality of chip portions 102 are arranged in a lattice shape with a slide line portion 101 as a boundary in order to effectively utilize the area of the wafer surface. Each chip part 102
includes first and second circuit pattern areas 103, 10.
4 are provided respectively.

The first circuit pattern area 103, which is a memory cell part, is
It has a plurality of cell blocks 103a configured by repeating fine patterns, and the cell blocks 103a are regularly arranged.

Moreover, the circuit pattern in the first circuit pattern area 103 is dense and uniformly formed.

The second circuit pattern area 104 provided around the first circuit pattern area 103 has a plurality of circuit pattern parts 104a, and each of the circuit pattern parts 104a is arranged without particular regularity and has a dimension There are also some very large patterns, and the pattern density is low. Furthermore, a resist pattern 100 is placed in the empty area of the second circuit pattern area 104.
A plurality of dummy regions 104b having no function as an electric circuit are provided so that the overall pattern density is substantially uniform.

5(1) to 5(5) are manufacturing process diagrams of a resist pattern forming method showing an embodiment of the present invention.
Each step will be explained with reference to Figures (1> to (5)).

(A) Step of FIG. 1 (1) Heat treatment is performed to remove adsorbed materials such as silicon on the semiconductor wafer 110. As a result, an oxide insulating film 111 such as 5i02 is formed on the semiconductor wafer top 50.

(B) The oxide insulating film 11 is formed using the process spin code method, spray method, etc. in FIG.
A resist film 112 is applied uniformly over the resist film 112. Subsequently, in order to remove the organic solvent remaining in the applied resist film 112, heat treatment is performed at about 80° C. using an electric oven or infrared heating in a dry atmosphere such as dry N2 gas.

(C) Process of FIG. 1 (3) An original image corresponding to the resist pattern 100 as shown in FIG. 1 is transferred as a light-blocking image onto the surface of a transparent glass plate, etc. using a method such as reading with a digitizer. death,
A photomask 113 is created. Next, this photomask 1
13 is superimposed on the surface of the resist M112, and ultraviolet light 113a is irradiated from above the photomask 113 using, for example, an ultra-high pressure mercury lamp of around 200 W (exposure). By this exposure, the portions of the resist that are irradiated with the ultraviolet light 113a are The film 112 is polymerized. As a result, latent images corresponding to the resist pattern 100 as shown in FIG. Ru.

(D) Process of FIG. 1(4) For example, using a spray method, a table on which a number of semiconductor wafers 100 on which latent images have been formed is rotated, and a developer such as an organic solvent is sprayed thereon.

Then, the resist film 112 that has been made into a polymer by being exposed to the ultraviolet light 113a remains undissolved in the developer, and the portions that are not exposed to the light 113a are dissolved, forming a resist pattern. After development, the film is rinsed with a type of solvent different from the developer, and then dried with dry N2 gas or the like.

(E) At the end of the process shown in FIG. 1(5), if the portion not covered with the resist film 112 is removed by vapor phase etching such as sputter etching, the first
A resist pattern 100 as shown in the figure is obtained.

This embodiment has the following advantages.

(1> FIG. 6 is a diagram showing the dissolved state of the resist film 112 during the development process in a cross-sectional area between the broken line Ia and Ib in FIG. I.

By providing the dummy region ↓04b near the periphery of the memory cell portion 103, the dissolved region of the resist film 112 in the vicinity is reduced. Therefore, as shown in Figure 6,
The concentration of the developer 112a existing in this vicinity can be made almost equal to the concentration of the developer 112a in contact with the center of the cell block 103a. This can prevent errors in pattern dimensions between the center of the cell block 103a and the cell block 03a near the periphery of the memory cell section 103.

(2) By providing the dummy region 104b, it is possible to reduce the area to be etched in the etching process after the photogelatinization process, so the amount of etching agent (etchant) that disappears in the etching reaction is reduced, and the etching rate is reduced. We can expect improvement.

Note that the present invention is not limited to the above embodiments, and various modifications are possible. For example, the following variations are available.

(I) In the above embodiment, the first circuit pattern area is the memory cell portion 103, but other circuit configurations may be used.

(I) In the above embodiment, the photomask 113 was used to form a latent image in the resist film 112. It is also possible to form latent images.

(I[I) In the step (5) of FIG. 1, the portion not covered with the resist film 112 was removed using vapor phase etching such as sputter etching, but other dry etching methods may be used. It is also possible.

(Effects of the Invention) As described in detail above, according to the present invention, in the resist pattern layout, the latent image density of the entire resist film is made uniform in the empty area in the second circuit pattern area. , a dummy area that does not function as an electric circuit is provided, and a latent image of the resist pattern is formed in the resist film by exposure, so when the latent image is converted into a resist pattern using a developer, the area near the dummy area is The dissolved area of the resist film is reduced. Therefore, the concentration of the developer existing in this vicinity can be made almost equal to the concentration of the developer in contact with the center of the first circuit pattern area. This can prevent errors in pattern dimensions between the center of the second circuit pattern area and the vicinity of the periphery of the second circuit pattern area.

Furthermore, in the etching process after the photogelatinization process, the area to be etched can be reduced, so the etching material (which disappears by the etching reaction) can be reduced.
Since the amount of etchant (etchant) is reduced, an improvement in etching speed can be expected.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a resist pattern showing an embodiment of the present invention, FIG. 2 is a configuration diagram of a conventional resist pattern, and FIGS. 3 (1) to (5) are manufacturing methods showing a conventional resist pattern forming method. Process diagrams, FIGS. 4(a>, <b) are diagrams showing the dissolved state of the resist film in FIG. 3, and FIGS. 5(1) to (5>) are resist pattern formation showing examples of the present invention. The manufacturing process diagram of the method, FIG. 6, is a diagram showing the dissolved state of the resist film in FIG. 5. 100...Resist pattern, 102... Chip portion, 103... a first circuit pattern area;
104... Second circuit pattern area, 104a
...Circuit pattern portion, 104b...Dummy region, 110...Semiconductor wafer, 112.
...Resist film, 112a...Developer.

Claims (1)

[Claims] A first step of forming a resist film on a semiconductor wafer;
A first circuit pattern area having a predetermined pattern density provided on each of the plurality of chip parts on the semiconductor wafer, and a first circuit pattern area having a lower pattern density than the first circuit pattern area and being arranged near the first circuit pattern area. a second step of forming a latent image having two circuit pattern areas in the resist film by exposure; and a third step of converting the latent image into a resist pattern using a developer. In the forming method, when forming the first and second circuit pattern regions, an electric circuit is formed in an empty area in the second circuit pattern region so that the latent image density of the entire resist film is approximately uniform. After forming a dummy area that has no function as
A resist pattern forming method characterized by performing the third step.