JPH0346297A - Forming of via - Google Patents
Forming of viaInfo
- Publication number
- JPH0346297A JPH0346297A JP18170389A JP18170389A JPH0346297A JP H0346297 A JPH0346297 A JP H0346297A JP 18170389 A JP18170389 A JP 18170389A JP 18170389 A JP18170389 A JP 18170389A JP H0346297 A JPH0346297 A JP H0346297A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- titanium oxide
- wall
- film
- copper powder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims abstract description 25
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 22
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims abstract description 17
- 239000000945 filler Substances 0.000 claims abstract description 12
- 239000003795 chemical substances by application Substances 0.000 claims abstract description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 8
- 238000005245 sintering Methods 0.000 claims description 6
- 239000002313 adhesive film Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 3
- 238000010304 firing Methods 0.000 claims 1
- 239000000919 ceramic Substances 0.000 abstract description 12
- 239000004020 conductor Substances 0.000 abstract description 7
- 230000006378 damage Effects 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 239000000203 mixture Substances 0.000 abstract description 3
- 239000011800 void material Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 22
- 239000002344 surface layer Substances 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 239000010410 layer Substances 0.000 description 7
- 238000010276 construction Methods 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- FAPWRFPIFSIZLT-UHFFFAOYSA-M Sodium chloride Chemical compound [Na+].[Cl-] FAPWRFPIFSIZLT-UHFFFAOYSA-M 0.000 description 2
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000011780 sodium chloride Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000004506 ultrasonic cleaning Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概 要〕
各種電子機器の構成に広く使用される多層プリント回路
基板の基板内接続用のビア形成方法に関し、
セラミックスよりなる絶縁基体のビアホールに対して密
着性の優れた介在膜を形成して、その内部に導電性の優
れた導体を設ける新しいビア形成方法の提供を目的とし
、
一定厚みに成形して加熱と加圧を行った絶縁基体の基板
内接続用ビアホールに、有機チタネートと銅粉末を混合
したペースト状の密着膜形成剤を充填して焼成し、前記
有機チタネートを酸化チタンに成長させるとともに銅粉
末を焼結した後、焼結された前記、銅粉末を溶解、除去
して内壁に酸化チタン膜を形成し、当該酸化チタン膜の
内部に導電性の優れたビア充填剤を充填して積層、焼結
することによりビアを形成する。[Detailed Description of the Invention] [Summary] Regarding a method for forming vias for internal connections in multilayer printed circuit boards that are widely used in the construction of various electronic devices, the present invention relates to a method for forming vias for internal connections in multilayer printed circuit boards that are widely used in the construction of various electronic devices. With the aim of providing a new via formation method in which a highly conductive conductor is formed by forming an intervening film inside the via hole, the insulating substrate is formed to a certain thickness and heated and pressurized to form a via hole for connection within a substrate. is filled with a paste-like adhesion film forming agent that is a mixture of organic titanate and copper powder, and fired to grow the organic titanate into titanium oxide and sinter the copper powder, and then the sintered copper powder. A titanium oxide film is formed on the inner wall by dissolving and removing the titanium oxide film, and a via filler with excellent conductivity is filled inside the titanium oxide film, and the vias are formed by laminating and sintering.
〔産業上の利用分野］
本発明は、各種電子機器の構成に広く使用される多層プ
リント回路基板の基板内接続用のビア形成方法に関する
。[Industrial Field of Application] The present invention relates to a method for forming vias for internal connections in multilayer printed circuit boards that are widely used in the construction of various electronic devices.
最近、特に、大型電算機等に使用される多層プリント回
路基板は回路規模の増大と高速化の要求に伴いパターン
の微細化と多層化が進んでいるが、基板内接続用のビア
と絶縁基体のセラミックスとは密着性が悪いので、製造
工程において熱および薬品によるビア自体の断線、また
は表面層パターンを破壊する恐れがある。そのため、絶
縁基体に対して密着性の優れた新しいビア形成方法が要
求されている。Recently, the patterns of multilayer printed circuit boards used in large computers, etc. have become increasingly finer and more multilayered due to the demand for increased circuit scale and higher speed. Since the adhesiveness is poor with ceramics, there is a risk that the via itself may be disconnected or the surface layer pattern may be destroyed due to heat and chemicals during the manufacturing process. Therefore, a new method for forming vias with excellent adhesion to an insulating substrate is required.
従来広く使用されているビア形成方法を第３図の工程順
側断面図で示すように、
（ａ）は、一定厚みのスラリーを乾燥して加熱と加圧に
より焼鈍と密度の均一化を行った誘電体となる絶縁基体
１に、多数個の微細な基板内接続用ビアホール１−１を
パンチングシステム等により穿孔した状態、
（ｂ）は、絶縁基体１の上面にビア充填用の図示してい
ないスクリーンを被せ、その上に導電性の優れた金属粉
末１例えば銀−バラジュウムよりなるビア充填剤２−１
を搭載して、図示していないスキージ等にて前記ビアホ
ール１−１に当該ビア充填剤２−１を充填した状態、
（ｃ）は、ビア充填剤２−１を充填した絶縁基体１を複
数枚積層して高温で焼結することにより、各層間を接続
するビア２を形威した状態、
で示す工程順により多層セラミックス基板にビアを形成
している。As shown in the step-by-step side cross-sectional view in Figure 3, a conventionally widely used via forming method is shown in Fig. 3. (a) is a method in which a slurry of a certain thickness is dried and annealed by heating and pressure to make the density uniform. (b) shows a state in which a large number of fine via holes 1-1 for connection within the substrate have been punched in the insulating substrate 1, which serves as a dielectric material, using a punching system or the like. A via filler 2-1 made of highly conductive metal powder 1 such as silver-baladium is placed on top of the screen.
(c) shows a state in which a plurality of insulating substrates 1 filled with the via filler 2-1 are mounted and the via hole 1-1 is filled with the via filler 2-1 using a squeegee or the like (not shown). By laminating the layers and sintering them at high temperature, vias 2 connecting each layer are formed, and vias are formed in the multilayer ceramic substrate according to the process order shown below.
そして、積層された表裏両面に所定の表面層パターンを
印刷することにより、セラミックスからなる多層プリン
ト回路基板が形威されている。A multilayer printed circuit board made of ceramics is produced by printing a predetermined surface layer pattern on both the front and back surfaces of the stacked layers.
以上説明した従来のビア形成方法で問題となるのは、第
４図（ａ）に示すように一般にビア２の金属材料と絶縁
基体１のセラミックスとは密着性が悪いので、絶縁基体
１のビアホール１−１とビア２との界面に空孔が生じて
、後工程の表面層パターン３の形成１例えばメッキ等の
ＷＥＴプロセス時に薬剤がその空孔に浸透して腐食が発
生したり、第４図の（ｂ）に示すように表面層パターン
３形成後においても、内部からガス発生によりその表面
層パターン３を破壊する恐れがある。The problem with the conventional via forming method described above is that the metal material of the via 2 and the ceramic of the insulating substrate 1 generally have poor adhesion, as shown in FIG. Holes are generated at the interface between 1-1 and the via 2, and during the subsequent wet process of forming the surface layer pattern 3 (for example, plating), chemicals may penetrate into the pores and cause corrosion. As shown in (b) of the figure, even after the surface layer pattern 3 is formed, there is a risk that the surface layer pattern 3 may be destroyed due to gas generation from inside.
また、ビア２の材料は導電性の良い１例えば銀バラジュ
ウム等の金属であり、セラミックスからなる絶縁基体１
に比して熱膨張率が大きいので、ビアホール１−１とビ
ア２と密着して一体化していないと、プリント板の使用
時に熱がかかるとビア２が絶縁基体１より伸びて表面層
パターン３を破壊し、同様に熱ショックが繰り返される
とビア２の中間部に断線が生じてその補修に大きなコス
トを必要となるという問題が生じている。The material of the via 2 is a metal with good conductivity, such as silver baladium, and the insulating base 1 is made of ceramics.
Since the coefficient of thermal expansion is larger than that of the insulating substrate 1, if the via hole 1-1 and the via 2 are not closely integrated, the via 2 will extend beyond the insulating substrate 1 and the surface layer pattern 3 will be damaged when heat is applied when the printed board is used. If the via 2 is damaged and the thermal shock is repeated in the same way, a break occurs in the middle part of the via 2, causing a problem in that a large cost is required to repair it.
さらに、近年導体材料として低抵抗で且つ低コストの銅
が有望視されているが、銅とセラミックスとの密着性が
悪く両方の間に密着性の優れた介在物を挾む必要がある
という問題も生じている。Furthermore, in recent years, low-resistance and low-cost copper has been seen as a promising conductor material, but there is a problem in that the adhesion between copper and ceramics is poor and it is necessary to insert an inclusion with excellent adhesion between the two. is also occurring.
本発明は上記のような問題点に鑑み、セラミックスより
なる絶縁基体のビアホールに対して密着性の優れた介在
膜を形成して、その内部に導電性の優れた導体を設ける
新しいビア形成方法の提供を目的とする。In view of the above-mentioned problems, the present invention provides a new via forming method in which an intervening film with excellent adhesion is formed in the via hole of an insulating substrate made of ceramics, and a conductor with excellent conductivity is provided inside the intervening film. For the purpose of providing.
本発明は、第１図の工程順側断面図で示すように、一定
厚みに成形して加熱と加圧を行った絶縁基体１の基板内
接続用ビアホール１−１に、有機チタネートと銅粉末を
混合したペースト状の密着膜形成剤１３−１を充填して
焼成し、前記有機チタネートを酸化チタンに成長させる
とともに銅粉末を焼結した後、焼結された前記銅粉末を
融解、除去して内壁に酸化チタン膜１３を形威し、当該
酸化チタン膜１３の内部に導電性の優れたビア充填剤１
２−１を充填して積層、焼結することによりビア１２を
形成する。As shown in the cross-sectional side view of the process in FIG. Filled with a paste-like adhesion film forming agent 13-1 mixed with and fired, the organic titanate was grown into titanium oxide and the copper powder was sintered, and then the sintered copper powder was melted and removed. A titanium oxide film 13 is formed on the inner wall, and a via filler 1 with excellent conductivity is placed inside the titanium oxide film 13.
2-1 is filled, laminated, and sintered to form the via 12.
〔作 用］
本発明では、ビアホール１−１の内壁に形成されたＴｉ
ｅ、膜１３は、ビア１２の銅焼結剤と絶縁基体１のセラ
ミックスに対して共に密着性の優れており、そのビアホ
ール１−１のＴ ｉ Ｏ，膜１３内に充填したビア充填
剤２−１の銅粉末を焼結すると、その焼結銅とＴｉＯ２
膜１３が密着して絶縁基体１とビア１２が一体となるの
で、ビアホール１−１とビア１２との界面に空孔、或い
はビア１２の中間部の断線がなくなるとともに、プリン
ト板使用時の熱によるビア１２の熱膨張が抑制されて表
面層パターンの破壊を防止することが可能となる。[Function] In the present invention, the Ti formed on the inner wall of the via hole 1-1
e. The film 13 has excellent adhesion to both the copper sintering agent of the via 12 and the ceramic of the insulating substrate 1, and the T i O of the via hole 1-1 and the via filler 2 filled in the film 13 -1 copper powder is sintered, the sintered copper and TiO2
Since the film 13 is in close contact with the insulating substrate 1 and the via 12, there will be no holes at the interface between the via hole 1-1 and the via 12 or disconnection in the middle of the via 12, and there will be no heat loss when using a printed board. Thermal expansion of the vias 12 caused by this is suppressed, making it possible to prevent destruction of the surface layer pattern.
以下第１図および第２図について本発明の詳細な説明す
る。The present invention will be described in detail below with reference to FIGS. 1 and 2.
第１図は第一実施例によるビア形成方法を示す工程順側
断面図、第２図は第二実施例の工程順側断面図を示し、
図中において、第３図および第４図と同一部材には同一
記号が付している。FIG. 1 is a process-order side sectional view showing the via forming method according to the first embodiment, and FIG. 2 is a process-order side sectional view of the second embodiment.
In the figure, the same members as in FIGS. 3 and 4 are given the same symbols.
第一実施例のビア形成方法は、第１図の工程順側断面図
で示すように
（ａ）は、一定厚みのスラリーを乾燥して加熱と加圧に
より焼鈍と密度の均一化を行った絶縁基体１に、パンチ
ングシステム等により多数の基板内接続用のビアホール
１−１を従来と同様に穿孔した状態、
（ｂｌ）は、絶縁基体１の上面に図示していないスクリ
ーンを被せて、前記ビアホール１−１の内部に有機チタ
ネートと銅粉末を混合したペースト状の密着膜形成剤１
３−ｌを充填した状態、（ｂ２）は、上記密着膜形成剤
１３−ｌを充填した絶縁基体１を約ｓ ｏ ｏ ’ｃで
焼成して、有機チタネートをＴ ｉ Ｏｚに成長させる
とともに銅粉末を焼結した状態、
（ｂ３）は、銅が溶解する２例えば過硫酸アンモニウム
と塩化ナトリウムの混合液からなる選択エツチング剤に
浸漬して、ビアホール１−１内の焼結された銅粉末を融
解、除去し、超音波洗浄等によりビアホール１−１内を
洗浄して内壁にＴｉｅ、膜１３を形成した状態、
（ｂ４）は、絶縁基体ｌの上面にビア充填用の図示して
いないスクリーンを被せ、その上に導電性の優れた金属
粉末１例えば銅よりなるビア充填剤１２−１を搭載して
、図示していないスキージ等にて前記ＴｉＯ□膜１３の
内部に当該ビア充填剤１２−１を充填した状態、
（ｃ）は、上記ビア充填剤１２−■を充填した絶縁基体
１を複数枚積層して従来と同様に高温で焼結することに
より、各層間を接続するビア１２を形成した状態、
で示す工程順により多層セラミックス基板にビアを形成
している。In the via forming method of the first embodiment, as shown in the cross-sectional side view of the process in FIG. (bl) shows a state in which a large number of via holes 1-1 for connection within the board have been punched in the insulating substrate 1 using a punching system or the like in the conventional manner. Paste-like adhesive film forming agent 1 containing organic titanate and copper powder mixed inside via hole 1-1
3-l is filled, (b2) shows that the insulating substrate 1 filled with the adhesive film forming agent 13-l is fired at about soo'c to grow organic titanate to TiOz and to grow copper. The state in which the powder is sintered (b3) is immersed in a selective etching agent that dissolves copper, such as a mixture of ammonium persulfate and sodium chloride, to melt the sintered copper powder in the via hole 1-1. , and the inside of the via hole 1-1 is cleaned by ultrasonic cleaning or the like to form a Tie film 13 on the inner wall. (b4) shows a screen (not shown) for filling the via on the top surface of the insulating substrate l. A via filler 12-1 made of highly conductive metal powder 1, for example, copper is mounted thereon, and the via filler 12-1 is filled inside the TiO□ film 13 using a squeegee (not shown) or the like. (c) shows the via 12 that connects each layer by stacking a plurality of insulating substrates 1 filled with the via filler 12-■ and sintering them at high temperature in the same way as in the past. In the formed state, vias are formed in the multilayer ceramic substrate according to the process order shown in .
また、第二実施例のビア形成方法としては、第２図の工
程順側断面図で示すように、
（ｂ３）は、上記（ａ）〜（ｂ・２）と同一工程を経て
絶縁基体１のビアホール１−１内壁にＴ ｉ Ｏ，膜１
３を形成した状態、
（ｂ４）は、上記Ｔｉｅ、膜１３の内壁に導電性の優れ
たニッケル、または銅の無電解メッキを施して導電体２
２−１を形成した状態、
（ｃ）は、上記導電層２２−１を形成した絶縁基体ｌを
複数枚積層して、従来と同様に高温で焼結して各層間を
接続するビア２２を形成した状態、で示す工程順により
多層セラミックス基板にビアを形成している。In addition, as for the via forming method of the second embodiment, as shown in the step-order side cross-sectional view of FIG. T i O, film 1 is on the inner wall of via hole 1-1.
(b4) shows the state in which the conductor 2 is formed by applying electroless plating of nickel or copper, which has excellent conductivity, to the inner wall of the Tie and film 13.
2-1 is formed, (c) shows a state in which a plurality of insulating substrates l on which the conductive layer 22-1 is formed are laminated and sintered at a high temperature as in the past to form vias 22 to connect each layer. Vias are formed in the multilayer ceramic substrate according to the process order shown in the formed state.
そして、積層された表裏両面に所定の表面層パターンを
印刷することにより多層プリント回路基板を形成してい
る。A multilayer printed circuit board is formed by printing a predetermined surface layer pattern on both the front and back surfaces of the stacked layers.
その結果、ビアホール１−１の内壁に形成されたＴｉＯ
２膜１３により絶縁基体１のセラミックスとビア１２．
２２とが一体化されて、ビアホール１−１とビア１２．
２２との界面に空孔、或いはビアの中間部の断線がなく
なるとともに、熱によるビアの熱膨張が抑制されて表面
層パターンの破壊を防止することができる。As a result, TiO formed on the inner wall of via hole 1-1
The two films 13 connect the ceramics of the insulating substrate 1 and the vias 12.
22 are integrated, and the via hole 1-1 and the via 12.
There are no holes at the interface with 22 or disconnections at the intermediate portions of the vias, and thermal expansion of the vias due to heat is suppressed, making it possible to prevent destruction of the surface layer pattern.
［発明の効果］
以上の説明から明らかなように、本発明によれば極めて
簡単な方法でビアホールの内壁に密着性の優れた酸化チ
タン膜が形成されるので、セラミックスよりなる絶！！
基体と焼結銅からなるビアとが一体化されて空孔、或い
は断線がなくなるとともに、表面層パターンの破壊を防
止することができる等の利点があり、著しい経済的及び
、信頼性向上の効果が期待できるビア形成方法を提供す
ることができる。[Effects of the Invention] As is clear from the above explanation, according to the present invention, a titanium oxide film with excellent adhesion can be formed on the inner wall of a via hole using an extremely simple method. !
The base body and the via made of sintered copper are integrated, eliminating voids or disconnections, and has the advantage of preventing destruction of the surface layer pattern, resulting in significant economical and reliability improvement effects. It is possible to provide a via formation method that can be expected to provide the following.
第１図は本発明の第一実施例によるビア形成方法を示す
工程順側断面図、
第２図は第二実施例を示す工程順側断面図、第３図は従
来のビア形成方法を示す工程順側断面図、
第４図は課題を示す側断面図である。
図において、
１は絶縁基体、
１−１はビアホール、
１２．２２はビア、
１２−１はビア充填剤、
１３はＴ ｒ Ｏｚ膜、
１３−１は密着膜形成剤、
２２−１は導電体、
を示す。
第
図
第
図
オニ尤流側１零Ｔ側断面図
第２図FIG. 1 is a process-order side cross-sectional view showing a via forming method according to a first embodiment of the present invention, FIG. 2 is a process-order side cross-sectional view showing a second embodiment, and FIG. 3 is a conventional via-forming method. Step-by-step side sectional view. Figure 4 is a side sectional view showing the problem. In the figure, 1 is an insulating substrate, 1-1 is a via hole, 12.22 is a via, 12-1 is a via filler, 13 is a TrOz film, 13-1 is an adhesive film forming agent, 22-1 is a conductor , indicates. Figure Figure Figure 1 Zero T side sectional view Figure 2
Claims (2)
（１）の基板内接続用ビアホール（１−１）に、有機チ
タネートと銅粉末を混合したペースト状の密着膜形成剤
（１３−１）を充填して焼成し、前記有機チタネートを
酸化チタンに成長させるとともに銅粉末を焼結した後、
焼結された前記銅粉末を溶解，除去して内壁に酸化チタ
ン膜（１３）を形成し、当該酸化チタン膜（１３）の内
部に導電性の優れたビア充填剤（１２−１）を充填して
積層，焼結することによりビア（１２）を形成すること
を特徴とするビア形成方法。(1) A paste-like adhesive film forming agent (mixed with organic titanate and copper powder) ( After filling and firing 13-1) to grow the organic titanate into titanium oxide and sintering the copper powder,
The sintered copper powder is melted and removed to form a titanium oxide film (13) on the inner wall, and a highly conductive via filler (12-1) is filled inside the titanium oxide film (13). A via forming method characterized in that a via (12) is formed by laminating and sintering.
た金属よりなる無電解メッキを施したことを特徴とする
請求項１記載のビア形成方法。(2) The via forming method according to claim 1, wherein the inner wall of the titanium oxide film (13) is electroless plated with a metal having excellent conductivity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18170389A JPH0346297A (en) | 1989-07-13 | 1989-07-13 | Forming of via |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18170389A JPH0346297A (en) | 1989-07-13 | 1989-07-13 | Forming of via |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0346297A true JPH0346297A (en) | 1991-02-27 |
Family
ID=16105381
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18170389A Pending JPH0346297A (en) | 1989-07-13 | 1989-07-13 | Forming of via |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0346297A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6054652A (en) * | 1997-04-18 | 2000-04-25 | Fujitsu Limited | Thin-film multi-layer substrate and electronic device |
-
1989
- 1989-07-13 JP JP18170389A patent/JPH0346297A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6054652A (en) * | 1997-04-18 | 2000-04-25 | Fujitsu Limited | Thin-film multi-layer substrate and electronic device |
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