JPH0346016A - Bus control system - Google Patents

Abstract

PURPOSE:To prevent the increase of power consumption and the deterioration of an element owing to heat generation by preventing the reception terminal of a data reception means receiving data from coming in an open state for a long time in complementary MOS. CONSTITUTION:Plural first drivers 121 are driven by driving signals which are respectively supplied and the drivers transmit data for a bus 110. A decision means 131 decides that all the driving signals supplied to respective first bus drivers 121 are in a non-supplied state, drives a second bus 141 at that time and transmits data for the bus 110. Data transmitted to the bus 110 is received by complementary MOS in the data reception means 111. Thus, the reception terminal of the data reception means 111 receiving data is prevented from coming in the open state for a long time in comlementary MOS. Thus, the increase of power consumption and the deterioration of the element owing to heat generation can be prevented.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Examples ■, Correspondence between the Examples and FIG. 1 ■ , Configuration and operation of embodiments Effects of the invention [Summary] Regarding a bus control system in which complementary MOS is used to input and output data via a bus, prevention of increase in power consumption and deterioration of elements due to heat generation are achieved. A data receiving means receives data supplied via a bus using a complementary MOS, and a plurality of first bus drivers sends data to the bus in accordance with drive signals supplied to each first bus driver. , determination means for determining that all of the plurality of drive signals are not supplied; and based on the determination result of the determination means, sending data to the bus when all of the plurality of drive signals are not supplied. and a second bus driver.

In addition, a plurality of bus drivers transmit data to the bus using complementary MOS in accordance with drive signals supplied to each bus driver, and a switching signal is output in synchronization with switching of data transmission operations by the plurality of bus drivers. A drive signal limiter receives drive signals corresponding to each of the switching signal generation means and the plurality of bus drivers, and limits supply of the drive signal to the bus driver according to the switching signal output from the switching signal generation means. and means.

(Industrial Application Field) The present invention relates to a bus control system that uses complementary MOS (hereinafter referred to as CMOS) to input and output data via a bus.

[Prior art] CMOS includes n-channel type and n-channel type MOSFE.
It has a configuration that combines TTLs, has excellent features different from conventional logic elements, such as extremely low power consumption and a wide operating voltage range, and is widely used along with TTL.

FIG. 4 shows the configuration of a digital signal processing processor (hereinafter referred to as DSP) constructed using CMOS.

In the figure, the DSP 411 includes a processing execution unit (hereinafter referred to as ALU) 421 that performs operations such as addition and multiplication;
It is equipped with a ROM 431 that holds execution programs and data, a RAM 441 that stores execution data, registers 451 and 461 that exchange data with the outside of the DSP 411, and a bus driver 471 that sends data to an internal bus. The components are connected by an internal bus.

In this way, in the SF311, when the ALU421 etc. sends data to other components via the internal bus, the ALU
Data is set in an output register inside 421, and then a bus driver 471 composed of CMOS is driven to send the data to the internal bus. Also, the side that receives the data sent to the internal bus in this way (for example, RAM
441) receives data through an input register having an internal CMOS inverter or the like.

[Problems to be Solved by the Invention] In the above-mentioned conventional system, in order to avoid data collisions on the internal bus, the output end of the bus driver 471 that does not transmit data is placed in a high impedance state, and the bus is switched off. We are opening up.

Therefore, if a state occurs in which all bus drivers 471 do not send data to the internal bus, the CMO on the data receiving side
The input end of the S inverter etc. becomes a high impedance state (open state).

FIG. 5 shows the configuration of the CMOS Impark and the relationship between input and output. As shown in the figure, the CMOS inverter has pM
It has a configuration in which an O5FET and an nMOSFBT are connected as a pair, and when the input logic is "0°", p
Since the MOSFET is in the on state, the output logic is II
I II ((a) in the same figure). On the other hand, when the input logic is ``1°'', the nMOS FET is turned on, so the output logic becomes ``01'' (see Figure 1).
b)). If the input side of such a CMOS inverter is connected to an internal bus and the high impedance state (open state) of this input side continues for a long time, the pMOSFET and nMOSFE in the CMOS may be damaged depending on the potential state of the input side.
There may be a case where T is turned on at the same time, and the power supply V D !
1 Current will flow between +VSS ((C) in the same figure)
). Therefore, this energization increases power consumption, and this power consumption generates heat, which causes deterioration of the element.

Also, when switching the driving state of the bus driver 471 configured with CMOS (for example, when driving of the bus driver 471 connected to the ALU 421 is finished, then the ROM 431
(when driving the bus driver 471 connected to the bus driver 471), data may sometimes be sent from the two bus drivers 471 to the internal bus.

Sending data simultaneously from two bus drivers 471,
Moreover, when data with different logic is sent, the output terminal of the CMOS inverter shown in FIG.
The output terminal of the CMOS inverter shown in b) is connected, and the power supply Vn + V is connected from one pMOSFET, both of which are in the on state, through the other nMOSFET.
A current will flow between S2. Therefore, this energization increases power consumption, and this power consumption generates heat, which causes deterioration of the element.

The present invention was created in view of these points, and an object of the present invention is to provide a bus control method that prevents an increase in power consumption and deterioration of elements due to heat generation.

[Means to solve the problem]

FIG. 1 is a principle block diagram of the bus control system of the present invention.

i et al. 11 (1) In FIG. 1(A), data receiving means 111 receives data supplied via bus 110 by a complementary MOS.

Each of the plurality of first bus drivers 121 sends data to the bus 110 in accordance with the drive signal supplied thereto.

The determining means 131 determines that all of the plurality of drive signals are not supplied.

The second bus driver 141 sends data to the bus 110 when all of the plurality of drive signals are not supplied, based on the determination result of the determination means 131.

Therefore, as a whole, the second bus driver 131 is configured to be driven depending on the driving state of the plurality of first bus drivers 121.

In FIG. 1B, each of the plurality of bus drivers 151 sends data to the bus 150 using a complementary MOS according to the drive signal supplied to each bus driver 151.

The switching signal generation means 161 is configured to
A switching signal is output in synchronization with switching of the data sending operation by 51.

The drive signal limiting means 171 includes a plurality of bus drivers 151
A drive signal corresponding to each of these is input, and supply of this drive signal to the bus driver 151 is restricted in accordance with a switching signal output from the switching signal generating means 161.

Therefore, as a whole, the configuration is such that the supply of drive signals to each bus driver 151 is restricted when switching data sending operations by the plurality of bus drivers 151.

[For production]

The plurality of first bus drivers 121 are driven according to the drive signals supplied to each one, and send data to the bus 110. The determining means 131 determines that all of the drive signals supplied to each of the first bus drivers 121 are not supplied, and at this time drives the second bus 141 to send data to the bus 110. I do. bus 110
The data sent to is received by the complementary MOS in the data receiving means 111.

In the invention of claim 1, a plurality of first bus drivers 1
21 is not driven, the second bus driver 141 is driven when the receiving end of the data receiving means it1, which receives data with the complementary MOS, is kept open for a long time. This will be prevented.

The plurality of bus drivers 151 are driven according to drive signals supplied to each bus driver 1.
51 sends data to the bus 150 using a complementary MOS. The switching signal generating means 161 outputs a switching signal when the data/evening sending operation by each of these bus drivers 151 is switched, and the drive signal limiting means 171 to which this switching signal is input,
51 to prevent data transmission from multiple bus drivers 151 from overlapping.

In the invention of claim 2, when the data sending operation by each bus driver 151 is switched, the supply of the drive signal to each bus driver 151 is restricted according to the switching signal output from the switching signal generating means 161. This prevents a plurality of bus drivers 151 from being driven simultaneously.

[Example] Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of an embodiment of a DSP to which the bus control method of the present invention is applied.

(1) Here, the correspondence between the embodiment of the present invention and FIG. 1 will be shown.

Bus 110 corresponds to internal bus 291.

The data receiving means 111 includes input registers 271 and 273.
．． It corresponds to 275.

The first bus driver 121 is a bus driver 211.21.
This corresponds to 3,215.

The determining means 131 corresponds to the bus control circuit 231.

The second bus driver 141 corresponds to the bus driver 217.

Bus 150 corresponds to internal bus 291.

The bus driver 151 is connected to the bus drivers 211, 213, .
215, equivalent to 2.17.

The switching signal generating means 161 corresponds to the off circuit 255.

The drive signal limiting means 171 corresponds to the bus control circuit 231.

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

■ In Fig. 2, 211, 213, 215, 217 are bus drivers, 221, 223, 225, 227 are output registers, 231 is a bus control circuit, 251 is a decoder, 261 is a program counter, 263 is a program ROM, 265 is an instruction register, 271, 2
Reference numerals 73 and 273 indicate input registers, and 291 indicates an internal bus.

Note that FIG. 2 shows the configuration of the DSP focusing on data input/output operations via the internal bus 291, and the overall configuration is assumed to be the same as that in FIG. 4.

The bus drivers 211, 213, 215, and 217 are for sending data to the internal bus 291, and the logic of the drive signal supplied from the bus control circuit 231 is '°1''.
, the data held in the corresponding output registers 221 to 227 is sent to the internal bus 291. On the other hand, when the logic of the drive signal is "0", the output terminal is placed in a high impedance state to prevent data collision on the internal bus 291.

The output registers 221, 223, 225, and 227 are component parts (
For example, ROM, RAM, ALU, etc.) are provided, and after storing data in these output registers, the above-mentioned bus driver is driven.

In addition, the program counter 261 has a program RO
This is for specifying the address of M263. The program ROM 263 is addressed by the address output from the program counter 261, and the corresponding program is read out. The read program is once stored in the instruction register 265 and then supplied to the decoder 251.

Decoder 251 includes an output register selection circuit 253 and an off circuit 255. Output register selection circuit 25
3, three selection signals A for decoding the output of the instruction register 265 and selecting any one of the three bus drivers 211 to 215;

Create B and C. These selection signals are signals that become logic "1'" when driving the corresponding bus drivers, and are supplied to the bus control circuit 231.

Further, the off circuit 255 creates an off signal whose logic becomes "0" when switching the drive state of the bus driver.

Assuming that data transmission by each of the bus drivers 211 to 217 corresponds to one cycle of the operating clock signal, for example, an off signal is created that keeps the logic at "0" for a predetermined period of time from the rising edge of the operating clock signal. do.

The bus control circuit 231 controls all the bus drivers 211 to 2.
The bus control circuit 231 controls the output of the drive signal so that the logic of the drive signal supplied to the bus 17 does not become "O".
245, 247 and a Noah gate 249.

The selection signal A output from the output register selection circuit 253 is input to one input terminal of the AND gate 241, and the OFF signal output from the OFF circuit 255 is input to the other input terminal.

Similarly, the selection signal B is input to one input terminal of the AND gate 243, and the off signal is input to the other input terminal. The selection signal C is input to one input terminal of the AND gate 245, and the off signal is input to the other input terminal.

Furthermore, the output of the NOR gate 249 is input to one input terminal of the AND gate 247, and the off signal is input to the other input terminal. Three selection signals A, B, and C are input to the three input terminals of this NOR gate 249, respectively, and when all the logics are "O11", the output logic of the NOR gate 249 becomes "I11".

Further, the output of the AND gate 241 is supplied as a drive signal A to the bus driver 211. This drive signal A has a logic of "'O" only when the logic of the selection signal A output from the output register selection circuit 253 is 'l' and the logic of the off signal output from the off circuit 255 is not 'O'. This is a signal that becomes 1゛.

Similarly, the output of the AND gate 1243 is supplied as a drive signal B to the bus driver 213, the output of the AND gate 245 is supplied as a drive signal C to the bus driver 215, and the output of the AND gate 247 is supplied as a drive signal H to the bus driver 213. is supplied to

When all the logics of the three selection signals A, B, and C are "'0", the output logic of the NOR gate 249 becomes "l11", so all the logics of the three drive signals A, B, and C are "0". “
0"', the logic of the drive signal H becomes "°1".

In this way, one of the bus drivers 211-217 is always driven, and the corresponding output register 221-2
The data held in 27 is sent to internal bus 291.

The data sent to the internal bus 291 is input to the input register 27.
1 to 275 and taken in together.

For example, input register 271 is connected to internal inverter 281.
receives data supplied from internal bus 291. Similarly, input register 273 receives data through inverter 283 and input register 275 receives data through inverter 285.

FIG. 3 shows the operation timing of the embodiment. In the figure, "clock" indicates an operating clock signal, and each component operates in synchronization with this operating clock signal. In addition, "output register selection" is performed by the output register selection circuit 253.
A shows the output state of the selection signal A, B shows the output state of the selection signal B, C shows the selection state of the selection signal C, and the shaded area shows the selection signal A. B, C
Each shows a state in which none of the above is output.

Furthermore, the "off signal" is the signal output from the off circuit 255, and the "drive signals A, B, C, HJ are the signals output from the AND gate 24
The signals output from 1,243, 245, and 247 are shown, respectively.

As shown in FIG. 3, in synchronization with the rise of the operating clock signal, the output register selection circuit 253 generates a selection signal, and the off circuit 255 generates an OFF signal. The logic of the off signal becomes 0 for a predetermined time after the operation clock signal rises, and all drive signals A, B, and C are turned off.

The logic of H becomes "0" only during this short period of time.

Therefore, two or more of the bus drivers 211 to 217 are not driven at the same time, and two or more bus drivers with different output logics are driven.
It is possible to prevent excessive current from flowing through the CMOS in the driver and deterioration of the element due to heat generated by this excessive current.

Also, the logic of all three drive signals A, B, and C is “0”
and three bus drivers 211, 213, and 215.
When the output terminal of is in a high impedance state, the drive signal H output from the AND gate 247 is supplied to the bus driver 217, and the contents of the output register 227 are sent to the internal bus 291.

Therefore, in each cycle of the operating clock signal, one of the four bus drivers 211-217 is always driven, and the inverters 281-2 in the input register
The pMOSFET and nMOSFET that constitute the CMOS are eliminated by eliminating each input terminal of 85 from being in an open state for a long time.
It is possible to prevent an excessive current from flowing through the FET and from deteriorating the element due to heat generated by this excessive current.

In particular, in LSIs that combine an analog processing section and an SP as described above, noise caused by excessive current in the DSP is magnified in the analog processing section, so preventing this excessive current can reduce noise. can be realized.

In the embodiments of the present invention described above, the control of the internal bus in the DSP has been described, but the control of the internal bus in other processors such as microprocessors or the system when connecting these processors to the system bus is also applicable. The present invention can be applied to bus control.

Furthermore, in the embodiment, when the logics of the three selection signals A, B, and C are all ItO11, the logic of the drive signal H is set to "1°" and the contents of the output register 227 are sent to the internal bus 291. However, the contents of any one of the output registers 221 to 225 may be selected by the bus driver 217.

In this case, since the purpose is not to leave the internal bus 291 in an open state, the content of the data to be sent may be of any kind.

Furthermore, in the embodiment, the drive signal H is created by determining the logic of the three selection signals A, B, and C by the NOR gate 249, but the decoding operation of the output register selection circuit 253 allows the three selection signals A , B, and C are all "OII", a selection signal H whose logic is "1" may be created and input to one end of the AND gate 247.

〔Effect of the invention〕

As mentioned above, according to the invention of claim 1, a plurality of first
When the determining means determines that all of the bus drivers are not driven, the second bus driver is driven and the complementary M
By preventing the receiving end of the data receiving means that receives data from the OS from being open for a long time, it is possible to prevent an increase in power consumption and element deterioration due to heat generation in the complementary MO8 on the data receiving side. .

Further, according to the second aspect of the invention, when the data sending operation by each bus driver is switched, the supply of the drive signal to each bus driver is limited according to the switching signal output from the switching signal generating means. By preventing a plurality of bus drivers from being driven simultaneously, it is possible to prevent an increase in power consumption and deterioration of the element due to heat generation in the complementary MOS on the data output side.

[Brief explanation of drawings]

Figure 1 is a principle block diagram of the bus control method of the present invention, Figure 2
3 is an operational timing diagram of the embodiment, FIG. 4 is a configuration diagram of a DSP, and FIG. 5 is an explanatory diagram of a CMOS inverter. In the figure, 110 and 150 are buses, 111 is a data receiving means, 121 is a first bus driver, 131 is a determining means, 141 is a second path driver, 151 is a bus driver, 161 is a switching signal generating means, and 171 is a driving signal Limiting means, 211. 213, 215, 217 are bus drivers, 22
1.223, 225, 227 are output registers, 231 is a bus control circuit, 241.243.2'45, 247 is an AND gate, 2
49 is a NOR gate, 251 is a decoder, 253 is an output register selection circuit, 255 is an off circuit, 261 is a program counter, and 263 is a program ROM. 265 is an instruction register, 271.273, 275 is an input register, 281.28
3,285 is an inverter, and 291 is an internal bus. Disturbance news ((A) m kinf yakuza diagram DSP's ellipse 4th diagram s 5S (aan (b,) ■ dai (C) CMO 54 Nhata's accent B moon diagram diagram

Claims (2)

[Claims] (1) data receiving means (111) which receives data supplied via the bus (110) by a complementary MOS;
10), a plurality of first bus drivers (
121); determining means (131) for determining that all of the plurality of drive signals are not supplied; and based on the determination result of the determining means (131), all of the plurality of drive signals are not supplied. When the said bus (
a second bus driver (14) that sends data to (110);
1) A bus control method comprising: (2) A plurality of bus drivers (151) that send data to the bus (150) by complementary MOS according to drive signals supplied to each bus driver, and data sending operation by the plurality of bus drivers (151). Switching signal generating means (1) that outputs a switching signal in synchronization with the switching of
61) and the drive signal corresponding to each of the plurality of bus drivers (151) are input, and the drive signal is changed to the bus driver (151) according to the switching signal output from the switching signal generating means (161). 151); drive signal limiting means (171) for limiting supply to 151);