JP2652024B2 - Clock circuit and microprocessor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock circuit for distributing a clock in an LSI or the like, and more particularly to a clock circuit and a microprocessor suitable for supplying a clock to an ultra-high-speed logic circuit. About Setsusa.

[Conventional technology]

Conventionally, as disclosed in, for example, Japanese Patent Application Laid-Open No. Sho 61-172432, the focus has been on the development of a clock signal generator for obtaining a two-phase clock signal from a one-phase clock signal, and the clock after the distribution has been focused. No consideration was given to signal duplication.

[Problems to be solved by the invention]

In the above-mentioned prior art, there is no consideration for clock skew generated due to bias of the characteristics of the clock driver element or variation in load in the clock distribution system, and the circuit may malfunction due to the generation of the clock skew.

This circuit malfunction becomes more apparent as the clock frequency increases.

For example, Japanese Patent Application Laid-Open No. Sho 60-146315 discloses that after a clock signal from a two-input AND gate propagates to the end of the wiring of a digital circuit, the other two-input AND gate is further passed through a folded signal line and an inverter. The example connected to the input of the gate is shown. In this conventional example, a long wiring and a fan-out load must be driven before the clock signal of the two-input AND gate is supplied to the input of the other two-input AND gate, and a long time is required for driving. And This means that the peak width of the clock of each clock signal (the period during which the clock signal is at the H level) is reduced and narrowed, so that the effective time for the logical operation is reduced and the high-speed operation is hindered. .

An object of the present invention is to provide a clock circuit which corrects a clock skew which occurs in a clock distribution system and causes a malfunction, and which can fundamentally avoid a malfunction of the circuit, and a microprocessor provided with the clock circuit. is there.

[Means for solving the problem]

The above object is achieved by directly supplying the output of one clock driver to the input of the other clock driver between clock drivers generating a skew causing a malfunction in a clock supply unit for a circuit causing a malfunction. Is done.

That is, the present invention includes a multi-input clock driver having a first clock as input and a multi-input clock driver having a second clock as input. In a clock circuit serving as a signal, a clock circuit in which at least one output of the two multi-input clock drivers is directly connected to one input of the other multi-input clock driver is proposed.

The present invention also includes a multi-input clock driver having a first clock as input and a multi-input clock driver having a second clock as input. In a microprocessor including a clock circuit serving as a signal, at least one output of only the dual-input clock driver that outputs a clock signal to the next-stage clock synchronous logic circuit is input to one input of the other multiple-input clock driver. It proposes a microprocessor directly connected.

[Action]

The other clock driver that receives a clock signal from one clock driver outputs its own clock signal after receiving the clock signal. Therefore, the overlapping of clocks that causes a malfunction of the circuit is eliminated, so that the malfunction of the circuit due to the clock skew can be avoided.

In particular, the present invention employs a unique configuration in which at least one output of both multi-input clock drivers is directly connected to one input of the other multi-input clock driver. And high-speed operation becomes possible.

Also, in the case of incorporating into a microprocessor, at least one output of only two multi-input clock drivers for outputting a clock signal to the next-stage clock synchronous logic circuit is directly connected to one input of the other multi-input clock driver. A clock circuit that pursues severely the order relationship of the synchronization timing and a clock driver that does not pursue the severely the sequence relationship of the synchronization timing as well as those clock circuits can be mixed well and each can operate stably. .

〔Example〕

 Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of a clock circuit according to the present invention. In the figure, Is a non-overlapping two-phase clock signal. Main clock circuit 10
1 is the clock A clock driver 1 that receives as input and K1 and outputs K2;
Clock And a clock driver 2 which receives a control signal 3 and outputs a signal K1.

The connection line 4 provided according to the present invention is for outputting the K1 clock signal after the K1 clock signal is output, and for suppressing the overlap of the two clock signals.

This clock circuit 101 has clock driver outputs K1 and K1.
In the case where a skew occurs between 2 and 2, the operation is performed so that the latter half of the H level of K1 and the former half of the H level of K2 do not overlap. That is, if K1 does not change from H level to L level, K2
Does not change from the L level to the H level.

FIG. 2 shows an example of a general dynamic circuit using the clock output of the present invention as a clock signal. The dynamic circuit 102 includes a PMOS 11 for precharging, NMOSs 12 and 13 for discharging, and an output latch 19. K
1, K2, K1 'are clocks. The output latch 19 has K1
This is a type of latch in which data is sampled at the level and held at the L level. Dynamic Node
14 is the input of the latch 19. Inverter 18
It is for inverting K2.

Next, the operation of the dynamic circuit 102 will be described. When the clock K2 is at H level and K1 (K1 ') is at L level, the latch 19 holds the previous data and the node 14 holds.
Is precharged. Here, consider the case where clock K2 is at L level and K1 (K1 ') is at H level. First, when the input data D is at the H level, the node 14 is destroyed and the latch 19 is latched with the H level data. When the input data D is at the L level, the latch 19 is latched at the L level while the node 14 holds the H level.

When a clock is supplied to the dynamic circuit 102, a circuit malfunction may occur depending on the type of clock skew. For example, when clocks K1 (K1 ') and K2 with a skew shown in FIG. 3 are supplied to the dynamic circuit 102, the clocks overlap (hatched portions in FIG. 3).
Causes malfunction. This is because the output latch 19
This is because the precharging of the node 14 is performed in the latter half of the data sampling, and erroneous data is latched.

This problem can be solved by using a dynamic circuit as shown in FIG.
This can be avoided by supplying the clock to 102 from clock circuit 101 of the present invention.

Through the clock circuit 101 of the present invention, as is apparent from the timing chart of FIG. 5, in the latter half of sampling of the latch 19 (when K1 is at the H level), the connection line 4
This is because the change in K2 is suppressed and the level does not change from the L level to the H level.

FIG. 6 shows an example in which the present invention is applied to a clock distribution system of a microprocessor. In the figure, reference numerals 111 and 112 denote non-overlapping clocks, which are supplied to clock drivers 116, 117 and 118. Of these, 116 and 118 are clock drivers employing the clock circuit of the present invention,
A skew-corrected clock signal is output in pairs of 6 and 127 and 128 and 129. Reference numeral 117 denotes a clock driver without skew correction. Reference numerals 119 and 125 denote precharge means for precharging the dynamic type data buses 113, 114 and 115, respectively. The data on the data buses 113 and 114 is taken into the input latches 120 and 121 and sent to the calculating means 122. The data input to the arithmetic means 122 is subjected to arithmetic processing,
It is stored in the output latch 123. The stored data is output from the output means 124 to the data bus 115.

Here, the clock circuit of the present invention is adopted for the clock driver 116 because the precharge means 119 and the input latch 1 are used.
This is because a data input latch fetching error occurs due to a clock skew similar to that shown in FIG. On the other hand, the clock circuit of the present invention is employed for the clock driver 118 because an output error of the output result to the bus 115 occurs between the precharge means 125 and the output means 124. In FIG. 6, a dotted line indicates a clock signal supply path, and a solid line indicates a data transmission path.

According to these embodiments, it is possible to avoid the malfunction of the circuit due to the clock skew while minimizing the logic change.

In addition, the clock circuit of the present invention has the flexibility to be adopted only in the portion where skew correction is required. Therefore, the clock circuit which pursues the synchronization timing order relationship severely and the synchronization timing order relationship And a clock driver which does not pursue the severeness as much as those clock circuits can be mixed well and each can operate stably.

In the above embodiment, an example was shown in which the output of one clock driver was supplied to one input of the other clock driver, but the output of the other clock driver was also supplied to one input of one clock driver. May be supplied. That is, it is also possible to output own clock after the output of each clock signal.

〔The invention's effect〕

According to the present invention, even when the clocks are overlapped by the clock skew, it is possible to remove only the overlaps of the clocks which cause the malfunction of the circuit supplied with the clocks while minimizing the logic change.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a clock circuit according to the present invention, FIG. 2 is a diagram showing an example of a clock synchronous logic circuit,
FIG. 3 is a timing chart when the circuit of FIG. 2 malfunctions, FIG. 4 is a diagram showing a clock synchronous logic circuit to which the clock circuit of the present invention is added to avoid malfunction, and FIG. 5 is a timing chart of the operation. FIG. 6 is a block diagram showing an embodiment in which the present invention is applied to a microprocessor. 1 ... clock driver, 2 ... clock driver, 3
…… Control signal, 4… Connection line, 11… PMOS, 12,13 …… N
MOS, 14 ... dynamic node, 19 ... output latch, 1
01 …… Clock circuit, 102 …… Dynamic circuit, 111,1
12 Non-overlapping two-phase clock signal, 113, 114, 115 Data bus, 116, 118 Clock circuit (driver) of the present invention, 117 Clock driver without correction, 119 Precharge circuit, 120, 121 Input latch, 122 ... Arithmetic means, 123... Output latch, 124... Output means, 125... Precharge circuit, 126 and 127, 128 and 129.

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-60-146315 (JP, A) JP-A-60-156127 (JP, A) JP-A-61-264817 (JP, A)

Claims (2)

(57) [Claims] 1. A multi-input clock driver having a first clock input and a multi-input clock driver having a second clock input. A clock circuit, wherein at least one output of the two multi-input clock drivers is directly connected to one input of the other multi-input clock driver. 2. A multi-input clock driver having a first clock input and a multi-input clock driver having a second clock input, wherein the outputs of both multi-input clock drivers are clock signals of a clock synchronous logic circuit of the next stage. A microprocessor including a clock circuit, wherein at least one output of only the two multi-input clock drivers that outputs a clock signal to the next-stage clock synchronous logic circuit is directly input to one input of the other multi-input clock driver. A microprocessor connected thereto.