JPH034592A - Manufacture of ceramic board - Google Patents

Abstract

PURPOSE:To surely join a conductive layer and a via together by a method wherein the via is made to protrude once from a ceramic board, the surface of the board is covered with an insulating layer, and then the insulating layer is removed to make the end of the via exposed again. CONSTITUTION:The surface of a ceramic board 1 is etched, a via 2 formed in the board 1 is made to protrude from an etched surface 3, and then an organic insulating layer 4 is deposited on the surface 3 covering the protruded via 2. Then, the insulating layer 4 is partly removed to enable the via 2 to be exposed again, and a conductive layer 5 is laminated on an exposed part 2A. Therefore, even if deep voids occur to the via 2, the voids are eliminated by the lamination of the insulating layer 4, so that voids 16A and 16B can be thoroughly eliminated without much polishing and the via 2 and the conductive layer 5 are surely joined together, and a ceramic board of this design can be improved in quality.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a ceramic substrate, in which a conductive layer is laminated to a via exposed on the surface of the ceramic substrate.

When forming a surface pattern on the surface of a ceramic substrate, manufacturing is performed, for example, as shown in the diagram for explaining the formation of the surface pattern in FIG. 4.

As shown in FIG. 4(a), for a ceramic substrate 1 configured with an inner layer pattern 11 embedded in a ceramic material IO and a via 2 bonded to the inner layer pattern 11, As shown in (b), a conductive layer 5 is formed by laminating a conductive material on the surface IA, and then, as shown in (c), a hole 1 is formed through which a predetermined portion of the conductive layer 5 is exposed.
4, the insulating layer 12 is laminated, and the surface pattern 15 is stretched on the upper layer of the insulating layer 12, and the conductive layer 5
A surface pattern 15 connected to the inner layer pattern 11 via the vias 2 is formed.

However, in forming such a surface pattern 15, in reality, as shown in the side cross-sectional view of the via portion in FIG. A void 16A shown in (al) or a recess 16B shown in (bl) is generated due to insufficient filling of the metal material or variations in packing density.

Therefore, if the void 16A is generated, the void 16A will be filled with gas etc. during the lamination of the conductive layer 5 shown in (a2), and the E "Blistering" as shown in the figure occurs, resulting in a poor connection between 72 and the conductive layer 5.

Further, if the recessed portion 16B is formed, the conductive layer 5 will break as shown at part F in the step of laminating the conductive layer 5 shown in (b2), and the conductive layer 5 will not be formed.

Therefore, when forming the surface pattern 15 on such a ceramic substrate tt1il, 1. exposed via 2
It is desired that the manufacturing process be such that voids 16A and recesses 16B are not formed in the exposed portions of the substrate.

[Prior Art] Conventionally, the manufacturing process has been carried out as shown in the conventional manufacturing process diagrams in FIGS. 3(a), 3(b), and 3(c).

As shown in FIG. 3(a), the surface IA of the ceramic substrate l where the vias 2 are exposed is processed by polishing, and the vias 2 are polished.
The voids 16A and the recesses 16B generated in the exposed portions are removed to form the polished surface 1B shown in FIG. Perform lamination.

Therefore, the surface IA of the ceramic substrate l is polished by a predetermined polishing amount S.
By polishing the voids 16A and recesses 16B,
was removed, and a conductive layer 5 was formed.

Therefore, in this case, the polishing allowance S due to polishing is (
As shown in a), the depth sl of the void 16A and the recess 1
It is necessary to make the depth larger than the depth S2 of 6B.

[Problem to be solved by the invention]

However, by setting such a polishing allowance S to be polished, it is actually difficult to estimate how deep the void 16A will be.

Further, if the polishing allowance S is small and the voids 16^ are not completely removed, the above-mentioned trouble will occur.

Therefore, in order to improve quality, a large polishing allowance S has to be set, which poses a problem in that it is difficult to control the thickness of the ceramic substrate 1.

Therefore, it is an object of the present invention to improve quality by reducing the polishing allowance for the ceramic substrate 1 as much as possible, and by ensuring that the vias and the conductive layer can be bonded reliably.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention.

As shown in FIG. 1, the etching step a involves protruding the vias 2 on the etched surface 3 of the ceramic substrate l, which is wet-etched or dry-etched on the surface side 3 of the ceramic substrate l having the exposed grooves 72; After the insulating layer lamination process in which the organic insulating layer 4 is laminated on the etched surface 3 so as to cover the etched surface 72, the organic insulating layer 4 is polished or plasma etched, and the via 2 is formed on the surface 4A of the organic insulating layer 4. The polishing step C for forming the exposed portion 2A and the conductive layer forming step d for laminating the conductive layer 5 on the exposed portion 2A are performed in this order.

By manufacturing using such a manufacturing method, the above-mentioned problems can be solved.

[Effect]

That is, wet etching or dry etching is performed on the surface of the ceramic substrate l to make the vias 2 formed on the ceramic substrate l protrude from the etched surface 3, and then an organic layer is etched on the etched surface 3 so as to cover the protruded vias 2. The insulating layer 4 is laminated, a part of the organic insulating layer 4 is removed by polishing or plasma etching, the via 2 is exposed again, and the conductive layer 5 is laminated on the exposed portion 2A. This is what I did.

Therefore, even if a deep void 168 is generated with respect to the via 2, the stacking of the organic insulating layer 4 causes the void 168 to
6A will be eliminated, and the void 16A and recess 16B can be completely removed without increasing the polishing allowance as in the conventional method. By minimizing the polishing allowance in the etching process, quality can be improved. can be improved.

〔Example〕

The present invention will be explained in detail below with reference to FIG.

FIGS. 2(a) to 2(e) are manufacturing process diagrams of an embodiment of the present invention. The same reference numerals indicate the same objects throughout the figures.

As shown in FIG. 2(a), the above-mentioned inner layer pattern 11
The surface IA of the ceramic substrate 1, which is formed so that the end face of the via 2 connected to the
Make A flat.

Next, as shown in (b), the surface IA is wet etched or dry etched to a predetermined thickness Sl.
An etching process is performed to remove the ceramic material.

The via 2 thus protrudes beyond the etched surface 3 formed by the removal of the ceramic material.

In this case, the etching process is actually FIP
By etching for about 40 minutes using a (hydrofluoric acid) solution, the protrusion amount (Sll) of via 2 was made to be about 30 μm.

Furthermore, as shown in (c), a thickness 51 is formed on the etched surface 3.
An insulating layer lamination process is performed in which two organic insulating layers 4 are laminated to cover the protruding vias 2.

In addition, in the step of laminating the insulating layer in this case, a polyimide resin material was actually applied to a thickness of 50 .mu.m (312) and cured by heating at about 300'C.

As shown in (d), the organic insulating layer 4 thus formed is etched by removing the organic insulating layer 4 by a predetermined thickness S13 from the laminated surface 4B by polishing or plasma etching, and exposing the end face of the via 2 again. Perform the process.

In this case, the etching process was actually performed by polishing to a thickness of about 25 μm (S13).

Via 2 re-exposed by such polishing has (a
) and a void 16A of depth S1 and depth S2 as shown in FIG.
Even if the recessed portions 16B are formed, these will be completely erased.

As shown in (e), a conductive layer forming process is performed to laminate the conductive layer 5 on the surface 4A having the exposed portion 2A where the end face of the via 2 is exposed by the etching process. 5 can be reliably connected to the via 2.

In this case, the conductive layer was actually formed by sputtering or plating with Pd, Cu, or the like.

Therefore, when manufactured in this way, the polishing allowance S that is actually removed by polishing or etching the ceramic substrate l is about 5 to 6 μm, and the voids 16A and the recesses 16B can be completely removed without setting a large polishing allowance S. can be lost.

〔Effect of the invention〕

As explained above, according to the present invention, the vias are made to protrude from the ceramic substrate, and then the vias are covered with a laminated insulating layer, and the end faces of the vias are exposed again by removing the insulating layer. It is possible to completely eliminate voids 16A and recesses 16B that occur in vias.

Therefore, the voids 16A and the recesses 16B can be eliminated without the need for extensive polishing of the ceramic substrate as in the conventional method, and the quality of the ceramic substrate can be improved, which has a great practical effect.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention. FIGS. 2(a) to 2(e) are manufacturing process diagrams of an embodiment of the present invention. FIGS. 3(a), 3(b), and 3(c) are conventional manufacturing process diagrams. FIG. 4 is a process diagram for forming a surface pattern. FIG. 5 shows a side sectional view of the via portion. In the figure, l is a ceramic substrate and 2 is a via. 3 is an etched surface, and 4 is an organic insulating layer. 5 is a conductive layer, 2A is an exposed part. 4A shows the surface. Cα) (1)) σC) (d+ 8) Hon 2 Keko Rikoyori Ichiji moat one row of weir fence = S picture lol 2 Picture book Tamaki's IP, Rikarou Picture 1 picture Shibame no Shumini Process diagram (D) (b) +47jI-1-1C) (d) Machining diagram (α1) (bl) (α2) (b2) (σ3) of the via part Il! I 6 r cross section N side view

Claims (1)

[Claims] Ceramic substrate (1) with exposed vias (2)
an etching step (a) of protruding the via (2) on the etched surface (3) which has been subjected to wet etching or dry etching; and etching the etched surface (3) to cover the protruding via (2). An insulating layer lamination step (b) of laminating an organic insulating layer (4), and polishing or plasma etching the organic insulating layer (4).
A polishing step (c) of forming an exposed portion (2A) of the via (2) on the surface (4A) of 4), and a conductive layer forming step (d) of laminating a conductive layer (4) on the exposed portion (2A). A method for manufacturing a ceramic substrate, characterized in that it is manufactured by the following steps.