JPH0344333B2 - - Google Patents

Info

Publication number
JPH0344333B2
JPH0344333B2 JP58136021A JP13602183A JPH0344333B2 JP H0344333 B2 JPH0344333 B2 JP H0344333B2 JP 58136021 A JP58136021 A JP 58136021A JP 13602183 A JP13602183 A JP 13602183A JP H0344333 B2 JPH0344333 B2 JP H0344333B2
Authority
JP
Japan
Prior art keywords
circuit
input
output
data
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58136021A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5943430A (ja
Inventor
Debetsuson Pieeru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of JPS5943430A publication Critical patent/JPS5943430A/ja
Publication of JPH0344333B2 publication Critical patent/JPH0344333B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/285—Halt processor DMA

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Debugging And Monitoring (AREA)
JP58136021A 1982-07-27 1983-07-27 プログラム可能な停止符号の検出用システム Granted JPS5943430A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8213084 1982-07-27
FR8213084A FR2531244B1 (fr) 1982-07-27 1982-07-27 Systeme de detection de codes d'arret programmables dans un transfert de donnees intervenant entre une memoire locale d'un microprocesseur et un peripherique, dans un ensemble processeur utilisant un circuit d'acces direct a la memoire locale

Publications (2)

Publication Number Publication Date
JPS5943430A JPS5943430A (ja) 1984-03-10
JPH0344333B2 true JPH0344333B2 (en, 2012) 1991-07-05

Family

ID=9276351

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58136021A Granted JPS5943430A (ja) 1982-07-27 1983-07-27 プログラム可能な停止符号の検出用システム

Country Status (6)

Country Link
US (1) US4570218A (en, 2012)
EP (1) EP0100712B1 (en, 2012)
JP (1) JPS5943430A (en, 2012)
CA (1) CA1233261A (en, 2012)
DE (1) DE3370213D1 (en, 2012)
FR (1) FR2531244B1 (en, 2012)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4922416A (en) * 1984-12-14 1990-05-01 Alcatel Usa, Corp. Interface device end message storing with register and interrupt service registers for directing segmented message transfer between intelligent switch and microcomputer
JPH01241636A (ja) * 1988-03-17 1989-09-26 Internatl Business Mach Corp <Ibm> データ処理システム
JPH01163799U (en, 2012) * 1988-05-06 1989-11-15

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4879552A (en, 2012) * 1972-01-24 1973-10-25
US4075691A (en) * 1975-11-06 1978-02-21 Bunker Ramo Corporation Communication control unit
US4067059A (en) * 1976-01-29 1978-01-03 Sperry Rand Corporation Shared direct memory access controller
US4179732A (en) * 1977-06-10 1979-12-18 Dataproducts Corporation Microprogrammable processor control printer system
US4231087A (en) * 1978-10-18 1980-10-28 Bell Telephone Laboratories, Incorporated Microprocessor support system
JPS5790745A (en) * 1980-11-28 1982-06-05 Fujitsu Ltd Circuit controller

Also Published As

Publication number Publication date
EP0100712A1 (fr) 1984-02-15
JPS5943430A (ja) 1984-03-10
EP0100712B1 (fr) 1987-03-11
FR2531244B1 (fr) 1987-05-15
CA1233261A (en) 1988-02-23
DE3370213D1 (en) 1987-04-16
US4570218A (en) 1986-02-11
FR2531244A1 (fr) 1984-02-03

Similar Documents

Publication Publication Date Title
EP0303751B1 (en) Interface mechanism for controlling the exchange of information between two devices
EP0120889B1 (en) Direct memory access peripheral unit controller
CA1179069A (en) Data transmission apparatus for a multiprocessor system
US5890012A (en) System for programming peripheral with address and direction information and sending the information through data bus or control line when DMA controller asserts data knowledge line
US3953835A (en) Method and apparatus for adapting a data processing port to receive and transmit different frequency signals
US4485438A (en) High transfer rate between multi-processor units
EP0081961A2 (en) Synchronous data bus system with automatically variable data rate
EP0518488A1 (en) Bus interface and processing system
CA1299764C (en) Efficient interface for the main store of a data processing system
US4945473A (en) Communications controller interface
US5659720A (en) Computer control device for managing a timer array
US4564899A (en) I/O Channel bus
US5978865A (en) System for performing DMA transfers where an interrupt request signal is generated based on the value of the last of a plurality of data bits transmitted
JPS62115564A (ja) インタ−フエ−ス回路
KR920008448B1 (ko) 데이터 프로세서
US5828891A (en) Multilevel interrupt device
US5822548A (en) Programming interface for a universal asynchronous receiver/transmitter
US5930502A (en) Method for sharing a random-access memory between two asynchronous processors and electronic circuit for the implementation of this method
CA1208802A (en) Apparatus and method for direct memory to peripheral and peripheral to memory data transfers
US20020112105A1 (en) Method and apparatus for efficient messaging between memories across a PCI bus
US6223237B1 (en) Expandable communications bus
EP1255375B1 (en) Plural station memory data sharing system
IE970147A1 (en) Programmable read/write access signal and method therefor
US4032898A (en) Interface control unit for transferring sets of characters between a peripheral unit and a computer memory
JPH0344333B2 (en, 2012)