JPS5790745A - Circuit controller - Google Patents

Circuit controller

Info

Publication number
JPS5790745A
JPS5790745A JP55167866A JP16786680A JPS5790745A JP S5790745 A JPS5790745 A JP S5790745A JP 55167866 A JP55167866 A JP 55167866A JP 16786680 A JP16786680 A JP 16786680A JP S5790745 A JPS5790745 A JP S5790745A
Authority
JP
Japan
Prior art keywords
received data
memory
codes
stop
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55167866A
Other languages
Japanese (ja)
Inventor
Takao Tanaka
Hideaki Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55167866A priority Critical patent/JPS5790745A/en
Publication of JPS5790745A publication Critical patent/JPS5790745A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To facilitate the easy switching of the DMA transfer of received data, by installing a memory which stores plural pairs of codes showing both the start and stop codes of the received data to a circuit controller containing an ordinary DMA control circuit. CONSTITUTION:A code memory 23 which stores plural codes corresponding to the start and stop codes plus a comparator 24 which reads the start and stop codes out of the memory 23 and compares them with a received data are installed at a circuit control part 1 of a device containing an ordinary DMA control circuit. The received data is transferred directly to a main memory with no intervention of a CPU and in accordance with a coincident output obtained from the received data of the comparator 24 and the start code read out of the memory 23. At the same time, the stop code read out of the memory 23 is transferred to the main memory of the received data in accordance with the coincident output to the received data. In such way, the demarcation can be facilitated for the DMA transfer of the received data.
JP55167866A 1980-11-28 1980-11-28 Circuit controller Pending JPS5790745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55167866A JPS5790745A (en) 1980-11-28 1980-11-28 Circuit controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55167866A JPS5790745A (en) 1980-11-28 1980-11-28 Circuit controller

Publications (1)

Publication Number Publication Date
JPS5790745A true JPS5790745A (en) 1982-06-05

Family

ID=15857530

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55167866A Pending JPS5790745A (en) 1980-11-28 1980-11-28 Circuit controller

Country Status (1)

Country Link
JP (1) JPS5790745A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2531244A1 (en) * 1982-07-27 1984-02-03 Debesson Pierre SYSTEM FOR DETECTING STOP CODES PROGRAMMABLE IN A DATA TRANSFER BETWEEN A LOCAL MEMORY OF A MICROPROCESSOR AND A DEVICE, IN A PROCESSOR ASSEMBLY USING A LOCAL MEMORY DIRECT ACCESS CIRCUIT

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2531244A1 (en) * 1982-07-27 1984-02-03 Debesson Pierre SYSTEM FOR DETECTING STOP CODES PROGRAMMABLE IN A DATA TRANSFER BETWEEN A LOCAL MEMORY OF A MICROPROCESSOR AND A DEVICE, IN A PROCESSOR ASSEMBLY USING A LOCAL MEMORY DIRECT ACCESS CIRCUIT
US4570218A (en) * 1982-07-27 1986-02-11 Pierre Debesson System for the detection of programmable stop codes

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