JPH0341814A - Voltage level conversion circuit - Google Patents

Abstract

PURPOSE:To prevent production of latchup by turning on/off a 1st switching transistor(STR) with a pulse, clamping its output to a 2nd STR, and level- shifting a gate voltage of the 2nd STR with a resistor. CONSTITUTION:With pulses phi1, phi2 at both L, pMOSFETs Q1, Q3 are turned on and nMMOSFETs Q2, Q4 are turned off and a capacitor CE is charged. Then the pulse phi1 goes to H and a pulse phi2 goes to H after a time t, the nMMOSFETs Q2, Q4 are turned on and a charge is charged in a capacitor CL through the FETQ4 and the capacitor CE. Then a negative voltage in response to the charge stored in the capacitor CL is obtained from an output terminal as an output voltage VL. The pMOSFETQ31 is connected between the gate of the FETQ3 and ground in this way to clamp the gate of the FETQ3, latchup is not produced. Thus, the level shift in a negative power supply circuit is implemented stably without latchup.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a voltage level conversion circuit, and is suitable for application to, for example, a negative power supply circuit or a booster circuit.

[Summary of the invention]

The present invention charges the first capacitor by connecting a predetermined power supply to the first capacitor via a first switching transistor, and obtains a voltage from the first capacitor at a different level from that of the predetermined power supply. In the voltage level conversion circuit, the first switching transistor is turned on/off by applying a pulse to the gate of the first switching transistor via the second capacitor, and the first switching transistor is turned on/off. clamped by a second switching transistor connected between the gate and the predetermined power source, and the gate voltage of the second switching transistor is connected between the gate of the second switching transistor and the predetermined power source. The level is shifted by the resistor. by this,
Level shifting in the negative power supply circuit, booster circuit, etc. of the CMO3 can be performed stably without causing latch-up.

[Conventional technology]

FIGS. 4 and 5 each show an example of a conventional CMO3 level shift circuit. The conventional CMOS level shift circuits shown in FIGS. 4 and 5 are P-channel MO3
C consisting of FETTI and n-channel MO3FETT
It is composed of MO3, p-channel MO3FETT, and CMO3 which is separated from n-channel MO3FETT4.

Code 1. ．． 1. indicates an inverter. The CMOS level shift circuits shown in FIGS. 4 and 5 obtain an output voltage φ' having a different level from an input voltage φ.

Both of the CMOS level shift circuits shown in FIGS. 4 and 5 have low power consumption because no DC current flows, but the output voltage φ' is limited by the power supply voltage. That is, the CMOS level shift circuit shown in FIG. 4 cannot obtain an output voltage φ' higher than the power supply voltage of 15 V, and the CMOS level shift circuit shown in FIG. ′ cannot be obtained. For these reasons, the conventional CMOS level shift circuits shown in FIGS. 4 and 5 cannot be used for level shifting in negative power supply circuits, booster circuits, and the like.

FIG. 6 shows an example of a conventional CMO5 negative power supply circuit. 6th
As shown in the figure, in this conventional CMO3 negative power supply circuit, p channel MOS FET T s and n
CMO warns from channel MOS FET T b
3, and p-channel MOSFET T v and n
CMO consisting of channel MOS FET T s
3.

The symbols DI and Dz indicate clamp diodes.

Also, the code CII+C1i c,'+Ct''
indicates a capacitor.

In the CMO3 negative power supply circuit shown in FIG. 6, P channel MO3FET? The gate of the n-channel MO3FET is clamped with a diode D1, and the gate of the n-channel MO3FET is clamped with a diode D2. In this case, a pulse φ is applied to the gate of the p-channel MO3FET,
A capacitor C is connected to the gate of p-channel MO3FET T.
A pulse φ y is applied via 0. In addition, a pulse φ2 is applied to the gate of the n-channel MOS FET T b.
is added, and a capacitor CI! is added to the gate of the n-channel MO3FETTs. A pulse φ2 is applied via.

These pulses φ3. The waveform of φ2 is shown in FIG.

In the conventional CMO3 negative power supply circuit shown in FIG. 6, φ1. When both φ2 are at low level (L), p-channel MO3FETs and T? is on, n-channel MO3
FETs T,, T, are turned off, and at this time capacitor C
E' is charged. Next, first, φ, is at a high level ()(
), φ2 also becomes H after a time period of Δ. φ□ is H
, the n-channel MO3FET T,,T, turns on, and at this time, the n-channel MO3FET T,,T, turns on, and at this time, the n-channel MO3FET
Charge flows through O3FETTS to charge the capacitor CL. Then, a negative voltage corresponding to the amount of charge stored in the capacitor CL is obtained from the output terminal as an output voltage vL.

Now, let us consider a case where the output voltage vL is required to be about -9V, and when VE=10V and a pulse of 10V is applied to φ1, the gate of the p-channel MO3FET T is to be driven with 0 to -9V. However, since VL=Ov immediately after the power supply (2) is turned on, the gate voltage of this p-channel MO3FET must be level-shifted by the diode D shown in FIG.

Examples of structures of the above-mentioned clamp diodes D+ and Dz are shown in FIGS. 8 and 9, respectively. In FIG. 8, reference numeral 101 indicates a semiconductor substrate such as an n-type silicon (Si) substrate. In this semiconductor substrate 101, there is a p-well 1.
02 is formed, and in this p well 102, for example, a P'' type semiconductor region 103 and, for example, an n'' type semiconductor region 10 are formed.
4 is formed. And this P well 102 and n
A diode D1 is formed by the ゛-shaped semiconductor region 104. On the other hand, as shown in FIG. 9, a P well 105 is formed in this semiconductor substrate 101, and in this P well 105, for example, a p9 type semiconductor region 106 and, for example, an n' type semiconductor region 107 are formed. There is. A diode Dt is formed by this p-well 105 and the n-type semiconductor region 107.

[Problems to be Solved by the Invention] In the structural example of the diode D1 shown in FIG. A parasitic npn type bipolar transistor serving as a collector is formed. In this case, the diode D has a structure in which it is clamped at the base of this parasitic npn type bipolar transistor. Therefore, if the DC current amplification factor of this parasitic npn-type bipolar transistor is hFE, a current equal to hFE times the current required for clamping flows from the emitter of the n-type semiconductor region 104 to the semiconductor substrate as shown by the arrow. flows to However, when such a large current flows through the semiconductor substrate 101, there is a high possibility that latch-up will occur. That is, when the power is turned on, there is a high possibility that latch-up will occur due to the current required for clamping.

On the other hand, the diode D! shown in FIG. In the structure example shown in FIG. 1, an n-type semiconductor region 107, a p-well 105, and an n-type semiconductor substrate 101 are each etched to form a parasitic npn-type bipolar transistor having a base and a collector. In this case, the diode D2 has a structure in which it is clamped by the emitter of this parasitic npn type bipolar transistor, so that no current greater than the current required for this clamping flows through the semiconductor substrate 1. Therefore, the above-mentioned latch-up problem does not occur with respect to the diode Dt.

Therefore, an object of the present invention is to provide a voltage level conversion circuit that can stably perform level shifting in a CMO3 negative power supply circuit, booster circuit, etc. without causing latch-up.

[Means for Solving the Problems] In order to achieve the above object, the present invention is configured as follows.

In the invention of claim 1, the first capacitor t(cl) is charged by connecting a predetermined power supply to the first capacitor 1t(Ct) via the first switching transistor (Q3), and the first capacitor 1t(Ct) is charged. In a voltage level conversion circuit that obtains a voltage at a different level from a predetermined power supply from a power supply (CX), a second capacitor (C
, ) to turn on/off the first switching transistor (Q, ), and a second switching transistor (Q, ) connected between the gate of the first switching transistor (Q3) and a predetermined power supply. The gate voltage of the second switching transistor (Q,) is clamped by the transistor (Q, ,), and the gate voltage of the second switching transistor (Q,) is controlled by a resistor (rl) provided between the gate of the second switching transistor (Q,,) and a predetermined power supply. The level is shifted by

According to the second aspect of the invention, by connecting a predetermined power supply to the first capacitor (C1) via the first switching transistor (Q,), the first capacitor'! (c,), and obtains a voltage at a level different from a predetermined power source from a first capacitor (C4), a second capacitor is connected to the gate of the first switching transistor (Q3). 1t (
The first switching transistor (Q3) is turned on/off by applying a pulse through the first switching transistor (Q3), and the second switching transistor (Q3) connected between the gate of the first switching transistor (Q3) and a predetermined power source is A third switching transistor (Q2.) is clamped by the switching transistor (Q3.), and the second switching transistor (Q3.) is connected between the gate of the second switching transistor (Q,) and a predetermined power supply. )
is clamped by.

[Effect]

According to the invention of claim 1, the clamping is not performed with a diode as in the conventional voltage level conversion circuit, but the clamping is performed with the second switching transistor (Q, , ), so that the conventional voltage level conversion circuit does not perform clamping. This eliminates the latch-up problem caused by the formation of parasitic bipolar transistors in circuits. This allows stable level shifting in the negative power supply circuit, booster circuit, etc. of the CMO3 without causing latch-up.

According to the invention of claim 2, as in the invention of claim 1, since clamping is performed by the second switching transistor (Q□), the level shift in the negative power supply circuit of the CMO3, the booster circuit, etc. It can be performed stably without any occurrence.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. The following embodiments are all embodiments in which the present invention is applied to a CMO3 negative power supply circuit.

FIG. 1 shows a CMO3 negative power supply circuit according to Embodiment I of the present invention.

As shown in FIG. 1, in the CMO3 negative power supply circuit according to this embodiment I, P channel MO3FETQ and n
CMO consisting of channel M OS F E T Q t
3, and p-channel MOSFET Q s and n
CMO consisting of channel MOS FET Q a
3. Code c,,c,”,c,,c,”.

Ct and CL indicate capacitors. Here, p channel M
The source of the O3FETQ is connected to the power supply V, and the source of the n-channel MOS FETQt is grounded. Further, the source of the p-channel MO3FETQff is grounded, and the source of the n-channel MO3FETQ.

The source of is grounded via a capacitor CL.

In this embodiment I, p-channel MO3FF, TQ
p channel M between the gate of 3 and ground potential (GND)
O3FETQ31 is connected.

And this p-channel MO3FETQ! + clamps the gate of p-channel MOSFET Q3. Furthermore, this p-channel M OS F E
TQ.

A resistor r is provided between the gate of the p-channel MO3FETQ 3+ and GND, and the gate voltage of the p-channel MO3FETQ 3+ is level-shifted by the resistor r. On the other hand, n-channel M
An n-channel MO3FETQ is connected between the gate and output end of the OS FETQa. Then, the gate of n-channel MO3FETQ is clamped by this n-channel MO3FETQ,1. Further, a resistor r2 is provided between the gate and the output terminal of this n-channel MO3FETQ□, and the gate voltage of this n-channel M○S FET Q41 is level-shifted by this resistor r2.

In this Example I, p-channel MO3FE T
A pulse φ1 is applied to the gate of QI, and the p-channel M
Pulse φ1 is applied to the gate of O3FETQ3 via capacitor C1. In addition, n-channel MOS F
A pulse φ is applied to the gate of E T Q t, and a pulse φ2 is applied to the gate of the n-channel MO3FETQ4 via a capacitor C2. Also, p for clamp
Pulse φ2 is applied to the gate of channel MO3FETQ 31.
is added, n-channel MO3FETQ for clamping,
A pulse φ1 is applied to the gate of . Figure 2 shows these φ1゜φ1. φ2. An example of the waveform of φ2 is shown.

Next, the CM according to this embodiment I configured as described above
The operation of the O3 negative power supply circuit will be explained.

First, as shown in FIG. 2, φ1. When both φ2 are L, the P-channel MO5FETQ+ and Q3 are on, and the n-channel MO3FETQz and Q4 are off, and at this time, the capacitor C4 is charged.

Next, first, after φ1 becomes H, Δ is changed over time (for example, 10
n5ec~1 μsec) later, φ2 also becomes H. φ
2 becomes H, n-channel MOS FET Q
z, Q4 is turned on, and at this time, charge flows from the capacitor C2 through the n-channel MO3FETQ, and the capacitor Ct is charged. Then, a negative voltage corresponding to the amount of charge stored in the capacitor CL is obtained from the output terminal as an output voltage (2).

In this case, φ2 and φ1 each provide a p-channel MO
3FETQ31 and n-channel MO3FETQ0 are reset.

As described above, according to this embodiment I, the p-channel MO
This p-channel M O is connected between the gate of 3FETQ and GND.
Since the gate of S F E T Q s is clamped, a parasitic npn type bipolar transistor is not formed unlike the conventional CMO3 negative power supply circuit using the clamping diode D shown in FIG. Therefore, the latch-up problem caused by the formation of this parasitic npn type bipolar transistor is eliminated. This allows stable level shifting in the CMO3 negative power supply circuit without causing latch-up.

Figure 3 shows a CMO3 negative power supply circuit according to Embodiment 2 of the present invention.

As shown in FIG. 3, the CMO3 negative power supply circuit according to the embodiment (2) has p-channel MOSFET Qzz and n-channel transistors, respectively, in place of the resistors rl+r2 in the CMO3 negative power supply circuit according to the embodiment I shown in FIG. M.O.
It has the same configuration as the CMO3 negative power supply circuit according to Example I, except that 3FETQ, □ is used. Here, p-channel MO3FETQ3□ is p-channel M
It is connected between the gate of O3FETQ31 and GND. The gate of this p-channel MO3FETQ3g is connected to the gate of the p-channel MOSFETQs. Also, n-channel MQSFETQ
, 2 are connected between the gate and output terminal of the n-channel MO3FETQ41. And this n channel M
O3FETQ4! The gate of is an n-channel MO3FET
It is connected to the gate of Q.

According to this embodiment (2), the latch-up problem caused by the formation of a parasitic npn-type bipolar transistor as in the conventional CMO3 negative power supply circuit shown in FIG. 6 is eliminated, as is the case with embodiment I. Level shifting in the CMO3 negative power supply circuit can be performed stably without latch-up.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, Example 1 above. In II, the present invention is
Although the case where the present invention is applied to an MO3 negative power supply circuit has been described, the present invention can also be applied to, for example, a CMO3O booster circuit.

〔Effect of the invention〕

Since the present invention is configured as described above, it has the following effects.

According to the invention of claim 1.2, level shifting in an 0MO3 negative power supply circuit, a booster circuit, etc. can be performed stably without causing latch-up.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a CMO3 negative power supply circuit according to the embodiment (2) of the present invention, and FIG. 2 is a circuit diagram showing the pulse φ1. φ,. φ2. FIG. 3 is a circuit diagram showing a CMO3 negative power supply circuit according to the embodiment (2) of the present invention. FIGS. 4 and 5 are circuit diagrams showing a conventional CMOS level shift circuit, respectively. The figure is a circuit diagram showing a conventional CMO3jLt source circuit, and FIG. 7 is a circuit diagram showing the pulse φ1. A waveform diagram showing the waveform of φ2, and FIGS. 8 and 9 are cross-sectional views showing an example of the structure of a clamping diode in the CMO3 negative power supply circuit shown in FIG. 6, respectively. Explanation of main symbols in the drawings Q,,Q3. Q, , Q, □: p-channel MO3FET
, Q! , Qa, Qa1. Qat: n channel M
O3FET, r,, rt: resistance, Ct. Ct', C! , Cz”, CE, CL,: Capacitor.

Claims (1)

[Claims] 1. The first capacitor is charged by connecting a predetermined power source to the first capacitor via a first switching transistor, and the first capacitor charges the first capacitor at a level different from that of the predetermined power source. In a voltage level conversion circuit configured to obtain different voltages, the first switching transistor is turned on/off by applying a pulse to the gate of the first switching transistor via a second capacitor, and the first switching transistor is turned on/off. is clamped by a second switching transistor connected between the gate of the switching transistor and the predetermined power source, and the gate voltage of the second switching transistor is equal to the voltage between the gate of the second switching transistor and the predetermined power source. A voltage level conversion circuit characterized in that the level is shifted by a resistor provided between the circuits. 2. Charge the first capacitor by connecting a predetermined power source to the first capacitor via a first switching transistor, and obtain a voltage from the first capacitor at a different level from that of the predetermined power source. In the voltage level conversion circuit, the first switching transistor is turned on/off by applying a pulse to the gate of the first switching transistor via a second capacitor, and the gate of the first switching transistor and the gate of the first switching transistor are turned on and off. The second switching transistor is clamped by a second switching transistor connected between the predetermined power source, and the second switching transistor is a third switching transistor connected between the gate of the second switching transistor and the predetermined power source. A voltage level conversion circuit characterized by being clamped by a transistor.