JPH0340298A - Memory circuit - Google Patents

Abstract

PURPOSE:To always prevent recorded information from being destoryed and to eliminate necessity for refresh operation by setting and controlling the both ends of a ferroelectric capacitor in a memory cell, which stores the information, to the same potential. CONSTITUTION:When a first word line W1 of a first memory cell, which is accessed when data are written, is set to a high potential level and a transistor 1 is conducted, the signal of a phase reverse to that of the first word line W1 is applied to a second word line W2 and a transistor 8 is cut off. When a node 2 is made equal to the potential of a bit line, the polarizing direction of a ferroelectric capacitor 3 is made coincident with input data for a clock phi and the potential of the first word line W1 is lowered. then, the transistor 1 is cut off, the potential of the second word line W2 is increased and the transistor 8 is conducted. Accordingly, the both electrodes of the ferroelectric capacitor 3 become a ground potential and self polarization, which is once set, however, is not erased. Thus, a phenomenon to erase the data is prevented and while power is supplied, the necessity of refresh is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a memory circuit that can retain data without requiring refreshing.

(Prior Art) FIG. 3 is a diagram showing the structure of a memory cell of a conventional memory circuit using a ferroelectric material.

In such a circuit configuration, data is written by setting the potential of the bit line to a high or low potential according to the data to be stored, and then raising the potential of the word line to write the MO8.
Field effect transistor 1 is made conductive, node 2 is set to data potential, and a pulse is applied to clock φ. As a result, the direction of spontaneous polarization of the ferroelectric material 3 made of lead zirconate titanate, for example, which constitutes the capacitor is set, and data is written as shown in FIG. 4(a).

For example, if it is high potential data, node 2 or high potential,
When the clock φ is at the "0" level, a large electric field is applied to the ferroelectric material 3 in the direction of the arrow 4, causing spontaneous polarization.

On the other hand, regarding low potential data, when the node 2 is at a low potential and the clock φ is at a high potential, the strongly monotonous electric material 3 is polarized in the direction of the arrow 5. That is, the polarization direction of the arrow represents data, and since the polarization remains unchanged even when the power is turned off, nonvolatile data storage is possible.

To read the stored data, as shown in FIG. 4(b), the clock φ is set to a low potential, the bit line is placed in a floating state at a high potential, and the potential of the word line is raised to read out the memory cell to be accessed. transistor 1 is made conductive. This results in
Node 2 has a high potential, and an electric field is applied to ferroelectric material 3 in the direction of arrow 4.

Therefore, since no change occurs in the polarization state, the potential of the bit line does not change. However, if the polarization state was in the direction of arrow 5, the polarization is reversed and becomes in the direction of arrow 4. At this time, the potentials of node 2 and the bit line decrease by an amount corresponding to the polarization inversion. In FIG. 4(b), the amount of reversal is indicated by 6. The above change in the bit line is amplified by the sense amplifier 7 connected to the bit line and output.

Thereafter, the clock φ-“1” level is set to restore the polarization of the ferroelectric material 3 to perform rewriting.

(Problem to be solved by the invention) Even with ferroelectric memory, it is desirable that it does not require periodic refresh operations like dynamic memory, and data is not lost while the power is on. It is desired that

However, in the case of the above memory cell, there is a risk that data will be lost unless a refresh operation is performed.

That is, in FIG. 3, it is assumed that after the node 2 is set to a high potential and data is written, the clock φ remains at a low potential. The substrate node of transistor 1 is normally Vs
s, the node 2, which was at a high potential through the PN junction between the substrate and the source/drain, leaks and drops to a low potential. Therefore, if a write pulse from another memory cell is applied at this point, the electric field applied to the ferroelectric material will be opposite to that when writing high-potential data, resulting in polarization reversal and data loss. .

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a memory circuit equipped with ferroelectric memory cells that prevents the data loss phenomenon described above and does not require refreshing while power is being supplied.

(Means for Solving the Problems) In order to achieve the above object, in a memory circuit in which memory cells for storing information in ferroelectric capacitors formed by sandwiching a ferroelectric material between electrodes are arranged in a matrix,
The memory cell is configured to include a setting means for setting the electrodes of the ferroelectric capacitors of each of the memory cells to the same potential.

(Function) The setting means sets both ends of the ferroelectric capacitor to the same potential for memory cells that are not accessed when a write pulse is input to the memory cell, so that a reverse electric field is not applied. No data loss will occur.

(Embodiment) FIG. 1 is a diagram showing an embodiment of a memory circuit according to the present invention. The circuit shown in the figure shows the configuration of only the first and second memory cells to simplify the explanation.

Each memory cell has an additional M for short-circuiting the surface electrodes of each ferroelectric capacitor 3 with respect to the configuration shown in FIG.
OS transistors 8 are provided respectively.

The gate electrode G of the additional MOS transistor 8 is connected to the second word line W2, and the remaining electrodes are connected to both ends (plane electrodes) of the ferroelectric capacitor 3.

Since the polarities of the signals placed on the first word line WI and the second word line W2 are opposite to each other, when the MOS transistor 1 is on (conducting), the MOS transistor 8 is off (non-conducting).

Similarly, the remaining memory cells (not shown) including the second memory cell have similar configurations. In addition, the third
Similarly to the prior art memory circuit shown in the figure, 7 indicates a sense amplifier.

'Next, the operation of the memory circuit of the present invention will be explained with reference to FIG.

When writing data, the first word line W1 of the first memory cell to be accessed is brought to a high potential level, and the transistor 1 is made conductive. At this time, the transistor 8 is cut off because the second word line W2 receives a signal having the opposite potential to that of the first word line WI. When the potential of the node 2 becomes equal to the bit line potential, set the clock φ to the "11 level" to match the polarization direction of the ferroelectric capacitor 3 with the manual data, and then lower the potential of the first word line W. Transistor 1 is cut off, and the potential of second word line W2 is raised to make transistor 8 conductive.

As a result, the picture electrode of the ferroelectric capacitor 3 becomes at ground potential, but the spontaneous polarization set at -degrees does not disappear.

In reading data, the clock φ is set to "0" level (low potential), the bit line is set to a high potential, the potential of the first word line W1 is raised, and the memory cell to be accessed, for example, the transistor 1, is made conductive. Transistor 8 is made non-conductive. As a result, the potential of the node 2 becomes high, and the polarization data of the memory cell is read out as an output onto the bit line.

The data thus output is amplified by the sense amplifier 7 and output to the outside.

The data stored in each ferroelectric capacitor 3 of each memory cell will be lost when the polarization is reversed, but if the clock φ is set to the "1" level and rewritten when the bit line potential is set correctly, the data can be rewritten. good. Then transistor 1
is turned off, transistor 8 is turned on, and both ends of ferroelectric capacitor 3 are clamped to ground potential.

As described above, if the first memory cell is not accessed, the potential of the first word line WI will not reach a high level, so the transistor 8 will remain conductive, even if the clock φ-“1” level is reached. Both ends of the ferroelectric capacitor 3 are short-circuited and kept at the same potential, and never have opposite potentials. Therefore, no data loss condition occurs.

As a result, it becomes possible to provide a nonvolatile random access memory circuit that does not require a refresh operation. In addition,
The operation of the second memory cell is also exactly the same as that of the first memory cell, so a description thereof will be omitted.

In short, the present invention provides a second word line that provides a signal of opposite polarity to the signal on the first word line, and controls conduction of a second MOS transistor connected to the second word line. Both ends of the dielectric capacitor are set and maintained at the same potential.

Therefore, the data stored in the capacitor is protected from various noises, and a highly reliable ferroelectric memory circuit can be realized.

[Effects of the Invention] As explained above, according to the present invention, since both ends of the ferroelectric capacitor of the memory cell that stores information are controlled to be set to the same potential, destruction of stored information is always prevented. This makes it possible to provide a nonvolatile random access memory circuit using ferroelectric capacitors in memory cells that does not require a refresh operation.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory circuit according to the present invention, FIG. 2 is a timing chart explaining the operation of FIG. 1, FIG. 3 is a block diagram of a memory cell according to the prior art, and FIG. 4A and 4B are timing diagrams illustrating the operation of FIG. 3. FIG. 1...l MOS transistor of the first memory cell, 8
...additional MOS) transistor, 3...ferroelectric capacitor, 1-. 8-. 3''...corresponding components of the second memory cell, 2.2'...each node, 7...sense amplifier. a) (Reading operation timing) Figure 4 (b) Procedural amendment (voluntary) Commissioner of the Japan Patent Office July 11, 1999 2゜4゜ Person who amends the name of the invention Address related to the case (residence) Name (Name) Agent address memory circuit

Claims (2)

[Claims] (1) In a memory circuit in which memory cells are arranged in a matrix to store information in ferroelectric capacitors formed by sandwiching a ferroelectric material between electrodes, the electrodes of the ferroelectric capacitors of each memory cell are A memory circuit characterized by comprising a setting means for setting to the same potential. (2) The memory circuit according to claim 1, wherein the setting means is constituted by a field transistor controlled to short-circuit between the electrodes.