JPH0340129A - Floating point adder - Google Patents

Abstract

PURPOSE:To improve the processing efficiency of a floating point adder by performing a rounding process after deciding that the result of addition is already normalized even though the normalizing process is suppressed. CONSTITUTION:A setting means 15 and a normalization suppressing means 19 are provided. Then the result of addition is not normalized and undergoes directly a rounding process by the means 19. Thus the result of addition is equal to a normalized number S itself if the exponent value of the number S is equal to or larger than the exponent value of a normalized number A. Thus the least significant bit of the number S is substantially defined as a bit (i) and a rounding process is carried out. In this case, the bits equivalent (g), (r) and (k) are all equal to 0 and therefore the result of addition is equal to the number S itself. Then the actual weight of the least significant bit of a valid numeric character of the number S is equal to >=2 deg.. Thus it is decided that a rounding process is correctly carried out to the integer value since no valid numeric character having the weight smaller than 2 deg. exists. As a result, the process steps are decreased and the processing efficiency is improved for a floating point adder.

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding a floating-point adder used in a data processing device, the number of processing steps for rounding a normalized number to an integer value is reduced in an instruction to extract the integer part of a floating-point number. A floating-point adder that performs addition of floating-point numbers in accordance with the 11EIEB standard or compliant with the 11EIEB standard for the purpose of improving processing efficiency. A setting means that can be controlled by a microprogram to forcibly set the integer bit added to the upper part of the mantissa to "0" even if it is a normalized number, and a setting means that can be controlled by a microprogram to normalize the addition result before rounding. and an inhibiting means that can control inhibiting the normalization processing by a microprogram, and is configured to perform rounding processing on the assumption that the addition result has already been normalized even when the normalization processing is inhibited by the inhibiting means. .

(2) [Industrial Application Field] The present invention relates to a floating point adder used in a data processing device.

In a floating-point adder, rounding refers to the process of rounding up or truncating the significant digits below a certain bit position of the significant digits.

In the IBEB standard, there are rounding methods that allow you to specify the rounding direction using rounding modes such as rounding toward infinity, rounding toward zero, and rounding toward nearest value, and special rounding methods such as non-numbers (data that is not numerical) and infinity. A floating-point representation format that also represents operands has been proposed. Therefore, the number of data processing devices that handle rounding systems and floating point numbers that comply with this is increasing.

On the other hand, an instruction execution unit of a data processing device can execute a large number of instructions at high speed by controlling a general-purpose arithmetic unit such as an arithmetic logic unit (ALU) or a shifter using a microprogram.

Furthermore, since there is a strong demand for high-speed processing of scientific and technical calculations in large-sized computers, the speed of floating-point calculations (3) is increased by providing a dedicated arithmetic unit such as a floating-point adder. Dedicated arithmetic units are capable of higher-speed processing because they process specific instructions and data primarily through hardware control.

In this way, the instruction execution unit of a data processing device uses a general-purpose arithmetic unit to perform processing mainly under the control of a microprogram, and a dedicated arithmetic unit to perform processing mainly under hardware control. Generally, a method is used that is optimally used depending on the type and data.

[Conventional technology]

In a data processing device that uses a floating point number representation format compliant with the IEEE semi-standard, the floating point number χ has a 1-bit sign part S, m-bit exponent part E, and n-bits It is expressed in the mantissa.

The value of the exponent part E is obtained by adding a bias value to the actual exponent value, and 2(m-1) l is normally used as the bias value. The actual index value e is determined from (4) e=E−bias value.

The binary bit string representing the mantissa part F is f,, f2, 0. f.

Then, the binary floating point number X is given by the following equation.

X=(1)5XL'fl-f2,"',f
,,X2''Here, L is the most significant bit of the significant digits, and a floating point number where L=1 is called a normalized floating point number or a normalized number.

The maximum value (all bits are 1) and the minimum value (all bits are 0) of the exponent value E are non-numbers, infinite numbers, unnormalized numbers,
Reserved to represent data other than normalized numbers such as zero.

If the exponent part E is neither its maximum value nor its minimum value, it is a normalized number. In this way, whether it is a normalized number or not can be identified by the value of the exponent part, and since the value of n bits in a normalized number is always l, the n bits are not explicitly expressed. Therefore, in floating point arithmetic, when the operand data is a normalized number, n bits that are not explicitly expressed are added to the upper part of the mantissa (5) and processed.

The instruction to extract the integer part of a floating point number is an instruction that converts a floating point number into a floating point number having an integer value by rounding off the significant digits smaller than 2 degrees of the actual value represented by the floating point number.

As mentioned above, the rounding process is the process of rounding up or down the significant digits below a certain bit position of the significant digits (this bit is considered to be 1 bit). Here, the bit 1 bit lower than 1 bit is g bit,
If the further lower bits are r bits, and the logical sum of all bits lower than r bits is 2 bits, the rounding process is as follows.

■Rounding toward infinity If either g, r, or is 1 and the sign of the data is positive, round up; otherwise, round down.

- Rounding toward infinity If either g or r is 1 and the sign of the data is negative, round up; otherwise, round down (6).

■ Rounding toward zero If either g or l"+k is 1, round up; otherwise, round down.

■If g=1 in the direction of the latest value, and either r or k is 1, or g=l
, r=Q, ni=o, and if i=1, round up, otherwise round down.

FIG. 8 shows an example of the configuration of a floating point adder that performs addition of two floating point numbers specified by the IBEE standard. This circuit is controlled by a control circuit (not shown) and can output the results of addition and subtraction of two normalized floating point numbers in three machine cycles.

TI the first cycle of 3 machine cycles! Assuming that the second cycle is F2 and the third cycle is F3, the operations in each cycle are roughly as follows.

Here, Sl sign part El of operand 1: exponent part Fl of operand 1: mantissa part of operand 1 (7) Ll 1-bit integer part S2 added to the upper part of the mantissa part of operand 1; sign part of operand 2 F2: Exponent part of operand 2 F2: Mantissa part of operand 2 F2: 1-bit integer part added to the upper part of the mantissa part of operand 2 SR1: Register that holds the value of the sign part of operand 1 SR2: Significant part of operand 2 Register BXPR that holds the value of the sign part: Register FRI that holds the exponent part of the intermediate result
: Register that holds the first input of the addition/subtraction circuit PH2: Register S3 that holds the second input of the addition/subtraction circuit: Sign part of the calculation result F3: Exponent part of the calculation result F3: Mantissa part of the calculation result SAI: Digit alignment Shift amount of shifter 1 (8) SA2: Shift amount of digit alignment shifter 2 Also, the number of bits in the exponent part is 11, and the number of bits in the mantissa part is 5.
Set it to 2.

(1) Tl cycle (digit alignment processing) Sign parts SL and S2 of both operands are placed in registers SRI.
, stored in SR2. Further, the exponent comparison circuit 11 compares the exponent parts El and F2, and according to the result, if E1≧E2, El is used, and if El<F2, F2 is used.
is selected and stored in the exponent part holding register EXPR of the intermediate result, and the shift amount SAI, S to calculate the exponent difference between El and F2 and shift the digit alignment thick 16.17.
Generate 2 to. The digit alignment shift of the mantissa part is performed by shifting the mantissa part with the smaller exponent value to the right by the difference in exponents. Therefore, if E1≧E2, 5A1-exponential difference, 5A2=0, if El<F2, 5AIO1S
A2-index difference is output respectively.

The mantissa parts Fl and F2 of both operands are integer part addition circuit 1.
4.15, the upper 1-bit integer bit Ll, L2
are added and sent to the digit alignment shifters 16 and 17 as LFI and LP2, respectively. Digit alignment thick 16.17 shifts LFILF2 to the right according to the shift amount S by 1, SA2, and the part shifted to the right from the least significant bit position of the mantissa is the 2 bits lower than the least significant bit of the mantissa. Further, a total of three bits are added as one bit of the logical sum of all the lower bits and stored in the adder/subtracter circuit input registers FRI and PH1, respectively.

(2) F2 cycle (addition/subtraction and normalization processing) The addition/subtraction circuit 18 adds or subtracts the registers FR1 and PH2 and outputs the absolute value of the addition/subtraction result. As shown in FIG. 4, whether it is addition or subtraction is determined by a control circuit (not shown) depending on the signs of both operands. The sign part determination circuit 12 arithmetically determines the sign of the operation result based on the combination of both operands stored in the registers SRI and SR2, the type of instruction, and the addition/subtraction results of the addition/subtraction circuit, and stores it in the register SRI. As shown in Fig. 5, each bit of register FR1 is set from high order to x1 to
56, the absolute value output (XO) of the addition/subtraction circuit 18 becomes ZO to Z56. Here, ZO is the addition/subtraction circuit 18
This is the carry output generated from the most significant bit when addition is performed.

The normalization shift control circuit 19 generates a shift amount necessary to normalize the absolute value outputs 20-256 of the addition/subtraction circuit 18, and supplies it to the exponent correction circuit 13 and the normalization shifter 20.

Normalization is performed by right or left shifting so that the most significant "1" bit of ZO to Z56 comes to the 21st bit position. Since the right shift is performed only when ZO=1, the right shift amount is 1 at most.

The normalized thick outputs are assumed to be N1 to N56 corresponding to the bit positions Z1 to 256. However, the normalization shifter 20
If a right shift is performed in , N56 contains 2
The logical sum of 55 and Z56 is output.

N1 to N53 are stored in bit positions X1 to X53 of the FRI, and zeros are stored in X54 to X56.

The rounding decision circuit 21 decides whether to round up or discard the three bits N54 to N56, and if rounding up is selected, stores the king in the bit position of Y53 of FR2, Store zeros in other bits. Therefore, the rounding process determination circuit 21 determines the rounding process as described above by setting N53 to 1 bit, N54 to g bits, N55 to r bits, and N56 to 2 bits.

Further, the exponent correction circuit 13 corrects +1 per bit when a right shift is performed by normalization shift, and -1 per bit when a left shift is performed.
This is performed on the exponent part of the intermediate result held in PH, and the correction result is stored in IEXPR.

(3) T3 cycle (rounding process) The sign part of the intermediate result is stored in register SRI, the exponent part of the normalized intermediate result is stored in register BXPR, and the upper 53 bits (N1 to N53) of the normalized mantissa calculation result are stored in register SRI. ) is held in Regisc FRI.

Addition by rounding processing is performed by addition/subtraction circuit 18 between FRI and FR2.
This is done by adding . If rounding down is selected, FR2(12) is zero, so X1 to X53 of FRI is obtained as the addition result, and if rounding up is selected, Y53 of FR2 is 1. Therefore, FRI's X53
The result of adding 1 to the bit position is obtained. In other words,
A result is obtained by rounding the lower three bits of the normalized intermediate results N1 to N53.

The normalization shift control circuit 19 generates a shift It necessary to normalize the absolute value outputs 20-256 of the addition/subtraction circuit 18, and supplies it to the exponent correction circuit 13 and the normalization thick 20. In the case of ZO-1, normalization processing is performed by shifting one bit to the right, so the output of the exponent correction circuit 13 is the exponent part of the intermediate result held in the register EXPH plus ■, and the normalization The output of the shifter 20 is obtained by shifting ZO to Z56 one bit to the right. Z
When O=0, since Zl-1, the normalized shift amount is O.

Therefore, the output of the exponent correction circuit 13 becomes the exponent part of the intermediate result held in the register BXPR, and the output of the normalization shifter 20 becomes the values Z1 to Z56.

(13) Further, the sign part determining circuit (2) outputs the code part of the intermediate result held in the register SRI as the code part of the final result. Therefore, the sign part S3, exponent part E3, and mantissa part F3 of the final calculation result are the sign part determination circuit output, the exponent correction circuit output, and the normalization shifter output N2 to N5, respectively.
Obtained as 3.

[Problem to be solved by the invention]

Conventionally, in an instruction to extract the integer part of a floating-point number, the process of rounding a normalized number to an integer value is performed by repeating a conditional branch of the microprogram according to the value of gr/k, the sign of the data, and the rounding mode. Save,
There was a problem that the number of processing steps was large and efficiency was low.

SUMMARY OF THE INVENTION An object of the present invention is to provide a floating-point adder that can round floating-point numbers to integers at high speed.

[Means to solve the problem]

The present invention, as shown in the principle block diagram in FIG. For at least one of the operand data, even if the operand data is a normalized number, the mantissa part F2
The setting means 15 is controllable by a microprogram to forcibly set the integer bit L2 added to the upper part of The present invention is characterized in that it comprises a program-controllable inhibiting means 19, and even when the normalization processing is inhibited by the inhibiting means, rounding processing is performed on the assumption that the addition result has already been normalized.

[For production]

When two normalized numbers are added using a floating-point adder, the addition result is normally normalized, and the bit corresponding to the least significant bit position of the mantissa of the manually operand data is added to the normalized result by one bit. Rounding is performed as follows.

(15) Therefore, when rounding a certain normalized number S to an integer value, it has an exponent part such that the actual weight of the lowest bit position of the mantissa part is 2°, and the mantissa part is O. A positive normalized number A is added to the normalized number S. At this time, if the 1-bit 1 added to the mantissa of the normalized number A is forced to O by the setting means, all significant digits to the normalized number are O.
Therefore, the significant figures of the normalized number S are not affected by the addition.

Further, when the above-mentioned suppressing means causes the addition result to be rounded without being normalized, if the exponent value of the normalized number S is equal to or larger than the exponent value of the normalized number A, the addition result is not normalized. Since it becomes the number S itself, rounding processing is performed in which the least significant bit of the normalized number S is set as 1 bit. In this case, the bits corresponding to g, r, and k are all O, so the result of rounding is also the normalized number S itself, but is the exponent value of the normalized number S equal to the exponent value of the normalized number A? Large means that the actual weight of the least significant bit of the significant digits of the normalized number S is 2° or more, i.e. (16), that is, there is no significant digit with a weight less than 2°, so This means that rounding to an integer value was performed correctly.

On the other hand, if the exponent value of the normalized number S is smaller than the exponent value of the normalized number A, rounding is performed such that the bits with a weight of 2° in the significant figures of the normalized number S are treated as 1 bit. Therefore, rounding to an integer value can be performed correctly.

[Embodiment] FIG. 2 is a block diagram of an embodiment of the present invention. In the figure, the same components as in FIG. 8 are denoted by the same numbers.

In this embodiment, the integer part addition circuit 15 includes a setting means for forcibly setting the integer bit L2 added to the upper part of the mantissa part F2 of operand 2 to L2=0 under the control of a microprogram, and the normalization shift control circuit 19 includes If a normalization suppression signal NIS that can be controlled by a microprogram is added, and the normalization process is suppressed by the normalization suppression signal NIS, (17) the normalization shift control circuit 19 is related to the result of the addition/subtraction circuit ■8. By setting the normalization shift amount to O instead of 0, a suppressing means is provided to substantially suppress the normalization process.

Note that unless the microprogram enables the setting means and the inhibiting means, the floating point adder of this embodiment operates exactly the same as the floating point adder of FIG. 8.

To clarify the difference in operation between the floating point adder in FIG. 8 and the floating point adder according to the invention in FIG.
=4238888888888888 (sign part S 1
=O exponent part E 1 =423 mantissa part F1-888888
888888) Operand 2 =433000()0000[)000
0 (sign part 52 = O exponent part E 2 = 433 mantissa part F2
6 and 7 show examples of operations when two normalized floating point numbers such as 000000000000) are added using the floating point adder of FIG. 8 and the floating point addition of FIG. 2.

However, in FIG. 7, the setting means forcibly sets it to L2-0 in the T1 cycle, and the normalization process is suppressed by the inhibiting means in the T2 cycle (18).

Further, in the T3 cycle, the normalization inhibit signal NIS is turned off, and the result of the addition/subtraction circuit 18 is normalized by normal operation. Also, assume that the rounding mode is rounding towards the nearest value,
In the figure, the values of Regisc FR1 and FR2 are 16.
It is expressed in decimal numbers.

As can be seen from FIGS. 6 and 7, the results of the conventional floating-point adder and the calculation results of the floating-point adder according to the present invention are -4330001888, respectively.
888889 Result of floating point adder of the present invention-423
8888888890000. It should be noted that even in the floating point adder of the present invention, if the setting means and inhibiting means are not used, the calculation result will be the same as the conventional one. Therefore, it can be seen that the floating point adder of the present invention can output a special result as shown in FIG. 7 by using the setting means and inhibiting means.

Next, it will be shown that a special result by the floating point adder of the present invention is the result of an instruction to fetch the integer part of operand 1. The integer part extraction instruction is an instruction that converts a certain floating point number into a floating point number having an integer value by rounding off the significant digit part smaller than 2 degrees of the actual value represented by a certain floating point number.

Therefore, it can be obtained by finding the bit position where the actual weight of the significant digits of a given floating point number is 2 degrees, and rounding off the bits below that position.

In the floating point adder which is an embodiment of the present invention, a given floating point number is used as operand 1, and the mantissa part has an exponent part such that the actual weight of the least significant bit position of the mantissa part is 2 degrees. Add a floating point number whose all bits are O as operand 2, force the integer bits of operand 2 to 0 by the setting means in the addition process, and normalize the addition result before rounding. By inhibiting the processing by the inhibiting means, rounding is performed without normalizing the addition result, and by normalizing the rounding result, the result of taking out the integer part of operand 1 can be obtained. If the exponent part of operand 1 is greater than or equal to the exponent part of operand 2 (20), the mantissa part of operand 2 is shifted to the right by digit alignment shift and added, but the integer bits of operand 2 are set as above. Since the value is forced to 0 by means of the means, all significant digits of operand 2 become 0, so the addition result becomes operand 1 itself. Therefore, the addition results 254 to Z56 are all 0, and the final result obtained as a result of the rounding process is also the same as operand 1. If the exponent part of operand 1 is greater than or equal to the exponent part of operand 2, it means that the actual weight of the least significant bit of the mantissa part of operand 1 is 2 degrees or more, so the result of extracting the integer part of operand 1 is is operand 1 itself.

If the exponent part of operand 1 is smaller than the exponent part of operand 2, the integer bits and mantissa part of operand 1 are right-shifted and added, but since all the significant digits of operand 2 are O, the addition result is This is the result of the digit alignment shift of operand 1 itself. In the embodiment of the present invention, this addition result is rounded (21) without being normalized by the suppressing means. Therefore, since the actual weight of bit position 253 in the addition result is 2°, it is rounded to 254 to Z5.
Rounding 6 is nothing but rounding off the significant figures having a weight smaller than 2 degrees to an integer value. That is, by using the floating point adder according to the present invention, it is possible to process an instruction to fetch the integer part of a given floating point number. In the case of a floating point format as shown in Figure 3, the actual weight of the least significant bit position of the mantissa is 2°, which is the exponent part, and all bits of the mantissa part are 0.
The floating point number is 433000000000
It is 0000. Therefore, the result obtained in the operation example of FIG. 7 is the result of extracting the integer part of operand 1.

The actual exponent value represented by the exponent part 423 of the floating point number 4238888888888888 is 423-3FF = 24 (hexadecimal) -36 (1
0 base number), so the floating point number 4'2388888
88888888 represents the following binary number.

1, 10001000100010001000100
0100010001000100010001000
1000 x 236 (22) Rounding this to 1, 10001 by rounding the bits lower than the bit with a weight of 2° using nearest rounding mode
0001000100010001000↓00010
0010010000000000000000 X
2". If this is expressed in the floating point format of FIG. 3, it becomes 4238888888890000, which clearly matches the result obtained in FIG.

〔Effect of the invention〕

As described above, according to the present invention, in an instruction to extract the integer part of a floating point number, it is possible to reduce the number of processing steps for rounding a normalized number to an integer value and speed up the rounding process.

[Brief explanation of drawings]

Figure 1 is a diagram of the principle of the present invention; Figure 2 is a diagram of an embodiment of the present invention; Figure 3 is an example of a floating point data format; Figure 4 is an explanatory diagram of the processing of an addition/subtraction circuit; 6 is an explanatory diagram of the output of the adder/subtractor circuit, FIG. 6 is an explanatory diagram of the adder (23) result using a conventional floating-point adder, FIG. 7 is an explanatory diagram of the addition result by the floating-point adder of the present invention, and FIG. FIG. 1 is a configuration diagram of a conventional floating-point adder. (Explanation of symbols) 11...Exponent comparison circuit, 12...Sign part determination circuit, 13...Exponent correction circuit, 14, 15...Integer part addition circuit, 16.17...Digit alignment shifter , 18... Addition/subtraction circuit, 19... Normalization shift control circuit, 20... Normalization shifter, 21... Rounding process determination circuit, SRI, SR2, FRl, PH1, EXPR
···register. (24)

Claims (1)

[Claims] 1. A floating-point adder that performs addition of floating-point numbers in accordance with the IEEE standard or compliant therewith, with respect to at least one of two supplied operand data:
Even if the operand data is a normalized number, the mantissa (
A setting means (15) that can be controlled by a microprogram to forcibly set the integer bit (L2) added to the upper part of F2) to "0", and a normalization process of the addition result performed before rounding process. a suppression means (19) whose suppression can be controlled by a microprogram, and even if the normalization processing is suppressed by the suppression means, rounding processing is performed on the assumption that the addition result has already been normalized. Floating point adder.