JP2007073061A - Data processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multiply-add unit which can fast carry out a multiply-add operation instruction to normalize the computing result. <P>SOLUTION: This product-sum computing unit includes a digit alignment shift number and exponent generator unit, an addend digit alignment and sign adjusting unit, a multiplier array, a sticky-bit for addend lower digits generator unit, a most significant digit detector unit, a carry propagate adder, an exponent normalizing unit, an addend higher digit incrementer unit, a sticky-bit generator unit, a normalizing shifter, a positive number conversion and rounder unit, and an exponent correction unit. The multiplier array comprises an array of carry save adders. The most significant digit detector unit receives the two terms of carry and sum parts from the multiplier array, sequentially checks a digit pair of "0" to "1" at each corresponding digit position from the highest digit, and detects the most significant non-zero digit of the absolute values depending upon digit pair values (11, 00, 10, 01) from higher to lower digit position. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a product-sum operation unit in a data processing apparatus such as a microprocessor, and more particularly to a product-sum operation unit that executes a product-sum operation instruction that normalizes an operation result at high speed, and a data processing device that includes the product-sum operation unit. .

An example of executing a product-sum operation instruction that normalizes an operation result with a conventional microprocessor is PowerPC 603 (see, for example, Non-Patent Document 1).
The processor detects the most significant digit from the value after carry propagation addition. Further, when the addend protrudes above the product, the added addend is incremented by carry from the lower position with the digit position aligned with the lower portion.

The PowerPC 603 Microprocessor: A High Performance, Low Power, Superscalar RISC Microprocessor (Digest of papers SPRING COMPCON 94 pp300-306)

As described above, the processor of the above document performs the top detection based on the value obtained by carry propagation addition after carry propagation addition as described above, so the time required for the processing of carry propagation addition and top detection is the sum of these times. The product-sum operation instruction could not be executed at high speed.
Also, when the addend protrudes higher than the product, the extended addend is aligned with the lower part and is incremented by carry from the lower order, so the most significant digit is detected and normalized. The number is getting bigger.
An object of the present invention is to provide a product-sum operation unit that executes a product-sum operation instruction that normalizes an operation result at high speed, and a data processing device that includes the product-sum operation unit.

In order to achieve the above object, the present invention provides:
In a product-sum operation unit that performs carry propagation addition based on the operation output of the two terms of the multiplication array at the end of the product-sum operation, detects the highest non-zero digit of the absolute value of the operation result, and performs normalization,
An arithmetic output of the second term of the multiplication array is provided as an input, and a most significant digit detection circuit that detects the most significant digit that is not zero of the absolute value based on the arithmetic output of the two terms before carry propagation addition, The detection of the most significant digit is executed in parallel.
The most significant digit detection circuit may be a most significant digit detection circuit that allows an error of one digit in detection accuracy, and a means for correcting the normalized output based on the output of the most significant digit detection circuit by one digit is provided. I have to.
In addition, in a sum-of-products calculator that performs normalization, an addend digit-matching code matching unit that receives as input a digit-shift number and an addend mantissa part that are output from the digit-shift-number exponent generation output unit in the sum-of-products calculator Is configured to output an addend part that protrudes above the product, and is provided with means for processing the addend part without moving the most significant digit position. Several parts of processing and other parts of normalization are executed in parallel.
Further, any one of the product-sum calculators is provided in the data processing apparatus.

  According to the present invention, it is possible to detect the most significant digit that is not 0 of the absolute value of the value after carry propagation addition from the value before carry propagation addition, and to perform carry propagation addition and detection of the most significant digit in parallel. Become. Of the carry propagation addition and the detection of the most significant digit, the shorter required time is hidden in the other time. Further, it is only necessary to complete the increment of the addend that protrudes above the product by the end of normalization of the other part. Of the time from the generation of the carry from the lower order to the completion of the increment and the normalization time, the shorter one is hidden in the other time. As described above, the product-sum operation is speeded up.

  An embodiment of the present invention will be described with reference to the drawings.

Embodiments of the product-sum calculator according to the present invention will be described in detail with reference to the accompanying drawings.
In the following embodiments, components having the same function are denoted by the same reference numerals, and redundant description thereof is omitted.
The product-sum operation in the present invention is a floating point operation for calculating (multiplicand) × (multiplier) + (addend). Normalization means to set the decimal point to the right of the highest digit other than 0. For example, 0.001 × 22 is set to 1.000 × 2 to 1.
FIG. 1 is a block diagram of an embodiment of a multiply-accumulate arithmetic unit that speeds up a multiply-accumulate operation according to the present invention, and includes a digit shift number exponent generation unit 1, an addend digit alignment code match unit 2, and an addend lower sticky bit. Generation unit 3, multiplication array (product-sum operation array) 4, most significant digit detection unit 5, carry propagation adder 6, addend higher incrementer 7, exponent normalization unit 8, sticky bit generation unit 9, normalization shifter 10 , A positive number rounding unit 11 and an exponent correction unit 12.

Next, the configuration and operation of each unit in FIG. 1 will be described.
Digit shift number exponent generation unit 1 receives an addend, a multiplicand, and an exponent part of the multiplier, generates digit shift number D1 and exponent D2 of the product-sum operation result before normalization, and each addend digit The data is output to the matching code matching unit 2 and the exponent normalization unit 8.
The digit shift number is generated by subtracting the addend exponent from the sum of the exponent part of the multiplicand and the exponent part of the multiplier, that is, the exponent part of the product.
The exponent D2 output to the exponent normalization unit 8 is an addend exponent when the digit shift number is -3 or less, that is, when the most significant digit is always higher in the addend, and the digit shift number is -2. In the above case, that is, when the most significant digit is not necessarily higher in the addend, the exponent part of the product is selected.
The addend digit matching code matching unit 2 receives the addend mantissa part and the digit shift number D1, performs digit addition and sign matching, and sets the digit corresponding to the product to the multiplication array 4 with the addend middle. The portion that protrudes from the middle of the addend is output to the addend high incrementer 9 as the addend high, and the portion that protrudes from the low addend is output to the addend low sticky bit generation unit 3 as the addend low.
In the sign matching, when the sign of the addend and the sign of the product of the multiplier and multiplicand are compared and the signs are different from each other, in order to invert the addend part to 2's complement, Is inverted and 1 is added. However, only the reversal of 0 and 1 in the upper and middle addends is performed here. The upper part of the addend is not shifted to the lower side at the time of digit alignment so that the normalization shift in the normalization shifter 10 becomes unnecessary. When the upper part of the addend is not shifted to the lower side, the lowest digit position of the upper part of the addend changes according to the number of digits of the upper part of the addend. Therefore, the addend upper / lower order is also output to the addend upper incrementer 9. The addend high-order least significant is a value obtained by setting 1 at the least significant digit position of the addend high, and can be incremented by adding the high-order addend when added to the high-order addend.

The addend lower sticky bit generation unit 3 receives the addend lower order from the addend digit alignment code matching unit 2, generates an addend lower sticky bit D5, and outputs it to the carry propagation adder 6 and the sticky bit generation unit 9 To do.
The sticky bit is a value used when rounding the operation result. If the number of digits of the input data and the number of digits after rounding are n, the sticky bit is set when the value other than the upper n + 1 digits of the operation result before rounding is not 0. Is a bit.
When the lower part of the addend is not 0 digit, the carry-out by the product-sum operation is 1 digit at the maximum, so that the carry propagation adder 6 output has at least 2n-2 digits.
Note that a digit loss of two or more digits occurs when the digit shift number is -2 to 1, and at this time, the lower part of the addend is 0 digits. Therefore, since the addend low is always used only for sticky bit generation, the addend low value itself is not necessary, and may be left as an addend low sticky bit that becomes 1 when the addend low is not 0.
The addend digit matching code matching unit 2 does not perform addend lower sign matching, but it does not change whether the sign addition is performed or not, so the value of the addend lower sticky bit does not change.

The multiplication array 4 receives the multiplicand mantissa part, the multiplier mantissa part, and the addend middle order from the addend digit alignment code matching section 2, and carries the product of the multiplicand mantissa part and the multiplier mantissa part and the sum of the addend middle order as a carry. The calculation is performed using an array such as a storage adder or a redundant binary adder, and the result is output to the most significant digit detector 5 and the carry propagation adder 6.
The outputs of the multiplication array 4 are two values (two terms) that become the mantissa part of the product-sum operation result before normalization when added by the carry propagation adder 6. The two terms are, for example, a carry part and a sum part if the multiplication array is a carry save adder, and a positive part and a negative part if the multiplication array is a redundant binary adder.

The most significant digit detection unit 5 is not 0 out of the absolute value of the mantissa part of the product-sum operation result before normalization from the digitization shift number S1 from the digitization shift number exponent generation unit 1 and the output of the multiplication array 4 The most significant digit is detected, and based on the detection result, the exponent normalization unit 8 normalizes to the exponent normalization value D7, the sticky bit generation unit 9 to the sticky bit generation mask D8, and the normalization shifter 10 to normalize The shift number D9 is output. The most significant digit detection is performed as follows.
When the digit shift number is -3 or less, the most significant digit is higher in the addend. If the product and addend have the same sign, a carry of one digit may occur, and if the product has a different sign, a drop of one digit may occur.
Therefore, when the most significant digit is detected without allowing the use of the carry or the carry loss, the most significant digit can be determined by allowing an error of one digit to the upper side in the most significant digit detection. When the product and the addend have the same sign, the uppermost digit of the addend is one digit lower than the uppermost digit of the addend.
The exponent output by the digit shift number exponent generation unit 1 when the digit shift number is -3 or less is an addend exponent part. Therefore, the exponent normalization value is 0 because the most significant digit does not move on the basis of the addend if the product and the addend have the same sign, and is -1 if the product and the addend move one digit higher if the sign is different. Also, if the product and addend have the same sign, the normalized shift number can be shifted to the right by the left shift number of the addend at the time of the digit shift. Then, since it is shifted one digit higher than the case of the same sign, the value is obtained by adding 1 to the digit shift number and inverting the sign.
If the number of digits after rounding is n, the normalization shifter 10 extracts n + 2 digits from the uppermost digit of the most significant digit. Then, a sticky bit is generated from a lower digit than the extracted value. Therefore, the sticky bit generation mask may be set to all “1” s after the (n + 2) th digit starting from the least significant digit, that is, after the (n + 1) th digit lower digit of the most significant digit.

  When the digit shift number is -2 or more, the most significant non-zero digit is in the carry propagation adder 6 output or the lower two digits of the upper part of the addend. Detailed processing in this case will be described later. The exponent normalization value and the normalized shift number are determined by the difference between the most significant digit obtained and the decimal point position before normalization. As in the case described above, the sticky bit generation mask may be all set after the lowest n + 1 digit of the most significant digit.

Carry propagation adder 6 adds the two values of multiplication array 4 output to generate the mantissa part of the product-sum operation result before normalization, and outputs the result to sticky bit generation unit 9 and positive number rounding unit 11. At this time, when the product and the addend have different signs and the addend lower sticky bit is 0, 1 is added to the lowest order at the time of addition.
In the addend digit matching code matching unit 2, only the middle of the addend and the upper 0 and 1 of the addend are inverted in the sign inversion processing, so the sign inversion processing is completed by adding 1 to the lowest order.
The reason why 1 is added only when the addend lower sticky bit is 0 is as follows. If the lower order of the addend is 0 and 1 is inverted and 1 is added to the lowest order, the carry is transmitted to the middle of the addend when all the lower addends become 1 after the inversion, that is, before the inversion. This is the case when the lower addend is 0. This corresponds to the case where the addend lower sticky bit is 0. There is no need to add 1 if the carry is not transmitted.

The addend high incrementer 7 receives the addend high and the addend high least significant from the addend digit matching code matching unit 2 and the carry from the carry propagation adder 6, and when the carry is 1, the addend high When the carry is 0, the higher addend is selected.
Further, when the product and the addend have the same sign and different signs so that the extracted value of the normalized shifter 10 matches the digit position, the most significant digit of the addend is the most significant of the addend higher incrementer 7 output. The result is output to the normalization shifter 10 so as to be one digit lower and most significant digit.
When the digit shift number is −2 or more, the extracted value of the normalization shifter 10 and the digit position may not match in the above process. Therefore, when the information on the normalized shift number is obtained from the most significant digit detection unit 5 and the normalized shift numbers are 1 and 2, the most significant digit of the addend is the most significant digit of the addend significant incrementer 7 output. And one digit lower than the most significant digit. If the normalized shift number is other than the above, the addend higher incrementer 7 output is set to zero.

The exponent normalization unit 8 adds the exponent from the digit shift number exponent generation unit 1, that is, the exponent of the product-sum operation result before normalization and the exponent normalization value from the most significant digit detection unit 5, and the addition result is obtained. The normalized exponent D11 is output to the exponent correction unit 12.
The sticky bit generation unit 9 masks the mantissa part of the product-sum operation result before normalization from the carry propagation adder 6 with the mask from the most significant digit detection unit 5 to obtain a logical sum, and further performs the addend lower sticky bit. And outputs the result as a sticky bit to the positive number rounding unit 11.
The normalization shifter 10 normalizes the mantissa part of the product-sum operation result before normalization from the carry propagation adder 6 using the normalization shift number from the most significant digit detection part 5 and outputs the addend higher incrementer 7 output. And the result is output to the positive number rounding unit 11.
The positive number rounding unit 11 receives the output of the normalization shifter 10, performs positive numbering and rounding, and outputs the final normalized mantissa part of the product-sum operation result. The positive number processing is performed when the upper part of the addend is negative or the upper part of the addend is 0 and the output of the carry propagation adder 6 is negative. After 0 and 1 inversion, the sticky bit is set as in the case of the carry propagation adder 6. Add 1 only if 0.
The exponent correction unit 12 corrects the exponent part by the carry generated by the positive number and rounding, and outputs the exponent part of the final normalized product-sum operation result.

Next, the operation of the product-sum calculator will be described with reference to FIG. 1 to FIG. 3 using specific numerical values having a mantissa part of 4 bits.
Here, the case where the following formula (1) is calculated will be described with reference to FIGS. FIG. 2 is an operation explanatory diagram showing the flow of processing in each component of FIG. 1 when the equation (1) is calculated by the product-sum calculator of FIG.
(1.110 × 22) × (1.101 × 23) + (1.011 × 2 to 1) (1)
First, the digit shift number index generation unit 1 generates 2 + 3-(− 1) = 6 as the shift number (digit shift number) necessary for digit alignment between the product result and the addend.
In this case, since the digit shift number 6 is -2 or more, the sum of the exponents of the product part (2 + 3 = 5) and the sum of the exponents of the mantissa part 5 are selected as the exponents and output. (Step S1 in FIG. 2).
Next, in the addend digit matching code matching unit 2, the mantissa part 1.011 of the addend is shifted 6 digits to the right (lower side) in accordance with the digit shift number 6 obtained in step S1, and 0.000001010 is set. obtain.
First, the addend middle 00.000001 is obtained (8 digits are significant because it is a multiplication of 4 digits × 4 digits) (step S2).
Furthermore, the mantissa part 1.011 of the addend and the mask 0.000 (from the logical product that the mantissa part 1.011 is not over-exposed due to a 6-digit right shift and the mask bits are all 0) Get the top 0.000 (step S3),
Further, the mantissa part of the addend is 1.011 and 0.111 (the bit that the mantissa part 1.011 protrudes to the lower order by 6-digit right shift is the lower 3 bits of the mantissa part, so this lower 3 bits are valid. Therefore, the addend low-order 0011 is obtained from the logical product of (the mask bit is 0.111) (step S4).
Further, in this case, since the upper order is only 0, a carry from the lower order can be considered. Therefore, 1 is set to the left of the decimal point as the addend uppermost order to obtain 1.000 (step S5).

Next, the addend lower sticky bit generation unit 3 generates the addend lower sticky bit based on the addend lower, but in this case, the addend lower 0011 is not all 0, so 1 is generated as the addend lower sticky bit. (Step S6).
Further, since the product and the addend have the same sign (both +) (that is, the output of the exclusive EOR1 (hereinafter referred to as EOR) gate EOR1 in FIG. 2 is 0), the output of the AND gate AND1 is 0. The value 0 is given to the carry propagation adder 6. This is because it is not necessary to negate when the product and addend have the same sign. The gate EOR1 may be included in the digit shift number generation unit 1.
By these operations, the equation (1) becomes the following equation (2).
{(1.110 × 1.101 + addend middle) × 25} + addend lower sticky bit = {(1.110 × 1.101 + 00.000001) × 25} + addend lower sticky bit (2)
Next, in the multiplication array 4, the calculation within (1.110 × 1.101 + 00.000001) of the above equation (2) is performed. First, the multiplication part is added to the addition units (3-1) to (3-4). Correct as follows.

0.001110 (3-1)
+ 0.00000 ...... (3-2)
+ 0.1110 (3-3)
+ 1.110 (3-4)
+ 00.000001 (3-5)
The value (3-5) is an adding unit of the expression (2).
Here, the multiplication array 4 is, for example, a carry save adder. The carry save adder adds three numbers and outputs two numbers (two terms), a carry part and a sum part. The carry part is generated by setting 1 to the next digit when there are two or more 1s in each digit. The sum part is generated by setting 1 in each digit when there is one or three in each digit.
First, when the first three terms (3-1) to (3-3) are added, this part becomes two terms of the carry part (3-6) and the sum part (3-7).
0.010000 (3-6)
+ 0.110110 (3-7)
+ 1.110 (3-4)
+ 00.000001 (3-5)
It becomes.
Furthermore, when the first three terms (3-6), (3-7), (3-4) of this result are added, this part becomes two terms (3-8), (3-9),
0.11.00000 (3-8)
+ 1.010110 (3-9)
+ 00.000001 (3-5)
It becomes.
Furthermore, when these three terms (3-8), (3-9), and (3-5) are added,
010.000000 ...... (3-10)
+ 00.110111 ...... (3-11)
\ 4 + 2 digits /
It becomes. These two terms are the output of the multiplication array 4, the value (3-10) is the carry part, and (3-11) is the sum part (step S7).
Details of the operation of the most significant digit detector 5 when the digit shift number is −2 or more will be described later in detail with reference to FIGS.

The most significant digit detecting unit 5 is based on the output of the multiplication array 4 (formulas (3-10) and (3-11)) and the digitized shift number exponent generation unit 16 based on the digitized shift number and the exponent normalized value and the sticky bit. Generate mask and normalization shift number.
First, in the first step of FIG. 7 to be described later, the most significant digit “0” of the addend is added to the upper side of the output of the multiplication array 4, that is, the higher side of the sum of the multiplication array 4. At the same time, it is input to the most significant digit detector 5. Next, it is determined whether the product and the addend have the same sign or different signs.
As described above, since the product and the addend have the same sign (the output of the EOR gate EOR1 is 0), the process proceeds to the 3+ step and the output of the multiplication array 4 (expressions (3-10) and (3-11)) When a digit other than “00” is searched from the first digit “00” to the lower order, there is “10” in the second digit, and therefore this digit is the most significant digit.

Accordingly, since the most significant digit is the second digit to the left of the decimal point, 1 is output to the exponent normalization unit 8 as the exponent normalization value. (Step S8)
If the first digit, the second digit, the third digit,... Are on the left of the decimal point, the exponent normalized values are 0, 1, 2,.
On the other hand, when the first digit, the second digit, the third digit,... Are to the right of the decimal point, the exponent normalized values are -1, -2, -3,.
As a mask, “1” is set below the lowermost n + 1 (= 4 + 1 = 5th digit (fourth digit to the right of the decimal point)) of the most significant digit (second digit to the left of the decimal point) to obtain 0.0001111 (step S9).
Since the most significant digit is the second digit to the left of the decimal point, 1 is output to the normalization shifter 10 as the normalization shift number (step S10). When the digit shift number is -2 or more, the value of the normalized shift number is the same as the exponent normalized value.

If it is determined in the first step of FIG. 7 that the product result and the addend have the same sign, 0 is output to the EOR gate EOR2 and the positive number rounding unit 11 as a sign change signal.
Further, if it is determined in the first step that the product result and the addend are different signs, the process proceeds to the second step of FIG. 6 and is added when “00” is found in the lower digit in the second step. Since the result is negative, 0 is output as the sign inversion signal (step S22). Therefore, in this example, since it is the same sign, 0 is output as the sign inversion signal.
The positive rounding unit 11 inverts the sign of the output of the normalization shifter 10 when the sign inversion signal is 1.

The carry propagation adder 6 adds the carry part (3-10), adder part (3-11) of the output of the multiplication array 4 and the output of the AND gate AND1 to generate 10.1011111 (step S11). The data is output to the sticky bit generation unit 9 and the normalization shifter 10. Further, the carry 0 from the most significant value of the addition value 10.1011111 obtained in step S11 is output to the addend high incrementer 7 (step S12).
The addend high incrementer 7 inputs the addend high 0.000 and the addend high lowest 1.000 and the carry, and the sum 01 of the addend high 0.000 and the addend high lowest 1.000 according to the carry. Select one of .000 and the upper addend 0.000. Further, the selected output is shifted according to the output of the EOR gate EOR1 in FIG.
In this case, since the carry is 0, the upper addend is selected as 0.0000, and since the addend is the same sign as the product (that is, the output of the EOR gate EOR1 is 0), the addend is higher without performing the shift. 00.000 is output (step S13).
At this time, the expression (1) is expressed as the following expression (4) from the addition value obtained in step S11 and the index 5 obtained in step S1.
(10.101111 × 25) + addend lower sticky bit (4)
Next, the exponent normalization unit 8 adds the exponent 5 from the digit shift number exponent generation unit 1 and the exponent normalization value 1 from the most significant digit detection unit 5 to output 6 (step S14).

The sticky bit generation unit 9 masks the output 10.1011111 of the carry propagation adder 6 with the mask bit 00.000111 which is the output from the most significant digit detection unit 5 and takes the logical sum thereof (step S15). A value 1 obtained by logically summing the logical sum and 1 from the addend lower sticky bit generation unit is output (step S16).
In the normalization shifter 10, since the normalization shift number from the most significant digit detection unit 5 obtained in step S10 is 1, the output 10.1011111 of the carry propagation adder 6 is shifted one digit to the right and the upper 6 bits are changed. 01.0110 is extracted (step S17), and ORed with the output 0.0000 of the addend higher incrementer 7 to obtain 01.0110 and output (step S18).
At this time, the first equation (1) is (01.0110 × 26) + sticky bit (5)
It has become.
The positive rounding unit 11 operates differently depending on the rounding mode. Here, assuming that the value is rounded toward the closer or even direction, the output of the normalization shifter 10 is 01.0110, and the sticky bit from the sticky bit generation unit 9 is 1. Therefore, the output of the positive number rounding unit 11 Is 1.011 (step S19).
The exponent correction unit 12 outputs the output 6 of the exponent normalization unit 8 as it is because the positive digit rounding unit 11 does not need to correct the most significant digit position (step S20).
As a result, the calculation result is 1.011 × 26 (step S21).

Next, the case where the following formula (6) is calculated will be described with reference to FIGS.
FIG. 3 is an operation explanatory diagram showing the flow of calculation in each component of FIG. 1 when the equation (6) is calculated by the product-sum calculator of FIG.
(−1.110 × 2 to 1) × (1.101 × 2 to 2) + (1.011 × 21)
...... (6)
First, the digit shift number index generation unit 1 generates −1 + (− 2) −1 = −4 based on the index of the equation (6) as the digit shift number (step S30).
In this case, since the digit shift number −4 is −3 or less, the exponent of the addend part of the sum of the exponents of the product part (−1 + (− 2) = − 3) and the exponent 1 of the addend part is used as the exponent. 1 is selected and output (step S31 in FIG. 3).
Next, the mantissa part 1.011 of the addend is shifted 4 digits to the left (upper side) in accordance with the digit shift number -4 obtained in step S30 in the addend digit matching code matching unit 2 to 1011.0000000 Get.
First, an addend middle 10.000.000 is obtained (8 digits are significant because it is a multiplication of 4 digits × 4 digits) (step S32).
Here, since the result of the product of Equation (6) and the addend are different in sign, the output of the EOR gate EOR1 is 1, so that the addend middle 10.000.000 obtained in step S32 is inverted and 01.111111 is set. Obtained and output to the multiplication array 4 (step S33).
Further, an inverted version of the mantissa part 1.011 of the addend and 0.100 and mask 1.110 (the bits that the mantissa part 1.011 protrudes to the upper side due to 4-digit left shift are 3 bits, so the upper 3 bits are The addend upper 0.100 is obtained from the logical product with the mask bit of 1.110 to be valid) and output to the addend upper increment unit 7 (step S34).
Further, it is added from the logical product of the mantissa part 1.011 of the addend and the mask 0.000 (the mask bits are all 0 because there is no bit in which the mantissa part 1.011 protrudes to the lower order due to the 4-digit left shift). The number lower order 0.000 is obtained and output to the addend lower sticky bit generation unit 3 (step S35).
Furthermore, since the upper 3 bits are valid for the upper part of the addend as described above, the third bit from the upper part corresponds to the lowest order of the addend high. .010 is obtained and output to the addend upper increment unit 7 (step S36).
The 2's complement of the upper part of the addend is 10.100, but it is omitted because the most significant digit represents a sign and is not necessary for calculation.

Next, the addend lower sticky bit is generated in the addend lower sticky bit generation unit 3 based on the addend lower. In this case, the addend lower sticky is 0000 and all 0s, so 0 is generated as the addend lower sticky bit. To the sticky bit generation unit 9 (step S37).
Also, since the product and the addend have different signs (-and +) (ie, the output of the EOR gate EOR1 in FIG. 2 is 1) and the sticky bit is 0, the AND gate AND1 (the sticky bit is inverted) This value 1 is given to the carry propagation adder 6 (step S38). This is because it is necessary to negate when the product and the addend have different signs.

By these operations, the equation (6) becomes the following equation (7).
− (0.100 × 21) + {(1.110 × 1.101 + 01.111111) × 2-3} (7)
Next, in the multiplication array 4, the calculation within (1.110 × 1.101 + 01.111111) of the above equation (7) is performed. First, the multiplication part is changed to the addition unit, and three terms are used as in the above case. Addition is performed to obtain a carry part (8-1) and a sum part (8-2) as follows (step S39).
011.101100 (8-1)
+ 01.001001 (8-2)
The two terms are (8-1) and (8-2) are the outputs of the multiplication array 4.

The most significant digit detecting unit 5 is based on the output of the multiplication array 4 (formulas (8-1) and (8-2)) and the digitized shift number from the digitized shift number exponent generating unit 1 and the exponent normalized value, sticky Generates a mask for generating bits and a normalized shift number.
As described above, the number of digit shifts is -3 or less, and in this case, the product of the multiplier and multiplicand has a different sign, so the most significant digit is one digit lower than the most significant digit of the addend. It becomes. Further, since the product result and the addend have different signs, −1 is output to the exponent normalization unit 8 as the exponent normalization value (step S40).
As a mask, “0” is set to 00.011111 below the lowermost n + 1 (= 4 + 1 = 5) digit (second digit to the right of the decimal point) of the most significant digit (fourth digit to the left of the decimal point) ( Step S40).
The normalized shift number is a value 3 obtained by adding 1 to the digit shift number -4 and inverting the sign, and outputs this value to the normalized shifter 10 (step S41).
When the digit shift number is -3 or less, 0 is output as the sign inversion signal when the product result and the addend have the same sign, and 1 is output as the sign inversion signal when the sign is different. Therefore, in this case, 1 is output because of the different code (step S48).

  The carry propagation adder 6 adds the carry part (8-1), the adder part (8-2) of the output of the multiplication array 4 and the output 1 of the AND gate AND1 to generate 100.110110 (step S42). It outputs to the sticky bit generation unit 9 and the normalization shifter 10. Further, the carry 1 from the top of the added value 100.110110 obtained in step S42 is output to the addend higher incrementer 7 (step S43).

In the addend high incrementer 7, the addend high 0.100, the addend high lowest 0.010 and the carry 1 are input, and according to the carry, the addend high and the addend high lowest sum 0.0110 Select one of the higher addends 0.100.
In this case, the carry is 1, so the sum of 0.110 is selected, and the result of the product and the addend are different signs (that is, the output of the EOR gate EOR1 in FIG. 2 is 1). After performing (that is, performing digit alignment), the shifted value 01.100 is output to the normalization shifter 10 (step S44).

The exponent normalization unit 8 adds the exponent 1 from the digit shift number exponent generation unit 1 and the exponent normalization value −1 from the most significant digit detection unit 5 to output 0 (step S45).
At this time, the first expression is − {(01.10 × 20) + (10.110110 × 2 to 3)} (8)
It has become.
Next, the sticky bit generation unit 9 masks the output 00.1110110 of the carry propagation adder 6 with the mask bit 00.011111 which is the output from the most significant digit detection unit 5 to obtain the logical sum of them. A value 1 obtained by logically summing the logical sum and 0 from the addend lower sticky bit generation unit is output (step S46).
In the normalization shifter 10, since the normalized shift number is 3, the output of the carry propagation adder 6 output 0.110101 is shifted right by 3 digits to extract the upper 6 bits of 0.0001, and the output of the addend upper incrementer 7 is output. The logical sum of 01.100 is taken and output as 01.1001 (step S47).
At this time, the first equation (6) is − ((01.1001 × 20) + sticky bit) (9)
It has become.
In the positive number rounding unit 11, first, since the upper part of the addend is negative, the output 01.1001 of the normalization shifter 10 is used for positive number in response to the sign inversion signal 1 from the most significant digit detection unit 5. Is inverted to 0.11010 (step S49).
Since the sticky bit is not 0, it is not necessary to add 1 to make it positive. Further, the most significant digit position is corrected to be normalized to be 1.00110 (step S50).
If rounding is performed in the direction closer to the value or in the even direction, the sticky bit is 1, and therefore the output of the rounding unit 11 is 1.010 (step S51).
Since the exponent correction unit 12 corrects one digit by the positive number rounding unit 11, 1 is added to the output 0 of the exponent normalization unit 8 to output 1 (step S52).
As a result, the final calculation result is 1.010 × 21 (step S53).

  Thus, in this example, when the addend is larger than the product, the upper part of the addend that protrudes higher than the product is processed without moving the most significant digit, and the addend and product other than the protruded part are multiplied. The final product-sum operation result is obtained by adding the normalized product-sum operation result and the final sum. Accordingly, normalization of the upper part of the addend that protrudes above the product is not required, so that the product-sum operation is speeded up.

Here, the most significant digit detection unit 5 obtains the most significant digit that is not 0 among the absolute values of the mantissa part of the product-sum operation result before normalization from the two terms output from the multiplication array 4 in FIG. This will be described with reference to a flowchart.
First, in step 401, it is determined whether the number of digit shifts is −3 or less or −2 or more. If it is −2 or more, the processing of FIGS. 5 to 7 (processing of FIG. 7 in this embodiment) is performed.
On the other hand, if the digit shift number is -3 or less, the process proceeds to step 402, where it is determined whether the product of the multiplier and multiplicand and the addend are different signs or signs.
If it is determined that the sign is the same, the most significant digit in the addend is determined to be the most significant digit that is not 0 among the absolute values of the mantissa part of the product-sum operation result before normalization (step 403).
On the other hand, when it is determined that the sign is different, the digit one digit lower than the most significant digit in the addend is determined to be the most significant digit that is not 0 in the absolute value of the mantissa part of the product-sum operation result before normalization. (Step 404).

Next, in the most significant digit detection unit 5 when the digit shift number is −2 or more, the absolute value of the mantissa part of the product-sum operation result before normalization is calculated from the two terms output from the multiplication array 4. A process for obtaining the highest digit other than 0 without error will be described.
First, in the most significant digit detecting unit 5, a method of generally giving an input of 2's complement expression to the adder of the detecting unit 5 and obtaining the most significant non-zero digit of the addition result without error will be described. Next, a case will be described in which this process is simplified by recognizing an error of one digit, and finally applied to the most significant digit detector 5.
FIG. 5 shows a process for obtaining the highest non-zero digit from the absolute value of the addition result from the input to the adder without error.
When the addition result is positive, since the addition result is an absolute value as it is, the most significant digit other than 0 may be obtained. On the other hand, when the addition result is negative, the addition result is inverted by 0 and 1 and 1 is added to obtain an absolute value. At this time, normally, the first 0 digit as viewed from the most significant digit is the most significant digit that is not 0 in absolute value. However, if the addition result is all 1s from the most significant to the middle and all the remaining are 0s, the carry is transmitted when 1 is added after reversing 0, so that the first digit higher than the first 0 is seen from the most significant. The most significant digit that is not zero. Based on this, the process is as follows.

The first and second steps are positive / negative check, the third step is the search for the most significant digit, the fourth step is the correction of the highest digit by the presence / absence of a carry, and the fifth step is the presence / absence of a carry when a negative number is converted to a positive number The most significant digit is corrected.
First, in the first step, the corresponding digits of the carry part and the sum part, which are the outputs of the two terms of the multiplication array 4, first, the bit pair of the most significant digit, that is, the value of the input 2 bits is checked. In the case of “00” or “11”, the second step is skipped and the third step is performed. If “01” or “10”, the second step is performed.
In the second step, the digit whose input 2-bit value is “00” or “11” is searched from the next digit toward the lower order. If it cannot be found, it corresponds to (11) in FIG. 5 and the addition result is all 1 or -1, so the highest digit that is not 0 is the lowest digit.
The third step is divided into two types according to the results of the first and second steps.
One is the case where the value of the input 2 bits of the most significant digit is “11” in the first step or “00” is found in the second step. Since the addition result in this case is negative, the third step is performed. The other is the case where the value of the input 2 bits of the most significant digit is “00” in the first step and “11” is found in the second step. Since the addition result in this case is positive, the third + step is performed.
In the third step, the input 2-bit value is searched for a digit other than “11” from the next digit to the lower order. If not found, it corresponds to (6) in FIG. 5 and the addition result is −2, so the highest digit that is not 0 is one digit higher than the lowest digit. If “01” or “10” is found, the fourth digit is performed because the highest digit that is not 0 moves by one depending on the presence / absence of carry from the lower order. If “00” is found, Step 5-B is performed.
In the third + step, a digit whose value of input 2 bits is other than “00” is searched from the next digit toward the lower order. If not found, it corresponds to (10) in FIG. 5 and the addition result is 0, so there is no non-zero most significant digit. If “01” or “10” is found, the 4th step is performed because the most significant digit that is not 0 moves 1 digit depending on whether there is a carry from the lower order. When “11” is found, it corresponds to (9) in FIG. 5, and a carry occurs in this digit and the upper digit of 1 is 1, so the upper digit of this digit is the highest digit other than 0.
In the fourth step, from the next digit toward the lower order, a digit whose input 2-bit value is “00” or “11” is searched. If “11” is found, Step 5-A is performed. When “00” is found or not found, it corresponds to (3) in FIG. 5 and no carry occurs, so that the first digit higher than the digit found in the third step is the highest digit other than 0.
In the 4th + step, from the next digit, the input 2-bit value is searched for a digit whose value is “00” or “11”. When “11” is found, it corresponds to (8) in FIG. 5, and the carry is transmitted from this digit to the digit one digit higher in the third + step, and the digit one digit higher in the third + step is found. The most significant digit that is not zero. If “00” is found or cannot be found, it corresponds to (7) in FIG. 5 and no carry occurs, so the digit found in the third + step is the highest digit other than 0.
In step 5-A, a digit whose input 2-bit value is other than “00” is searched from the next digit toward the lower order. If found, it corresponds to (1) in Fig. 5 and the carry is transmitted from the digit found in the 4-step to the digit one digit higher in the 3-step, and the digit found in the 3-step is The most significant digit that is not zero. If it is not found, it corresponds to (2) in FIG. 5, and if 1 is reversed and added to 1 and carry is further transmitted, the carry is transmitted. is there.
In step 5-B, the input 2-bit value is searched for a digit other than “00” from the next digit downward. When found, it corresponds to (4) in FIG. 5, and the highest digit that is one digit higher than the digit found in the 3-step is the non-zero digit. If it is not found, it corresponds to (5) in FIG. 5, and if 1 is inverted and 0 is added, carry is transmitted. Therefore, the second digit higher than the digit found in 3-step is the highest digit other than 0. .
The above is the processing for obtaining the most significant digit other than 0 as the absolute value of the addition result from the adder input.

Next, the above process will be described using specific numerical values of 4 bits.
Since there are 11 cases in this processing as shown in FIG. 5, each case will be described.
If the adder inputs are 1011 and 1110, the most significant digit is "11" in the first step, so the third step is performed next. Since “01” is found in the second digit from the higher order, the fourth step is performed next. Since “11” is found in the next digit, the 5-A step is performed next. Since the next digit other than “00” is found, it corresponds to (1), and the highest digit that is not 0 is the second digit. When it is actually added and the sign is inverted, 0111 is obtained and a correct result is obtained.
If the adder inputs are 1101 and 1111, the most significant digit is “11” in the first step, so the third step is performed next. Since “01” is found in the third digit from the upper order, the fourth step is performed next. Since “11” is found in the next digit, the 5-A step is performed next. Since it has already reached the lowest order and cannot be found, it corresponds to (2), and the highest digit that is not 0 is the second digit. When it is actually added and the sign is inverted, 0100 is obtained and a correct result is obtained.
If the adder inputs are 0010 and 1000, the most significant digit is “01” in the first step, so the second step is performed next. Since “00” is found in the next digit, the third step is performed. Since “10” is found in the third digit from the upper order, the fourth step is performed next. Since “00” is found in the next digit, it corresponds to (3), and the most significant digit which is not 0 is the second digit. When it is actually added and the sign is inverted, 0110 is obtained and a correct result is obtained.
If the adder inputs are 1000 and 0001, the most significant digit is “10” in the first step, so the second step is performed next. Since “00” is found in the next digit, the third step is performed. Since “00” is found in the third digit from the higher order, the 5-B step is performed next. Since other than “00” is found in the next digit, it corresponds to (4), and the highest digit which is not 0 is the second digit. When it is actually added and the sign is inverted, 0111 is obtained and a correct result is obtained.
If the adder inputs are 1100 and 1100, the most significant digit is “11” in the first step, so the third step is performed. Since “00” is found in the third digit from the upper order, Step 5-B is performed. Since nothing other than “00” is found, this corresponds to (5), and the most significant digit that is not 0 is the first digit. When it is actually added and the sign is inverted, it becomes 1000 and a correct result is obtained.
If the adder inputs are 0101 and 1001, the most significant digit is “01” in the first step, so the second step is performed next. Since “00” is found in the next digit, the third step is performed. Since a value other than “11” is not found, it corresponds to (6) and the most significant digit that is not 0 is the third digit. When it is actually added and the sign is inverted, 0010 is obtained and a correct result is obtained.
If the adder inputs are 0110 and 1101, the most significant digit is “01” in the first step, so the second step is performed next. Since “11” is found in the next digit, the third + step is performed. Since “10” is found in the third digit from the upper order, the 4th + step is performed next. Since neither “00” nor “11” is found, this corresponds to (7), and the most significant digit that is not 0 is the third digit. When actually added, 0011 is obtained and a correct result is obtained.
If the adder inputs are 0011 and 0101, the most significant digit is “00” in the first step, so the third + step is performed next. Since “01” is found in the second digit from the upper order, the 4th + step is performed next. Since “11” is also found in the next next digit, it corresponds to (8), and the most significant digit which is not 0 is the first digit. When it actually adds, it becomes 1000 and has obtained a correct result.
If the adder inputs are 0011 and 0010, the most significant digit is “00” in the first step, so the third + step is performed next. Since “11” is found in the third digit from the top, this corresponds to (9), and the highest digit that is not 0 is the second digit. When actually added, it becomes 0101, and a correct result is obtained.
If the adder inputs are 0110 and 1010, the most significant digit is “01” in the first step, so the second step is performed next. Since “11” is found at the next next digit, the third + step is performed. Since no digit other than “00” is found, this corresponds to (10), the value is 0, and there is no non-zero most significant digit. When actually added, the result is 0000, and the correct result is obtained.
If the adder inputs are 0110 and 1001, the most significant digit is “01” in the first step, so the second step is performed next. Since neither “00” nor “11” is found, this corresponds to (11), and the most significant digit that is not 0 is the least significant digit. When it is actually added and the sign is inverted, 0001 is obtained and a correct result is obtained.
The above is a specific example of the process for obtaining the most significant non-zero absolute value of the addition result from the adder input without error.

The processing of FIG. 5 is relatively complicated and may increase the amount of hardware and detection time. On the other hand, if an error of one digit is recognized when obtaining the most significant digit other than 0, the above processing is greatly simplified.
FIG. 6 shows a process for obtaining the highest non-zero digit of the addition result from the input of the adder with a one-digit error.
The first and second steps are the same as the processing in FIG. In the third step and the third + step, from the next digit, the input 2-bit values are searched for digits other than “11” and “00”, respectively, and the found digit is set to the highest non-zero digit. . If not found, the least significant digit is set to the most significant digit other than 0.
In this way, among (1) to (11) of FIG. In the case of (5), the second digit higher than the found digit is the highest digit other than 0, and does not fall within the error of one digit.
However, in this case, the positive rounding unit 11 may process as follows. In the above case, at the time when the sign is inverted in the positive number rounding unit 11, the one digit higher than the found digit is the most significant digit that is not 0 and is within one digit error, and the value is all 1. When 1 is added, the carry is transmitted to the top and becomes 100.0. If the result is shifted to the right by two digits, the correct mantissa is obtained, so 2 is sent to the exponent correction unit 12 to correct the exponent. On the other hand, the mantissa part is all zero except for the most significant part, and the value is correct even if it is not shifted, and a two-digit right shift circuit is not required. Only the most significant digit is shifted 2 digits to the right.

The process of FIG. 6 is applied to the most significant digit detection unit 5 as follows.
When the digit shift number is -1 or more, the upper part of the addend is 0 digits, but when the shift number is 2, the upper part of the addend is one digit. Therefore, the most significant digit detection is performed on the value obtained by adding the upper one digit of the addend to the output of the multiplication array 4 which is the input of the carry propagation adder 6 (first step in FIG. 7).
The output of the multiplication array 4 is binary with 2n + 1 digits and 2n digits, assuming that each input has n digits. For example, if the multiplication array 4 is a carry save adder, the carry part has 2n + 1 digits and the sum part has 2n digits. The upper 1 digit of the addend is added to the 2n digit side. In this way, both are 2n + 1 digits. In order to apply the processing of FIG. 6 as it is, it is necessary to add a sign bit to the most significant part of the carry part and the sum part. If the product and the addend have the same sign, 0 is added to both (the highest part of the carry part and the sum part). However, if the same sign is used from the 3+ step and if the different code is used from the second step, it is not necessary to add a sign bit. Eventually, the first step of the process of FIG. 6 may be modified as the first step of FIG.

FIG. 8 is a block diagram illustrating a configuration example of the most significant digit detection unit 5 of FIG. 1 that implements the processing of FIG.
The most significant digit detection unit 5 includes a digit shift number determination unit 82, a sign determination unit 84, a most significant digit determination unit 86, a search circuit 80, and an encoder 88. Here, the configuration of the mask generation unit for generating sticky bits is omitted.
The digit shift number determination unit 82 determines whether the value of the input digit shift number S1 is −2 or more or −3 or less. If it is determined that the number of digit shifts is −3 or less, the most significant digit determination unit 86 performs the processing of steps 402 to 404 in FIG. 4 based on the output of the gate EOR1, and the search completion mode described later in the search circuit 80. (01) is output and the search processing in the search circuit 80 is not performed.
If it is determined that the digit shift number is −2 or more, the code determination unit 84 performs the first step of FIG. That is, based on the output from the gate EOR1, it is determined whether the product and the addend have different signs or the same sign, and a mode (mode [K-1]) based on the determination result is output and supplied to the search circuit 80.
The search circuit 80 performs the second step, the third + step, and the third step in FIG.
If the bit width of two terms from the multiplication array 4 is, for example, 4n digits (n is an integer of 1 or 2 or more), the search circuit 80 includes n-1 four-digit search circuits 802 to 80n and one least significant bit. A 4-digit search circuit 801.
In FIG. 8, each input input [] to each 4-digit search circuit is one bit of the corresponding digit in two terms from the multiplication array 4 (that is, a bit consisting of one bit of the carry portion and one bit of the sum portion). It is a set of 2 bits (a set of digits).
Each 4-digit search circuit determines whether each 2-bit set is a set of numbers corresponding to the corresponding step in FIG. 7, outputs the determination result as found [], and all inputs to the circuit. The search mode signal mode [] is output in accordance with the determination result of (1) and provided to the search circuit at the next stage.
The output signal found [] is “1” if the digit corresponding to the input is a set of numbers corresponding to the step corresponding to FIG. 7, and “0” otherwise.
All outputs found [4n-1] to found [4k-4] of the search circuit 80 are encoded by the encoder 88 and output as an exponent normalized value D7 and a normalized shift number D9.
As described above, in this example, the search circuit 80 is divided into four digits to constitute a plurality of four-digit search circuits, and each four-digit search circuit is configured to input two terms (input []) from the multiplication array 4. A search is performed based on the search mode (mode []) from the preceding circuit (or upper 4-digit search circuit), and the search result (found []) is output, and the lower 4-digit search circuit is based on the search result. Give search mode.
In this example, there are four search modes as shown in FIG. That is, a positive / negative determination mode corresponding to the second step in FIG. 7, a positive number search mode corresponding to the third + step, a negative number search mode corresponding to the third step, and a search end mode. Are assigned 2-bit codes “00”, “10”, “11”, and “01” indicating the type of mode.

10 and 11 are tables showing examples of logic in the 4-digit search circuit and the least significant 4-digit search circuit of FIG. 8, respectively. 10 and 11, ¬ (00) and ¬ (11) (where ¬ represents negation) indicate combinations other than 00 and 2 bits other than 11, respectively.
The operation of the search circuit 80 of FIG. 8 will be described using the flowchart of FIG. 7 and the logic shown in FIGS.
The sign determination unit 84 executes the first step of FIG. 7. If the output of the gate EOR1 is “1”, the sign determination unit 84 has a different sign, so the positive / negative determination mode [00] is set as the mode signal mode [k−1]. If the output of the gate EOR1 is “0”, the sign is the same, so that the integer search mode [10] is output as the mode signal mode [k−1].
The operation of each 4-digit search circuit 802-80n will be described below.
In each of the 4-digit search circuits 802 to 80n, if the mode of the input mode signal mode [k-1] is the positive / negative determination mode [00] (corresponding to (1) to (22) in FIG. 10), In order to execute the two steps, the digit of the set of 2 bits “00” or “11” is searched from the next digit downward.
If there is a digit of “00” in the four sets of input inputs [4k−4] to input [4k−1] of the 4-digit search circuit (corresponding to (1) to (10) in FIG. 10), the addition result is negative. Therefore, the third step is executed to search for a digit other than “11” from the digit where “00” is found toward the lower digit. If a digit other than “11” is found, the found digit other than “11” is the most significant digit to be obtained. Therefore, in this case, since the search in the 4-digit search circuit after the next stage is unnecessary, the search completion mode [01] is output as the mode signal mode [k] ((1) to (3) in FIG. 5), (6), (8)). If no digit other than “11” is found, the negative number search mode [11] is output as the mode signal mode [k], and the third step is executed in the next-stage 4-digit search circuit ((4 in FIG. 10). ), (7), (9), (10)).

On the other hand, if the digit “11” is found in the second step (corresponding to (13) to (22) in FIG. 10), the addition result is positive. A digit other than “00” is searched from the digit where is found to the lower digit.
If a digit other than “00” is found, the found digit other than “00” is the most significant digit to be obtained. Therefore, in this case, since the search in the 4-digit search circuit after the next stage is unnecessary, the search completion mode [01] is output as the mode signal mode [k] ((15), (17), (18), (20) to (22)).
If no digit other than “00” is found, the positive number search mode [10] is output as the mode signal mode [k], and the 3+ step is executed in the next four-digit search circuit ((13 in FIG. 10). ), (14), (16), (19)).
In addition, if neither “00” nor “11” digit is found in the second step, the positive / negative judgment mode [00] is output as the mode signal mode [k], and the second digit search circuit in the next stage outputs the second digit. Steps are executed ((11) and (12) in FIG. 10).

On the other hand, in each of the four-digit search circuits 802 to 80n, if the mode of the input mode signal mode [k-1] is the positive number search mode [10] ((24) to (28) in FIG. 10), Perform the 3+ step as above.
In each of the 4-digit search circuits 802 to 80n, if the mode of the input mode signal mode [k-1] is the negative search mode [11] ((29) to (33) in FIG. 10), 3-Step is performed as above.
In each 4-digit search circuit 802 to 80n, if the mode of the input mode signal mode [k-1] is the search completion mode [01] ((23) in FIG. 10), the search is not performed as it is. Output the search completion mode [01].
The logic of the least significant four-digit search circuit 801 is almost the same as that of the four-digit search circuits 802 to 80n. However, when the second step, the third + step, or the third step is executed, the corresponding digit is not found. If it is, the lowest digit is determined as the highest digit. The least significant 4 digit search circuit 801 does not output a mode signal.

Next, the operation of the search circuit 80 of FIG. 8 will be described using the example of FIG.
In the example of FIG. 2, the search circuit 80 is composed of one 4-digit search circuit 802 and the lowest-order 4-digit search circuit 801. Here, for example, the input to the lowest-order 4-digit search circuit 801 is 5 digits. Since the output of the gate EOR1 is “0” and the product and the addend have the same sign, the positive search mode [10] is given to the 4-digit search circuit 802 as the mode signal mode [k−1], and the 4-digit search circuit 802 executes the third + step.
That is, when searching for digits other than “00” in the lower order, “10” is input.
Since it is in [4k-3], "0100" is output as output found [4k-4], found [4k-3], found [4k-2], found [4k-1], and the mode signal mode The search completion mode [01] is output as [k]. Therefore, the least significant digit search circuit 80 outputs “0000” as the output found [4n-4], found [4n-3], found [4n-2], and found [4n−1].
In this way, it is determined that there is the most significant digit to be found in the input input [4k-3].

The circuit of FIG. 8 is a simple circuit when the output bit width of the multiplication array 4 is small, but the search time increases as the bit width increases. Also, if the normalization by the normalization shifter 10 is performed with a one-stage shift when the bit width is large, the shifter load becomes heavy and slows down.
The search circuit of FIG. 12 is a circuit obtained by improving the search circuit 80 of FIG. 8 in response to a case where the bit width is large.
The bit width is 64 digits in this example. Here, the search circuit 110 includes seven mode look-ahead and first stage shift control circuits 30 to 36, the least significant mode look ahead and first stage shift control circuit 37, 15 four-digit search circuits 38 to 52, and the least significant. It consists of a 4-digit search circuit 53 and eight 8-bit logical sums 54 to 61 (FIG. 13).
In order to speed up the search, a mode look-ahead circuit for transmitting the search mode signal to the lower order at high speed is added, and the first-stage shift control signal shift — 1st [1-8 corresponding to the case where the normalization by the normalization shifter 10 is performed in two stages. ] And the second stage shift control signal shift_2nd [1-8].

Here, the input to each mode look-ahead and first stage shift control circuits 30 to 36 and the lowest first stage shift control circuit 37 is 8 digits. Of these 8-digit inputs, the upper 4 digits and the lower 4 digits are respectively input to two 4-digit search circuits (same configuration as the 4-digit search circuit in FIG. 8).
First stage shift control signals shift — 1st [1] to [8], which are outputs of the first stage shift control circuits 30 to 37, are applied to the encoder 90. Eight outputs (found [8k-8] to found [8k-1], k = 1 to 8 in this example) of the two 4-digit search circuits related to the first stage shift control circuits 30 to 37 correspond to each other. It is input to one of the corresponding OR gates 54 to 61. That is, eight outputs found [8k-8], found [8 (k + 1) -8]... Found [56] are input to the OR gate 54, and eight outputs found [8k-7], found [8 (k + 1) − 7] ... found [57] is input to an OR gate (second stage shift control circuit) 55. The second stage shift control signal shift_2nd [i], which is the output of these signals and 54 to 61, is similarly applied to the encoder 90.
Each mode look-ahead and first stage shift control circuits 30 to 36 perform a search in a mode according to the mode signal mode [] from the previous stage, and determine whether or not there is the most significant digit to be found in the 8-digit input. The first stage shift control signal shift — 1st [k] is given to the encoder as “1”, otherwise “0”. Further, a mode signal according to the determination result is given to the next stage.

14 and 15 are tables showing examples of operation logic of the mode look-ahead, the first stage shift control circuit, and the lowest first stage shift control circuit of FIG.
Next, the operation logic of the mode look-ahead and the first stage shift control circuits 30 to 36 will be described. In FIG. 14, “-” indicates don't care.

In the figure, examples (1) to (18) indicate that the input mode is [00], that is, the positive / negative determination mode, and the second step is executed in the circuit. Among them, examples (1) to (8) show a case in which the negative number search mode [11] is output as an output mode signal because “11” is found as a result of executing the second step for 8-digit input in the circuit. Therefore, the third step is executed in the next stage.
Similarly, in the examples (11) to (18), since “00” is found as a result of executing the second step for 8-digit input in the circuit, the positive number search mode [10] is output as the output mode signal. Indicates. Therefore, in the next stage, the third + step is executed.
In the examples (9) and (10), the result of executing the second step for the 8-digit input in the circuit is that neither “00” nor “11” is found, so the positive / negative judgment mode [00] is selected as the output mode signal. Indicates the case of output. Therefore, the second step is still executed in the next stage.
In the example (19), since the most significant digit to be obtained is found in the previous stage, the input mode is [01], that is, the search completion mode. Therefore, the search completion mode [01] is similarly output as an output mode signal.

In the example (20), the input mode is [10], that is, the positive number search mode. As a result of executing the third + step in the circuit, no digits other than “00” are found, and the output mode signal is a positive number. The case where search mode [10] is output is shown. Therefore, in the next stage, the third + step is still executed.
In the example (21), the input mode is [11], that is, the negative number search mode. As a result of executing the third step in the circuit, no digits other than “11” are found, and the negative number search is performed as the output mode signal. The case where mode [11] is output is shown. Therefore, the third step is still executed in the next stage.
In any of the above cases, the first stage shift control signal shift — 1st [k] is “0”.
On the other hand, the example (22) is a case other than the above, and the most significant digit required in the mode look-ahead and the first stage shift control circuit is found, and the search completion mode [01] is output as the output mode signal and the first stage “1” is output as the shift control signal shift — 1st [k].

The operation logic of the lowest first stage shift control circuit 37 is as shown in FIG.
That is, since the most significant digit to be obtained is found in the previous stage, the input mode is [01], that is, the search completion mode. Accordingly, “0” is output as the first stage shift control signal shift — 1st [8].
In addition, when the input mode is other than [01], that is, in any case of [00] [10] [11], the most significant digit required in the previous stage is not found, and therefore, the least significant 8 digits are used. If it is found or not found in this least significant 8 digits, it is considered as found in the least significant digit. Therefore, in any case, since it is found in the least significant 8 digits, “1” is output as the first stage shift control signal shift — 1st [8].

  Therefore, the most significant digit position (shift amount) to be obtained in units of 8 digits can be found from each mode look-ahead and the first-stage shift control signal shift_1st [k] from the first-stage shift control circuit. The most significant digit position (shift amount) can be determined in units of one digit by the stage shift control signal shift_2nd [i]. Therefore, the most significant digit position is known from these first-stage and second-stage shift control signals, and when this is encoded, the exponent normalized value and the normalized shift number can be obtained.

As described above, when the target digit is not found as a result of executing the corresponding steps in FIG. 7 in each mode look-ahead and first-stage shift control circuit, the same is applied to the next-stage mode look-ahead and first-stage shift control circuit. These steps need to be executed (examples (10) and (19) to (21) in FIG. 14).
Therefore, in such a case, in the configuration of FIG. 8, the mode is transmitted through the search operation in the 4-digit search circuit, but in the configuration of FIG. 12, the mode look-ahead and the processing of only the first stage shift control circuit can quickly Since the mode to be executed at the next stage can be instructed, the output mode can be transmitted to the lower order at a higher speed than in the configuration of FIG.

The mode look-ahead logic appears to be complex and seemingly unable to transmit high-speed mode signals. However, the search mode is switched twice from the positive / negative determination mode to the positive number search mode or the negative number search mode and from the search mode to the search completion mode. That is, the search mode is not switched by at least six of the eight mode look-ahead circuits of eight digits.
Therefore, if the speed of the case where the search mode is not switched is increased, high-speed mode signals can be transmitted. When the search mode is not switched, all the inputs are 0 (example (20) in FIG. 14), all 1 (example 21), and the exclusive OR of the inputs is all 1 () examples (9) and (10). The speed of this part of the circuit is easy.
In addition, since the first stage shift control logic determines whether or not the most significant digit is somewhere in the 8 digits, the generation logic is simpler and faster than the search result found [0 to 63]. it can.
Since the second stage shift control logic is generated from the found [0 to 63] through the 8-input OR circuit, the second stage shift control logic is slow. However, there is no problem because it is sufficient if the first stage shift is completed.
For example, when a double-precision floating-point multiply-accumulate operation is performed, the input mantissa part has 53 digits, and the output of the carry propagation adder 6 is 106 digits + carry to the higher order. When a digit loss occurs, there is a possibility that the highest digit which is not 0 in absolute value will come anywhere in 106 digits. However, the possibility that the most significant digit comes in the lower 53 digits is extremely low. In addition, when such a significant digit loss occurs, the significant figure becomes 0 digits. Furthermore, if the most significant digit is in the lower 53 digits, rounding is unnecessary and an accurate value can be output without normalization. Therefore, in such a case, it is sufficient to output a value that has not been normalized once as a result even if the number of execution cycles increases, and then normalize by increasing the number of execution cycles.
From the above, the most significant digit detection unit 5 and the normalization shifter 10 perform normalization correctly when the most significant digit is present in the 52 or more digits from the lower order of the output of the carry propagation adder 6, and otherwise the lower order 53. Even if the digit is output without normalization, the performance is not affected. In this way, the most significant digit detector 5 and the normalization shifter 10 can be simplified.

  The operation of the product-sum calculator having such a configuration will be described with reference to FIG.

Here, the case where the mantissa part is 4 digits will be described using specific numerical values.
When (1.001 × 21) × (1.001 × 22) + (− 1.010 × 23) is calculated, the result is as follows.
First, the digit shift number exponent generation unit 1 generates 1 + 2-3 = 0 as the digit shift number, and generates 1 + 2 = 3 as the exponent because the digit shift number is −2 or more.
Next, in the addend digit alignment code matching unit 2, the addend mantissa part 1.010 is shifted to the right by 0 digits, and since it is a different sign, 0 is added to the middle of the addend and the upper part of the addend, and the addend is changed. Generates the order 10.101111, the addend high 1.000, the mantissa low 0000, and the addend high lowest 1.000. Next, the addend lower sticky bit generation unit 3 generates 0 as the sticky bit because the addend lower 0000 is 0.
By these operations, the above equation becomes (1.000 × 25) + ((1.001 × 1.001 + 10.101111) × 23)
It becomes. 25 indicates that the upper one of the addend is the highest one digit of the middle of the addend.
Next, in the multiplication array 4,
1.001 × 1.001 + 10.101111
As described above, the multiplication part is converted to addition and 3 terms are added.
000.000010
+ 11.111111
It becomes. These two terms are the output of the multiplication array 4.

In the most significant digit detection unit 5, since the most significant digit that is not 0 is the least significant digit from the output of the multiplication array 4 and the digit shift number 0, the search is terminated at the fourth digit from the least significant, and the exponent normalization unit The exponent normalized value -3 is output to 8, the mask 00000000 is output to the sticky bit generation unit 9, and the normalized shift number -3 is output to the normalization shifter 10.
The carry propagation adder 6 adds the outputs of the multiplication array 4 and, since the product and addend have different signs and the addend lower sticky bit is 0, adds 1 to the least significant to generate 00.000001 to generate a sticky bit. Output to the unit 9 and the normalized shifter 10. Also, carry 1 from the top is output to the addend higher incrementer 7.
The addend higher incrementer 7 generates 00.000 because the digit shift number 0 is -2 or more and the normalized shift number -3 is other than 1.
At this time, the first equation is (00.000 × 23) + (00.000001 × 23)
It has become.
The exponent normalization unit 8 adds the exponent 3 from the digit shift number exponent generation unit 1 and -3 from the most significant digit detection unit 5 to output 0.
The sticky bit generation unit 9 masks the carry propagation adder 6 output 00.000001 with the most significant digit detection unit 5 output 00000000 to perform a logical sum, and further performs a logical sum with 0 from the addend lower sticky bit generation unit. The value 0 is output.
In the normalization shifter 10, since the normalized shift number is -3, the carry propagation adder 6 output 00.000001 is shifted to the left by 3 digits to extract the upper 6 bits of 00.0010, and the addend upper incrementer 7 output The logical sum of 00.000 is taken and output as 0.010.
At this time, the first equation is 00.0010 × 20
It has become. In the positive rounding unit 11, the output of the normalization shifter 10 is 00.0010 and the sticky bit is 0, so the output of the positive rounding unit 11 is 0.001. The exponent correction unit 12 outputs the exponent normalization unit 8 output 0 as it is because the positive digit rounding unit 11 did not need to correct the most significant digit position.
As a result, the final calculation result is 0.001 × 20. When this value is normalized again, it becomes 1.000 × 2-3.

FIG. 17 is a block diagram of a product-sum calculator according to still another embodiment of the present invention.
This product-sum calculator does not perform sign matching, normalization, and rounding in various rounding modes, which are generally performed in floating-point product-sum operations. Therefore, the present embodiment is a floating-point product-sum operation unit in which the multiplicand, multiplier, and addend all have the same sign and rounding is performed only by truncation. An engineer specializing in this field can construct a general floating-point product-sum calculator by adding the sign matching, positive number conversion, and rounding processing to this embodiment.

This embodiment includes a digit shift number exponent generation unit 1, an addend digit adjustment unit 2, a product-sum operation array 4, a re-higher digit detection unit 5, a carry propagation adder 6, an exponent normalization unit 8, and a normalization shifter It consists of ten.
A digit shift number exponent generation unit 1 receives an addend, a multiplicand, and an exponent part of a multiplier, generates a digit shift number and an exponent before normalization, and an addend digit adjustment code match unit 2 and an exponent, respectively. Output to the normalization unit 8. As the exponent before normalization, the sum of the exponent part of the multiplicand and the multiplier, that is, the exponent part of the product is output. The digit shift number is generated by subtracting the addend exponent from the exponent of the product.
If the number of digit shifts is equal to or less than (-the number of digits in the mantissa part-1), the addend digit aligning unit 2 for processing the mantissa part, the product-sum operation array 4, and the re-higher digit detection The bit widths of the unit 5, carry propagation adder 6, and normalization shifter 10 become enormous and are not realistic. In this case, if the rounding is rounded down, the product part is rounded down and the result becomes the addend itself. Therefore, by adding a circuit that detects this case and outputs the addend as a result separately from this embodiment. The number of digits for processing the mantissa part can be (number of digits of the mantissa part × 3).

  The addend digit aligning unit 2 receives the addend mantissa part and the digit shift number, performs digit alignment of the addend mantissa part, and outputs the result to the product-sum operation array 4 as an addend mantissa part after digit alignment. Normally, the shift is performed according to the number of digit shifts. However, as described in the previous section, when the digit shift number is (−digit number of mantissa part−1) or less, the processing result of the circuit of this embodiment is not used, and the output value is arbitrary. On the other hand, when the number of digit shifts is equal to or greater than (the number of mantissa digits × 2-1), the addend is discarded and the result is the product of the multiplicand and the multiplier. In this case, 0 is output as the addend mantissa part after digit alignment.

  The product-sum operation array 4 receives the multiplicand mantissa part, the multiplier mantissa part, and the addend mantissa part after digit alignment, and carries the sum of the product of the multiplicand mantissa part and the multiplier mantissa part and the addend mantissa part after digit alignment as a carry. The calculation is performed using an array such as a storage adder or a redundant binary adder, and the result is output to the most significant digit detector 5 and the carry propagation adder 6. The outputs of the product-sum operation array 4 are two values that, when added by the carry propagation adder 6, result in a product-sum operation.

The most significant digit detection unit 5 detects the highest non-zero absolute value of the product-sum operation result from the output of the product-sum operation array 4, and the exponent normalization unit 8 supplies the exponent normalization value based on the detection result. The normalized shift number is output to the normalized shifter 10.
In this embodiment, the exponent normalization value and the normalized shift number are always the same. The most significant digit detection is performed based on the processing of FIG. However, in this embodiment, the output of the product-sum operation array 4 is not a two's complement but an absolute value. In order to apply the processing of FIG. 5, it is only necessary to add 0 to the higher order of the most significant digit of each of the two input values to make a two's complement. The exponent normalization value and the normalized shift number are the difference in the digit position between the calculated most significant digit and the digit to the left of the decimal point before normalization.

Carry propagation adder 6 adds the two values of product-sum operation array 4 output to generate a product-sum operation result mantissa part before normalization, and outputs the result to normalization shifter 10.
The exponent normalization unit 8 normalizes the exponent before normalization by adding the exponent normalization value from the most significant digit detection unit 5 and outputs the addition result as a final product-sum operation result exponent part.
The normalization shifter 10 normalizes the product-sum operation result mantissa part before normalization from the carry propagation adder 6 by using the normalization shift number from the most significant digit detection unit 5 and final product-sum operation result mantissa Output as part.

FIG. 18 shows an operation example in which the mantissa part of this embodiment is a specific numerical value of 4 bits.
When (1.110 × 22) × (1.101 × 23) + (1.011 × 27) is calculated, the result is as follows.
First, the digit shift number exponent generation unit 1 generates 2 + 3-7 = −2 as the digit shift number and 2 + 3 = 5 as the exponent before normalization. Next, the addend mantissa sign matching unit 2 shifts the addend mantissa part 1.011 two places to the left to generate an addend mantissa part 000011.100000 after digit alignment. By these operations, the above formula becomes ((1.110 × 1.101 + 000101.10000000) × 25)
It becomes. Next, in the product-sum operation array 4,
1.110 × 1.101 + 000101.100,000
The multiplication part of
0.001110
+ 0.00000
+ 0.1110
+ 1.110
+000101.100,000
And calculate as follows.

The product-sum operation array 4 is a carry save adder. The carry save adder adds three numbers and outputs two numbers, a carry part and a sum part. The carry part is generated by setting 1 to the next digit when there are two or more 1s in each digit. The sum part is generated by setting 1 in each digit when there is one or three in each digit. First, when the first three terms are added, this part becomes the two terms of the carry part and the sum part,
0.010000
+ 0.110110
+ 1.110
+000101.100,000
It becomes.
Furthermore, when the first three terms of this result are added, this part becomes two terms,
0.11.00000
1.010110
+000101.100,000
It becomes.
When these three terms are added,
000011.000000
+000101.010110
It becomes.
These two terms are the output of the product-sum operation array 4.

Next, the most significant digit detection unit 5 performs the most significant digit detection based on the processing of FIG. 5 by adding 0 to the uppermost part of the two most significant digits of the output of the sum-of-products operation array 4 to make a 2's complement.
First, in the first step, since the most significant digit is 00, the third + step is performed next.
In the 3+ step, since the left digit of the decimal point before normalization is found as the reference digit and 01 is found 2 digits to the left, the 4+ step is performed next.
Since 11 is found in the 4th + step, it corresponds to the case of (8) in FIG. 5, and the highest digit which is not 0 of the absolute value is obtained as one digit higher than the digit found in the 3 + step, that is, 3 digits to the left of the reference digit. The most significant digit.
Therefore, 3 is output to the exponent normalization unit 8 and the normalization shifter 10 as the exponent normalization value and the normalized shift number.
Carry propagation adder 6 adds outputs from product-sum operation array 4 to generate 0001000.010110, and outputs the result to normalized shifter 10. At this time, the first equation is (0001000.0101110 × 25)
It has become.
Next, the exponent normalization unit 8 adds the exponent 5 before normalization and the exponent normalization value 3 from the most significant digit detection unit 5 to output 8. Since the normalized shift number is 3, the normalization shifter 10 shifts the carry propagation adder 6 output 0001000.0110110 rightward by 3 digits and outputs 1.000 of 4 bits from the left digit of the decimal point. As a result, the calculation result is 1.000 × 28.

  In the above embodiment, an array of carry save adders is used as the multiplication array, and the most significant digit detection unit receives the carry part and the sum part, which are the operation outputs of the two terms of the multiplication array, as an absolute value of 0. The most significant digit is detected by using an array such as a redundant binary adder as a multiplication array and detecting the most significant digit that is not zero in absolute value using the operation output of the two terms of the array as an input. It goes without saying that the detection unit can be configured in the same manner as in the embodiment.

  As in the example of FIG. 3, when the addend is larger than the product, the upper part of the addend that protrudes higher than the product is processed without moving the most significant digit, and the addend other than the excess part is processed. In the embodiment in which the product sum operation result of the product and the product is normalized and finally added to obtain the final normalized product sum operation result, the input to the highest detection unit is multiplied by the array Instead of the two terms from, the mantissa part of the product-sum operation result before normalization from the carry propagation adder 6 may be used.

Next, an example of a data processing apparatus using the product-sum calculator according to the present invention will be described with reference to FIG.
The data processing apparatus includes an instruction fetch decoding unit 100, a calculation unit 200, a memory access unit 300, and a memory 400. The product-sum calculator 210 according to the present invention is in the calculation unit 200.

Next, the configuration and operation of each unit in FIG. 19 will be described.
The instruction fetch decoding unit 100 outputs an instruction address 110 to the memory access unit 300, makes an instruction fetch request, reads the instruction from the memory 400, receives the instruction 120 via the memory access unit 300, and decodes the instruction The control information 130 is output to the arithmetic unit 200. Normally, the instruction fetch and decode processing is performed on consecutive instruction addresses, and when the arithmetic unit 200 outputs a branch address 140 and issues a branch request, the processing is performed on the branch address 140.
The arithmetic unit 200 performs arithmetic operations, data fetches, stores, and the like based on the control information 130 from the instruction fetch decoding unit 100. In particular, when the operation is a floating-point product-sum operation, the product-sum operation unit 210 according to the present invention is used for processing.
In addition, when performing data fetch or store, the address 220 is output to the memory access unit 300, and further, the data 230 is also output at the time of store, a fetch or store request is performed, and the data 230 is received from the memory access unit 300 at the time of fetch. Receive.
Based on the instruction fetch request from the instruction fetch decoding unit 100 and the data fetch or store request from the arithmetic unit 200, the memory access unit 300 outputs the address 310 to the memory 400, and further outputs the data 320 at the time of storing. If the request is a fetch, the data 320 fetched from the memory 400 is output to the request source.
The memory 400 receives the address 310 from the memory access unit 300 and also receives the data 320 at the time of storing, performs a fetch or store operation, and outputs the data 320 to the memory access unit 300 when the request is a fetch.

Next, the calculation operation by the product-sum calculator 210 will be described.
First, the instruction fetch decoding unit 100 outputs the instruction address 110 to the memory access unit 300 as described above, receives the instruction 120 from the memory access unit 300, and decodes the instruction to obtain the control information 130. The control information 130 includes information related to operations such as operands, addition, multiplication, and floating point operations. Based on the control information, the product-sum operation unit 210 performs a product-sum operation on the data (addend, multiplier, multiplicand) read from the memory 400 or the data read from the register 212 in the operation unit 200 as in the above embodiments. To do. The calculation result is stored in the memory 400 via the register 212 or the memory access unit 300.

More specifically, the present embodiment is a so-called microprocessor if a portion other than the memory 400 is placed on one chip, and a processor board if it is placed on a plurality of chips and mounted on a board.
The present embodiment is an example of a data processing device using a product-sum operation unit based on the present invention. However, in general, if the data processing device uses a floating-point product-sum operation unit, the product-sum operation unit according to the present invention is used. Can be applied.

It is a block diagram which shows the structure of the sum-of-products calculator by the Example of this invention. FIG. 2 is a diagram for explaining an operation showing a flow of processing in each component of FIG. 1 when a product-sum operation of a certain expression is performed by the product-sum operation unit of FIG. 1. FIG. 8 is a diagram for explaining an operation showing a flow of processing in each component of FIG. 1 when performing a product-sum operation of another expression by the product-sum operation unit of FIG. 1. 3 is a flowchart illustrating an example of processing for obtaining a non-zero most significant digit from the absolute value of the mantissa part of the product-sum operation result before normalization from the two terms output from the multiplication array in the most significant digit detection unit of FIG. is there. In the most significant digit detection unit when the digit shift number is -2 or more, from the two terms output from the multiplication array, the most significant digit that is not 0 among the absolute values of the mantissa part of the product-sum operation result before normalization It is a flowchart which shows the process which calculates | requires without an error. FIG. 6 is a flowchart showing the processing modified in FIG. 5 so that the most significant digit that is not 0 among the absolute values of the mantissa part of the product-sum operation result before normalization is obtained with an error of one digit. 7 is a flowchart illustrating a process in which the process of FIG. 6 is modified to be applicable to the most significant digit detection unit of the product-sum operation result of FIG. FIG. 8 is a block diagram illustrating a configuration example of a most significant digit detection unit in FIG. 1 that implements the processing in FIG. 7. It is a figure which shows the example of the mode in the search circuit of FIG. It is a figure which shows the example of the operation | movement logic in the search circuit of FIG. It is a figure which shows the example of the operation | movement logic in the search circuit of FIG. It is a block diagram which shows another structural example of the search circuit of the most significant digit detection part of FIG. It is a figure which shows the structure of the 2nd stage shift control circuit of the search circuit of FIG. It is a figure which shows the example of the operation logic of the mode look ahead of FIG. 12, and a 1st stage shift control circuit. It is a figure which shows the example of the operation | movement logic of the lowest 1st stage shift control circuit of FIG. It is a figure for operation | movement explanation which shows the flow of a process in each component in the case of performing a product-sum operation by the product-sum operation unit by another Example of this invention. It is a block diagram which shows the structure of the product-sum calculator by another Example of this invention. FIG. 18 is a diagram for explaining an operation showing a flow of processing in each component of FIG. 17 when a product-sum operation of a certain expression is performed by the product-sum operation unit of FIG. 17; It is a block diagram which shows an example of the data processor using the product-sum calculator by this invention.

Explanation of symbols

1 Digit shift number exponent generation unit 2 Addend digit alignment code matching unit 3 Addend lower sticky bit generation unit 4 Multiplying array 5 Most significant digit detection unit 6 Carry propagation adder 7 Addend higher incrementer 8 Exponential normalization unit 9 Sticky bit generation unit 10 Normalization shifter 11 Normalization rounding unit 12 Exponential correction unit

Claims (1)

In a data processing device,
A memory for storing information necessary for calculation, and
An instruction fetch unit that reads and decodes the information in the memory and gives the information to the arithmetic unit;
An arithmetic unit having a product-sum operation unit that performs a product-sum operation with the multiplier, multiplicand, and addend based on the decoded information;
The product-sum calculator is
Based on the exponent part of the multiplier, the exponent part of the multiplicand, and the exponent part of the addend, a digit shift number generator that obtains the digit shift number and the exponent of the product-sum operation result before normalization,
The first mantissa part of the addend consisting of the first mantissa part of the addend consisting of the part of the mantissa part of the addend that protrudes above the digit corresponding to the product based on the digit shift number An addend that outputs and shifts the second mantissa part of the addend consisting of a portion excluding the first mantissa part of the mantissa part of the addend based on the digit shift number The digit alignment part;
Multiply-add operation in which the mantissa part of the multiplier, the mantissa part of the multiplicand, and the second mantissa part of the addend from the addend digit aligning section are input, and the product-sum operation is performed to output two terms. An array,
A carry propagation addition unit that inputs the two terms from the product-sum operation array, performs carry propagation addition based on the two terms, and outputs a lower-order mantissa part of the product-sum operation result before normalization;
The two terms from the product-sum operation array, one of a multiplier indicating that the product and the addend are different signs, an exclusive OR of the multiplicand and the sign of the addend, and the digit shift number An uppermost digit detection unit that detects the highest digit that is not 0 of the absolute value of the mantissa part of the product-sum operation result before normalization based on these, and is the sum of the two terms or the lower-order side A determination unit that determines whether a sum of a mantissa part and a digit shift number is positive or negative; and, when the sum is positive, based on the two terms or the lower-order mantissa part and a digit shift number before the normalization A first detection unit that detects the most significant digit that is not 0 among the absolute values of the mantissa part of the product-sum operation result, and when the sum is negative, the two terms or the lower-order mantissa part and a digit shift The highest non-zero of the absolute value of the mantissa part of the product-sum operation result before normalization based on the number A second detection unit for detecting a digit; a positive / negative determination mode for determining the sign of the sum from higher to lower; a positive number search mode when the sum is positive; a negative number search mode when the sum is negative; And a signal that indicates which mode is the search end mode after detecting the most significant digit, and the most significant digit that is not 0 is detected by the first detection unit and the second detection unit. Whichever detection unit is used, the most significant digit detection unit finally determined by the first detection;
Based on the most significant digit detected by the most significant digit detection unit, normalization of the lower mantissa part of the product-sum operation result before normalization from the carry propagation addition unit is performed, and the normalized product A normalization part for obtaining the lower-order mantissa part of the sum operation result;
An addend upper increment section that selectively increments the first mantissa part of the addend from the addend digit aligning section based on the carry from the carry propagation addition section;
A normal sum is obtained by ORing the lower mantissa part of the normalized product-sum operation result from the normalization part and the first mantissa part of the incremented addend from the addend upper increment part. Means for obtaining the mantissa part of the result of the sum of products
Based on the most significant digit detected by the most significant digit detection unit, normalization of the exponent of the product-sum operation result before normalization from the digit shift number generation unit is performed, and normalized product-sum operation An exponent normalization unit for obtaining an exponent of the result,
A data processing apparatus.

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