JPH0338912A - Output circuit - Google Patents

Abstract

PURPOSE:To suppress noise induced in a power supply line or a grounded line and to obtain an output circuit with high reliability by applying adjustment control to a charge current or a discharge current of a capacitor in relation to the voltage fluctuation of a power supply. CONSTITUTION:A series circuit comprising 1st and 2nd transistors(TRs) of the same conduction type is connected between a power supply terminal 4 and a ground terminal 17, 3rd and 4th TRs Q5, Q6 are connected in parallel with the 1st and 2nd TRs Q3, Q4 and one of the 3rd and 4th TRs Q5, Q6 is energized in relation to the output of a voltage fluctuation detection circuit A detecting the voltage fluctuation of the power supply. Then the charge current and the discharge current of a capacitor are adjusted in relation to the voltage fluctuation of the power supply to suppress noise caused in a power supply line and a grounded line.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an output circuit of a semiconductor device.

[Conventional technology]

A conventional output circuit of this type is shown in FIG. 4, for example. A series circuit of MOS transistors Q1 and Q2 is interposed between the voltage terminal 4 and the ground terminal 7.
The connection point between S transistors Q and Q2 is output terminal 3
connected to. Output end 3 is connected to ground end 7 via capacitor C. Manual input signals φ1 and φ2 are applied to the gates of the MOS transistors Q1 and Q2, respectively.

Next, this operation will be explained. MOS l-ranjisk Q
A human input signal φ1 is input to the gate of Q2. MOS l-transistor Q by binary logic rHJ and rLJ of φ2
,, Q2 becomes conductive or non-conductive, and depending on the combination of the binary logic values, the capacitor C connected to the output terminal 3 is charged or discharged, and the voltage level of the output terminal 3 becomes rH or "L".
"become. Also, the human power signal φ1. Both φ2 are r L J
When the level is high, both MOS transistors Q, , Q become non-conductive, and the output terminal 3 becomes a high impedance state.

[Problems to be Solved by the Invention] As mentioned above, in the conventional output circuit, when the voltage level at the output terminal 3 changes from rl, J to r)l4, ? '
A charging current flows all at once to the capacitor C through the lO5 transistor Q. This causes a problem in that noise that instantaneously lowers the voltage of the power supply line is generated on the power supply line, making the operation of transistors in the peripheral circuitry unstable. Further, when the voltage level of the output terminal 3 changes from "H" to "L", the discharge current of the capacitor C flows all at once to the ground terminal 7 through the MOS transistor Q2. This causes a problem in that noise that instantaneously increases the voltage of the ground line is generated on the ground line, making the transistor operation of the peripheral circuitry unstable.

In view of this problem, it is an object of the present invention to provide an output circuit that can suppress noise generated in a power supply line or a ground line when charging or discharging a capacitor to change the voltage level at the output terminal.

[Means for Solving the Problems] The output circuit according to the present invention includes a first . A series circuit of second transistors is connected to connect the first and second transistors. The third transistor is connected to the second transistor. In connection with the output of the voltage fluctuation detection circuit which connects the fourth transistor in parallel and detects the voltage fluctuation of the power supply, the third. One of the fourth transistors is configured to be conductive.

[Effect] The capacitor is charged by conduction of the first transistor.

The capacitor is discharged due to the conduction of the second transistor.

When the first or second transistor is conductive, if the voltage fluctuation detection circuit detects a voltage higher than a predetermined value, the third or 41st transistor becomes non-conductive, and if the voltage fluctuation detection circuit detects a voltage lower than the predetermined value, the third or The fourth transistor becomes conductive.

Therefore, the charging current and discharging current of the capacitor are adjusted in relation to voltage fluctuations of the power supply, thereby suppressing noise generated in the power supply line and the ground line.

〔Example〕

The present invention will be described in detail below with reference to drawings showing embodiments thereof. FIG. 1 is a circuit diagram of an output circuit according to the present invention. A series circuit including resistors R1 and R2 is interposed between a power supply terminal 4 to which a power supply is connected and a ground terminal 7.

The connection point between resistors R1 and R2 is connected to one input terminal NA of NAND circuits NA and NA via inverters I, L.
, □ and NA2. are connected to each other. A voltage fluctuation detection circuit A is constituted by these resistors R+, R'z and inverters It, rz. The gate G of transistor Q:l is connected to the other input terminal NA1 of the NAND circuit NA+.
．． and an N-channel MOS transistor Q.

gate G, N-channel MOS l-transistor Q
I.

and the transistors Q, respectively, through an inverter I4. 3N connected to gate G of
The output terminal of the AND circuit NA is connected to the drain D of the MOS I-transistor Q. MOS transistor Q. The sources S of and Q are connected to the gate G of the N-channel MOS transistor Q, and the source S thereof is connected to the power supply terminal 4.

A series circuit of the MOS transistor Q3 and an N-channel MOS l-transistor Q4 is interposed between the power supply terminal 4 and the ground terminal 7, and the MOS l-transistor Q and each drain D of A4 are connected. The point is connected to the output end 3. This output terminal 3 is connected to the drain D of a MOS I-transistor Q6 which connects the drain D and source S of the MOS transistor Q5 to the ground terminal 7, and the output terminal 3 is grounded via a capacitor C. .

The gate G of the MOS transistor A4 to which the input signal φ2 is input is connected to the other input terminal NAz of the NANDA path NA2.
b, the gate G of the N-channel MOS transistor Q, and the drain D of the N-channel MOS transistor Q8.
Channel MOS) Connected to the gate of transistor Q8. The output terminal of NANDA path NA2 is connected to the drain D of MOS transistor Q7. Each source S of MOS transistors Q7 and A8 is connected to the gate G of the MOS transistor Q6.

Next, the operation of the output circuit configured as described above will be explained with reference to FIGS. 2 and 3. FIG. 2 is an operational characteristic diagram for the voltage fluctuation detection circuit in which the vertical axis is the output signal SA of the constant voltage fluctuation detection circuit A and the horizontal axis is the voltage VCC at the power supply terminal 4. Output signal SA of circuit A, input signal φ0. φ2 and MOS) transistor Q5. Q,
This shows the truth values of the signals SB and Sc given to the gates of .

First, the operation of the voltage fluctuation detection circuit will be explained. If the voltage VCC at the power supply end 4 rises to V eel, the voltage at the input terminal of the inverter 11, that is, the node ND, becomes (R, ·V cc,)/(RI+R2), which is the voltage before rising. Input terminal (RZ ・VCC) / (R++'
It is slightly higher than R2). Here, if the threshold value of the inverter L is set to a predetermined value equal to or higher than (Rz・VCC)/(R,+R2), it is possible to detect that the voltage at the power supply terminal 4 fluctuates above or below the predetermined value. . That is, when the voltage VCC at the power supply terminal 4 becomes more than a predetermined value, the output signal SA to the voltage fluctuation detection circuit becomes the "11" level, and when it becomes less than the predetermined value (fi, the binary signal becomes rl, j level). .

Next, consider the case where the voltage level at the output terminal 3 changes from rl, J to rHJ. In this case, the input signal φ1 is rl
, J to rl (changes to J level. Thereby, MOS
) The transistor Q3 becomes conductive and a charging current flows from the power supply terminal 4 to the capacitor C, and the voltage level at the output terminal 3 becomes "L".
It changes from to rH. For example, if the channel width of MOS transistor Q2 of the conventional output circuit shown in FIG. 4 is W, and the channel width of MOS transistors Q, , Q, shown in FIG. 1 is W/2, then input signal φ1 but"
By changing from level 1- to level 11, the MOS
) Since only transistor Q is conductive, the channel width is halved compared to the conventional one, and as a result, capacitor C
charging current decreases. In the explanation so far, the output signal SA of the voltage fluctuation detection circuit A is rHJ, that is, NAN
The input terminal N8 of the D circuit NA is at the rHJ level, the human input signal φ is at the rH level, that is, the input terminal NA+b of the NAND circuit NA is at the rH level,
The output level is "L", and MOS transistor Q is turned on due to conduction of MOS transistor Q.

becomes non-conducting. ■The voltage at the power supply end. , is greater than a predetermined value, a charging current flows from the MOS I-transistor Q3 to the capacitor C, and the charging current does not flow to the capacitor C all at once. And the voltage at the N source end ■. NAIJD falls below a predetermined value and the output signal SA of the voltage fluctuation detection circuit hole reaches the rJ, J level.
When the output of circuit NA becomes rH level, MOS transistor Q becomes conductive, MOS transistor Q5 becomes conductive, and a charging current flows from MOS transistors Q3 and Q to capacitor C.

This will reduce delays in access operations,
Further, when the voltage VCC at the power supply end is high, the charging current flowing through the inductance component of the power supply line reduces the noise voltage L·(di/dL) induced.

On the other hand, the voltage level at the output terminal 3 changes from r 11 J to "L"
In this case, the human power signal φ2 changes from rlJ level to rI(J level).

Thereby? IO5) The transistor Q4 becomes conductive, the discharge current of the capacitor C flows through it, and the output terminal 3 changes from the rHJ level to the "L" level. Here, as mentioned above, the channel width of the MOS transistor Q2 in the conventional output circuit is W, and the MOS transistor Q4 .
Since the channel width of Q6 is set to W/2, the human input signal φ
2 changes from the r(-' level to the 2' level), first only the MOS I-transistor Q becomes conductive, so the channel width is halved compared to the conventional one, and the discharge of the capacitor C is thereby reduced. The current decreases.In the explanation so far, the output signal S of the voltage fluctuation detection circuit A becomes r
H, that is, the input terminal NA2. of the NANDA path NA2. is at the river-I level, and the human input signal φ2 is rH, level,
In other words, the input terminal NAzb of the NANDA path NA2 is "11".
” level, its output level is “L”, and M
When the OS transistor Q7 becomes conductive, MOS 1 to transistor Q6 become non-conductive. In this way, the voltage at the power supply terminal V
If CC is above a predetermined value, MOS transistor Q.

The discharge current of the capacitor C flows only through the capacitor C, and the discharge current does not flow to the ground terminal 7 all at once.

Also, on the contrary, the voltage V at the power supply end. When C falls below a predetermined value and the output signal S1 to the voltage fluctuation detection circuit reaches the 7J level, the output of the NANDA path NA2 becomes the rHJ level and the MOS transistor Q7 becomes conductive.
Transistor Q6 conducts and the discharge current of capacitor C flows through transistors Q4 and Q6 (MOS). This reduces the delay in access operations, and the noise voltage L・(di/dt ) can be reduced.

In this way, the voltage at the power supply end 4 is reduced. Since the charging current and discharging current of capacitor C are adjusted in relation to the fluctuations in do.

Thereby, the transistors in the peripheral circuits of the power supply and ground lines can always operate stably.

[Effects of the Invention] As detailed above, the output circuit of the present invention adjusts and controls the charging current or discharging current of the capacitor in relation to voltage fluctuations of the power supply when changing the voltage level at the output terminal. Therefore, noise induced in the power supply line or the ground line is suppressed. Therefore, according to the present invention, the operation of the transistors in the peripheral circuits of the power supply and ground lines does not become unstable due to voltage fluctuations at the terminal tA, and an excellent effect is achieved in that a highly reliable output circuit can be provided.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an output circuit according to the present invention, Fig. 2 is an operational characteristic diagram of a voltage fluctuation detection circuit, Fig. 3 is a diagram showing truth values of various signals, and Fig. 4 is a circuit diagram of a conventional output circuit. It is a diagram. 3... Output end 4... Power end 7... Ground end A
. . . Voltage fluctuation detection circuit I,, f2. [3,1,...
・Inverter Q3. Q4~Q,. ...N channel M
O5l-transistor NA+, NA2...NAN
D circuit C...capacitor In the drawings, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) An output circuit in which first and second transistors of the same conductivity type are connected in series between the power supply terminal and the ground terminal, and the connection point of the first and second transistors is grounded via a capacitor. The voltage fluctuation detection circuit includes a voltage fluctuation detection circuit that detects voltage fluctuations of the power supply, and third and fourth transistors connected in parallel with the first and second transistors, respectively, and the output of the voltage fluctuation detection circuit An output circuit characterized in that the output circuit is configured to conduct one of the third and fourth transistors in relation to the output circuit.