JPS62123827A - Output circuit in semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce noise on a ground line by connecting a couple of switch MOSFETs smaller in size than that of each component constituting an output buffer is parallel with each component, and driving the said switch MOSFETs before the drive of the output buffer so as to flow a current gradually to a load. CONSTITUTION:The output terminal of the output buffer 1 is connected in parallel with the output terminal of the switch comprising MOSFETs M1-M4. A signal TSCE driving a switch 10 is supplied before the inverse of signal TSC driving the output buffer 1 is supplies so as to switch the switch 10 by using the same signal being the inverse of signal IN fed to the output buffer 1. Since the size of each component of the switch 10 is constituted small sufficiently, the current is small. Thus, after a load CL is charged or discharged, the inverse of signal TSC is fed to the output buffer 1 to get a driven state. Thus, pulse noise is reduced.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a signal control technology and a technology that is effective when applied to the control of output signals. The present invention relates to a technique that is effective for use in output circuits of LSIs (Large Scale Integrated Circuits) such as LSIs.

[Background Art] There is a tri-state output circuit as shown in FIG. This output circuit consists of an output buffer 1 consisting of a P-channel MOSFETQ□ and an N-channel MO5FETQ2.
, a NAND gate 2 that turns on and off MOSFETQ by outputting a signal based on the output control signal TSC and data signal IN; and a NAND gate 2 that turns on and off MOSFETQ2 by outputting a signal based on the output control signal TSC and data signal IN. an inverter 4, an inverter 3 that outputs a signal obtained by inverting the data signal IN to one input terminal of the NAND gate 2, and a control signal T and a data signal I.
It consists of a NAND gate 5 that outputs a signal based on N to an inverter 4.

A timing diagram of the circuit shown in FIG. 5 above is shown in FIG. When the control signal TSC is at a high level (hereinafter referred to as "H"), the data signal "K is 11 H71
At this time, the outputs of the NAND gate 2 and inverter 4 both become "H", and accordingly, the N-channel MO3FET
Q2 is turned on, P-channel MO5FET Q1 is turned off, and the output of output buffer 1 is at a low level (hereinafter referred to as LL L
11).

On the other hand, when the control signal TSC is set to 44 Hjl and the data signal "■" is "L", the NAND gate 2,
The outputs of inverter 4 both go to 1'L 11 level, P channel MOSFET Q□ is turned on, and N channel MOSFET Q□ is turned on.
FETQ is turned off and the output of output buffer 1 is itH
“It’s leveled.

When the control signal TSC is "L", the output of the NAND gate 2 is set to the "H" level and the output of the inverter 4 is set to the "L" level regardless of the state of the data signal. Therefore, M.O.
Both S F E T Q1=Qz are turned off, and the output terminal of the output buffer 1 is placed in a tristate (high impedance) state.

A tristate type output circuit as described above is described in, for example, Japanese Patent Application No. 174593/1983.

In the circuit shown in FIG. 5, the signal to be output from the output pin 11 is determined based on the data signal IN, and whether or not the signal IN is output to the output pin 11 is determined by the control signal TSC.

Here, for example, when the control signal TSC is set to the "H" level while the data signal IN is set to "II L", the MOSFETQ is turned on in response. At this time, charge is supplied from the power supply voltage terminal to the output pin 11 in a short time via MOSFETQ□. here,
This MOSFETQ is relatively large in size so as to have a relatively large driving capacity. Therefore, the potential of the output pin 11 is determined as a result of a large amount of charge being supplied from the power supply voltage terminal to the output pin 11 within a short time, and
It will rise steeply as shown in Figure (A). Here, if there are a large number of output pins that change simultaneously, even if the amount of charge supplied to each output pin is small, the total amount of charge will be large. This large amount of charge is then supplied from a common power supply line. Therefore, as the number of output pins increases, the noise on the power supply line increases, and as shown in Figure 6 (A), there is a noise of 7 levels (VOH peak) on other output pins fixed at ``H''. occurs. On the other hand, when the control signal TSC is set to the "H" level when the data signal] is at the "H" level, the MOSFETQ
, the charge is extracted from the output pin 11 to the ground in a short time, and the potential of the output pin 11 is brought to the "L" level. Here, this MOSFETQ is MOSFETQ
Similar to □, its size is made relatively large. Therefore, the potential of the output pin 11 changes as shown in FIG.
As shown in B), it suddenly changes from n Hpp level to It L
Move to jj level.

In the case where there are a large number of output pins that change simultaneously as described above, even if the charge supplied from each output pin is small, the total amount of charge is large.

Then, a large amount of charge will be leaked to the common ground line. Therefore, as the number of output pins increases, noise on the ground line increases, and as shown in FIG. 6(B), I'
Hl+ level noise (VOR peak) occurs.

When the levels of the VOH and VOL peaks become large, it causes system malfunction. For example, as microprocessors become larger in size, such as 8 bits, 16 bits, and 32 bits, the number of output pins that change at the same timing, such as address and data output pins, increases accordingly. There was a problem in that the level of this increased, causing system malfunction.

[Objective of the Invention] The object of the invention is to simultaneously control a large number of output pins in an LSI (Large Scale Integrated Circuit) having a large number of output pins.
The purpose of this invention is to reduce the VOR peak and VOL peak when switching from the L'' level or from the rr L It level to the ``H'' level, thereby preventing system malfunction.

The above-mentioned and other objects and novel features of the present invention will become apparent from the description of the present specification and the attached accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, a pair of switch MOSFETs of a sufficiently smaller size are connected in parallel with each element constituting the tri-state output buffer, and the above-mentioned Controls the switch MOSFET. As a result, when the potential of the output pin is changed from the J/L11 level to the LLH level, charge is gradually supplied to the capacitive load, and the output pin potential is changed from the H level to the L/L level. At this time, the charge is gradually drawn from the output pin to ground. In this way, after the level of the output pin is determined to a certain extent, the output buffer is driven by the control signal that controls whether or not to output an output signal based on the data signal, and the output is determined. Noise (VO
R peak, V.

This achieves the above objective of reducing the L peak.

[Embodiment 1] FIG. 1 shows an embodiment in which the present invention is applied to a tri-state output circuit in a complementary MOSFET such as a microprocessor. In the same figure, P channel MO3FETQ and N channel M
It consists of OSFETQ. An output buffer 1 having a complementary MO8 configuration and gates 2 to 2 for forming its control signal.
5 has the same configuration as that shown in FIG. 5. According to the embodiment, the control circuit consisting of MOSFET Q
-MOSF sized sufficiently smaller than the size of -Q-
ET, i.e. MO with sufficiently small conductance
SFETM1. Complementary MO8' consisting of M,! ft.
circuits are connected in parallel. In other words, one P-channel MO forming the complementary MO8 configuration circuit
SFETM is connected between the output terminal of output buffer 1 and the power supply voltage output terminal, and the other N-channel M
OSFETM is connected between the output buffer 1 and ground.

The tri-state control signal TSC is formed by a suitable tri-state enable signal.

The output buffer 1 is activated by setting the control signal TSC to a high level. P channel MOS
The control signal PIN for the FETM is connected to the inverter 4 which receives the input signal IN and the tri-state enable signal.
A control signal DIN for the N-channel MOSFETM is formed by a control circuit (not shown) having a similar configuration to that of the Nant gate 5 and inverter 3. Therefore, the circuit 10 consisting of MOSFETs M and M2 can be considered to constitute an output buffer with a small driving capacity.

Here, the control signal TSC is a signal that is delayed by a relatively large amount with respect to the tri-state error signal. On the other hand, the tri-state enable signal is directly supplied to a control circuit (not shown) for the circuit 1o, although this is not particularly limited. Therefore, the control signals PIN and DIN
is changed at a relatively early timing relative to the change in the tristate enable signal.

2A and 2B show timing diagrams for the circuit shown in FIG. 1. A signal based on the data signal IN'' is output from the output pin 11.The control signal TSC determines whether or not to output that signal, and the signal is set to diH'l level. , a signal based on the data signal “R” is output. Also, when the control signal TSC is at the tz L ## level, the output pin 11
is placed in a tristate (high impedance) state.

In the circuit shown in FIG. 1, when an "H" level signal should be output to the output pin 11, that is, when the input IN is connected to the second A
When the control signal 'r is set to low level as shown in the figure,
The PIN signal changes from It H+1 to 11 L based on the tri-state enable signal TSCE and the input signal IN before the s
It is made H. and.

MOSFET M1 of sufficient size is turned on, and charge is gradually supplied to capacitive load CL connected to output pin 11 via MOSFET M1. In this operating state, when charge is supplied and the output level approaches the power supply voltage terminal (Vcc), the control signal TSC
When is changed to tl H11 level, this turns on the large size MO5F E T Q i.

As a result, the level of the output terminal 11 is quickly changed to a good "H" level by the MOSFETQ.

On the other hand, when a signal at the It L 7j level is to be output to the output pin 11, the signal TSC switches from the "I, 3 level" to the "H" level as shown in FIG. The DIN signal is changed from “L” to “H” before the DIN signal is turned on. This turns on MO3FETM2, which is sufficiently small, and drains the charge from output pin 11 to ground through MO5FETM. Then, when sufficient charge has flowed out and the output level approaches the ground potential, the control signal TSC is
is changed to the level and the large size MOSFET Q2 is turned on. In response, the output terminal 11 is quickly changed to a favorable "L" level via the MOSFET Q2.

In this way, when the output pin 11 outputs a signal of "H7 level", charge is gradually supplied to the capacitive load C through the MOSFET M1 of a sufficiently small size, so that the potential of the output pin 11 is The rise when tt transitions from L to H becomes gentle, and even if many pins are changed from the 11 L jl level to the H level at the same time, a large current will not flow, and other "L" level noise (VOR peak) at the output pin fixed to "H" is reduced. On the other hand, output pin 11 is “It L”
When outputting a level signal, a MO of sufficient size
Since the charge is gradually drained from the output pin 11 to the ground via the 5FETM, the fall when the potential of the output pin 11 transitions from 'Hn to "L" is gentle, and a large number of Even if the output pin is changed from the “H” level to the “L” level, it will cause noise at the H## level on other output pins that are fixed at “L” (
VOL peak) is reduced.

[Embodiment 2] FIG. 3 shows the second embodiment of the tri-state output circuit according to the present invention.
This is an example. In the same figure, P channel/l/MOS
Complementary MO consisting of FET and N-channel O8FET
The control circuit consisting of eight output buffers 1 and gates 2 to 5 for forming control signals thereof is the same as that of the first embodiment. Furthermore, a complementary MO8 circuit composed of MO5FETM, .about.M, which is sufficiently smaller than the output terminal of the output buffer 1, is connected in parallel. MO5 configuring the circuit 10 with the complementary MO8 configuration
FETM, M, are connected in series between the terminal of output buffer 1 and power supply voltage terminal Vcc, and MOSFETs M2 and M4 are connected between the output terminal and ground.

Among these MOSFETs, MOSFETM.

A data signal IN is directly input to MOSFET M2. MOSFETM4 is MOSFETM, M4
A tristate enable signal TSCE signal is input which turns on and off the circuit 1o and controls the circuit 1o having a complementary MO8 configuration. MOSFET Ml converts the TSCE signal to inverter 1
2 is inverted and input.

FIG. 4 is a timing diagram of the circuit shown in FIG. The timing of the control signal TSC is formed based on an appropriate internal control signal TSCE as in the previous embodiment, and is set to the "H" level when the control signal TSCE signal is set to the 'JH)j level. A signal based on the data signal IN is output from the output pin 11. The control signal TSC determines whether or not to output that signal.
When that signal is set to the 11 HII level, a signal based on the data signal (2) is output. Further, when the control signal TSC is at the 11L'' level, the output pin 11 is placed in a tri-state (high impedance) state.

In the circuit shown in Figure 3 above, the potential of output pin 11 is “H”
When the control signal TSC is switched from the "L" level to the "H" level, the large-sized MOSFET
Before the ETQ switch is turned on, the TSCE signal is set to H" level, and the MOSFET M1, which is sufficiently sized, is turned on. Also.

MOSFETM is data signal I N (“L”)
It is turned on based on the L knee, and MOSFET M2 is turned off. Therefore, before MOSFET Q□ is turned on, capacitive load CL is connected to output pin 11 via MOSFET M□9M2, which is much smaller in size than MOSFET Q□.
Charge is gradually supplied to the After supplying sufficient charge, the control signal TSC is set to the 1H" level at the time when output determination is required.
FETQ.

is turned on, and immediately “
The signal is changed to "H" level.

On the other hand, when the output pin 11 is set to the "H" level, the control signal TSC switches from the "L" level to the "H" level, and the TSCE signal is set to the "H" level before the large size MOSFET Q2 is turned on. , a sufficiently small size MOSFETM.

is turned on. In addition, MOSFET M is a data signal I
is turned on based on N (“H”), and the MOSFET M is turned off. Therefore, before MO8FETQ is turned on, a MOSFE of a size much smaller than that is selected.
Charge is gradually drained from the output pin 11 to ground via TM, , M4. Then, at the point in time when output determination is required after sufficient charge has flowed out, the control signal TSC is set to the "H" level.

Then, the large size MOSFETQ is turned on,
The signal is immediately changed to the "H" level via the MOSFET Q2.

In this way, when the output pin 11 outputs a 'H' level signal, the MOSFET M1.M3 of a sufficiently small size is used.
Since charge is gradually supplied to the capacitive load CL connected to the output pin 11 via
The rise when transitioning from 9M to 1'H''' becomes gentle, and even if many pins go from "L" level to "H" level at the same time, other output pins fixed at "H" will not be at "L" level. Noise (VOR peak) is reduced. On the other hand, when the output pin 11 outputs the jJ L'' level signal, the charge is gradually removed from the output pin 11 to the ground via the sufficiently small sized MOSFETM, . As in the first embodiment, the potential of the output pin 11 is “H”.
” to “L” becomes smooth, and even if many bins are changed from “H” level to “L” level at the same time, other output pins fixed at “L” will have tzH” level noise. (VOL) is reduced.

Furthermore, in the first embodiment, the MOSFETs M, , M.

A logic circuit is required for each output circuit in order to form a PIN signal and a DIN signal for respectively controlling the MOSFETM2. Input data signal IN directly to M3.

Since the switch circuit is controlled, there is no need for a logic circuit for each output circuit. In addition, the newly added MO3FET
Since the sizes of M1 to M4 are small, they can be placed in an empty area near the output buffer.

Therefore, it is possible to reduce the chip size compared to the first embodiment.

[Effects] (1) A pair of switches M with a size sufficiently smaller than each element constituting the tri-state output buffer are installed in parallel with each element.
The switch MO is connected to the OSFET before driving the output buffer based on the data signal that determines the signal to be output.
When controlling the SFET to change the potential of the output pin from the "L" level to the "H" level, charge is gradually supplied to the capacitive load.

When the potential of the output pin is changed from the "H" level to the "L" level, the charge is gradually drawn from the output pin to the ground, and after the level of the output pin is determined to a certain extent, the output signal based on the data signal is output. Since the output buffer is driven by the control signal that controls whether to output or not, and the output is determined, the potential of the output pin becomes It.
Due to the effect that the rising edge when transitioning from the ``L'' level to the ``H1'' level and the falling potential when transitioning from the 11 Hu level to the ``II L'' level are gentle, many output pins simultaneously reach the ``HIt level'' or ``11'' level.
11L level noise (VOR) on other output pins fixed to ``H'' when set to ``L'' level and noise of ``H7 level'' (Voo peak) on other output pins fixed to ``L'' are reduced. This has the effect of being done.

(2) A second switch element is connected in series with each of the switch MOSFETs of a size sufficiently smaller than the switch MOSFET connected in parallel with each element constituting the tri-state output buffer, and directly inputs a data signal that determines the signal to be output, and the second switch MOSFET pair receives a signal that is the source of an output state control control signal that controls whether or not to output a signal based on the data signal. Since it is controlled by inputting (TSCE), there is no need to provide a logic circuit for forming a signal to control the switch circuit for each output circuit, and the switch elements that make up the switch circuit are small in element size. The effect of being able to be formed in a vacant area near the output buffer provides the effect that noise in the output signal can be reduced without increasing the chip size.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, Example 2 above
Now, of the elements constituting the newly added complementary MO5 configuration switch circuit, P-channel MO5FETM and N
The data signal IN is input to the gate of channel MO3FETM to control on/off, but the P-channel MOSFETM and N-channel MOSFETM4 outside
and a data signal IN to the gate of MOSFET M,
, M, (7) It is also possible to control the switch circuit by applying the T S CE signal to the gate.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to the complementary MO8LST such as a microprocessor, which is the field of application which is the background of the invention, but the present invention is not limited thereto. For example, N.M.O.
The present invention can be used in general semiconductor integrated circuits having a large number of output pins that change at the same timing, such as V.5 integrated circuits and bipolar integrated circuits.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a tri-state output circuit according to the present invention, FIGS. 2A and 2B are timing diagrams of the output circuit of FIG. 1, and FIG. 4A and 4B are timing diagrams of the output circuit of FIG. 3. FIG. 5 is a circuit diagram showing an example of a conventional output circuit. Figure 6A
5 and 6B are timing diagrams of the output circuit of FIG. 5. DESCRIPTION OF SYMBOLS 1...Output buffer, 2-5...Gate for control signal formation, 10...Switch element circuit, 11...
...Output pin, M1-M4...Switch element (switch MOSFET) + IN...Data signal, TS
C...Control signal. Fig. 1 Fig. 7゛〉■ Fig. 2A tW'' Bore 7-Bottle θ Fig. 2B, If'' specific force 4 now

Claims (1)

[Claims] 1. A tri-state output buffer, a control signal forming circuit that forms a control signal for controlling its output state, and a pair of large operating resistances connected in parallel with the elements constituting the output buffer. When the potential of the output pin is set to the "H" level, electricity is gradually supplied to the output pin through the switch element to increase its level, and the potential of the output pin is set to "L". ``When the level is set, the charge of the output pin is gradually drawn out through a switch element in advance, and then the output buffer is driven by the control signal to determine the output. Output circuit in. 2. The output buffer and switch element circuits are each composed of complementary MOSFETs, and the pair of switch elements are controlled by a signal corresponding to a data signal that is the basis of the control signal that controls the output buffer. An output circuit in a semiconductor integrated circuit according to claim 1, characterized in that the output circuit comprises: 3. A pair of switches M constituting the above switch element circuit
A second switch element is connected in series with each OSFET, the first switch MOSFET is provided with a data signal, and the second switch MOSFET is provided with a signal related to the output state control signal that is the source of the control signal. 2. The output circuit in a semiconductor integrated circuit according to claim 1, wherein the output circuit is configured to supply and control the output voltage.