JPH0338836A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a parasitic junction capacitance by a method wherein an oxide film layer by selectively implanting 0<+> ions into only a part directly under a parasitic base region. CONSTITUTION:An element region is formed selectively in a semiconductor substrate 1 of a first conductivity type; a region of a second conductivity type is formed selectively inside this element region; a second region of the first conductivity type is formed inside the region of the second conductivity type. An oxide film region 10 is formed by implanting 0<+> ions into a part directly under the region of the second conductivity type other than the second region of the first conductivity type. Thereby, a parasitic base capacity can be reduced sharply without being limited by a fine size; transistors of a conventional type which are rich in a technological inheritance can be used without especially adopting a self-aligned structure during this process; consequently, a greatly high performance can be realized technologically easily.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a bipolar transistor that has small parasitic capacitance and excellent high speed and high frequency characteristics.

[Conventional technology]

In recent years, with the development of computers and communications, the demand for high-speed, high-frequency devices has been increasing.

As a result, the performance of bipolar transistors has also been significantly improved. In order to improve the performance of bipolar transistors, it is necessary to realize shallow junctions, base resistance and parasitic capacitance (collector base).

It is important to reduce the collector-emitter capacitance (e.g. collector-emitter capacitance).

Among these, pattern miniaturization is an effective means for reducing base resistance and parasitic capacitance.

[Problem to be solved by the invention]

However, pattern miniaturization is limited by the eyelid exposure technology, and it is impossible to exceed the technical limits (resolution 2 overlay accuracy, etc.) at that time.

FIG. 5 shows the structure of a conventional bipolar transistor. As mentioned above, reducing parasitic capacitance for high performance requires
Although it is necessary to reduce the emitter width We and the base region width wb, there are certain limits to this. Furthermore, even if it were possible to reduce We and Wb with the best technology, the external base region 2 indicated by the dotted line in FIG.
0 actually does not contribute anything to the transistor operation and acts only as a parasitic capacitance, so it does not improve performance. However, this conventional bipolar transistor has undergone significant technological accumulation over the decades since the invention of integrated circuit technology by Kilby et al., and it is easy to take advantage of that legacy.

On the other hand, in order to overcome the drawbacks of conventional bipolar transistors, a transistor with a self-aligned structure as shown in FIG. 6 has recently been proposed and is showing excellent performance. However, in a self-aligned transistor, the overlapping of the P-type graft base 18 and the P-type intrinsic base 19 is extremely important, and since it is difficult to control this part, it has a different problem than the conventional type. There is. In addition, in the conventional method, there is a parasitic base region, that is, the graft base 1
8 is not large, but it is of a size that cannot be ignored as a parasitic capacitance, no different from conventional transistors.

To solve the problem of large parasitic capacitance in the base region, which is particularly noticeable in the conventional transistors mentioned above, the present invention forms an oxide film layer by selectively implanting 0+ ions only directly under the parasitic base region. The difference is that it reduces parasitic junction capacitance.

Furthermore, since a conventional transistor structure can be used in this case, past technological heritage can be utilized, and the problems described with self-aligned transistors do not exist.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes the steps of: selectively forming an element region in a first conductivity type semiconductor substrate; selectively forming a second conductivity type region within the element region;
forming a second first conductivity type region within the conductivity type region, and forming an oxide film region by implanting 0+ ions directly under the second conductivity type region other than the second first conductivity type region; The process includes the steps of:

〔Example〕

FIGS. 1(a) to (e) are cross-sectional views of a semiconductor chip for explaining a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of a semiconductor chip shown in FIG. 1(C).
It is a figure which shows the profile of the impurity along the AA line in FIG. In this example, disk! J-) (Single)
) shows an example of a transistor. First, as shown in FIG. 1(a), an n-type epitaxial layer 2 is elongated on an n+-type semiconductor substrate 1, and an oxide film 3 serving as an isolation region is formed. , B+ ions are implanted to form the base 5. As a method for forming the base, for example, the oxide film 4 may be removed and B+ ions may be directly implanted, or the oxide film 4 may be removed and then a gas diffusion method such as B (13) may be used. Grown film and SOG
Alternatively, boron may be added to (Spin On Glass) and used as a diffusion source.

Next, as shown in FIG. 1(b), a contact hole 6 is opened in the oxide film 4, and the polysilicon 7 doped with As (arsenic) is pre-coated, leaving only the region that will become the emitter. Etching. Here, the polysilicon 7 may be formed by implanting As+ ions into non-doped polysilicon, or by implanting As+ ions during vapor phase growth.
It may also be formed by adding. Here, 8 is a photoresist that serves as an etching mask, and 9 is, for example, 600
It is a thin oxide film of ~1000 layers. As for this oxide film, masking properties are improved if it is present, but there is no problem even if it is absent.

Next, as shown in FIG. 1C, 0+ ions are implanted using this resist 8 as a mask. The energy of ion implantation at this time is determined so that the O+ peak is slightly deeper than the depth Xj of B'' (P+ region), as shown in Figure 2.Here, the energy of 0+ ion implantation is By setting as described above, the position of the peak can be determined as shown in Fig. 2.At this time, by increasing the energy of 0+ ion implantation several times, the oxide film (SiOx) region 10 can be determined. The thickness T can be set arbitrarily. Therefore, when a thick oxide film region 10 is required,
The 0+ ion implantation may be performed by changing the energy in the energy range from several tens of KeV to several hundreds of KeV.

Next, as shown in FIG. 1(d), if the resist 8 is removed and annealing is performed at high temperature, the A
S is diffused to form an emitter 11, and damage caused by the O+ ion implantation is also repaired, and an oxide film (SiOx) region 10 of good quality and free of defects is formed at the interface with the base region 5. Thereafter, for example, B+ ion implantation and boron diffusion are performed using the oxide film 9 as a mask to reduce the base resistance and contact resistance, thereby forming a P+ type base contact 12. Of course, this step is not always necessary, and may be performed according to necessity.

Next, as shown in FIG. 1(d), as usual, the base electrode 13B, the emitter electrode 13E and the collector electrode 13
C is formed to complete the transistor.

FIG. 3 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention, and is an example of application to a semiconductor integrated circuit.

First, as shown in FIG. 3(a), after forming an n+ type region 15 which will become a buried collector layer in a P type semiconductor substrate 14 and growing an n type epitaxial layer 2, for example, by selective oxidation method. An oxide film 3 for element isolation is formed, and an n+ type region 16 (collector raising part) is selectively formed in the oxide film 4 over the element region.

Next, as shown in FIG. 3(b), after this, for example, using the photoresist 8 as a mask, B+ ions are selectively implanted to form the base region 5.

At this time, it goes without saying that the method for forming the base is not limited to B+ ion implantation as described in the first embodiment.

After this, as shown in FIG. 3(c), the process is roughly the same as in the first embodiment, and along with the formation of the emitter 11, an oxide film region 10 is formed by O+ ion implantation directly under the external base. The formation conditions (energy, dose, etc.) for this O+ ion implantation are also determined in the same manner as in the first embodiment. The same applies to forming the P+ type base contact 12 for reducing base resistance.

FIGS. 4(a) and 4(b) are cross-sectional views of a semiconductor chip for explaining a third embodiment of the present invention, which is an example of application to a self-aligned transistor.

First, as shown in FIG. 4(a), after forming an n-type epitaxial layer 2 on an n++ semiconductor substrate 1 and forming an isolation oxide film 3, a P-type polysilicon 17 doped with boron, for example, is formed. After growing the second oxide film 9 by selectively etching the region to become the emitter, a P+ type region which will become the graft base 18 is formed by high-temperature annealing. After that, a P+ type intrinsic base 19 is formed, for example, A
Polysilicon 7 containing s is selectively left using resist 8 as a mask.

Next, as shown in FIG. 4(b), O+ ions are implanted in the same manner as in the first embodiment, and the oxide film (SiOx) region 1 is
0 is formed, and an emitter 11 is formed by high-temperature annealing, completing the necessary diffusion process. After this, the base contact 21 on the P-type polysilicon 17 is opened.

According to the present invention, a self-aligned transistor can be constructed on a semiconductor integrated circuit in the same manner as in the second embodiment. Further, in the above example, an NPN) transistor was used as an example, but it goes without saying that a PNP) transistor can also be used.

〔Effect of the invention〕

As explained above, in the present invention, by implanting 0+ ions directly under the external base region other than the emitter region,
Parasitic base capacitance can be significantly reduced without being limited by miniaturization. Moreover, at this time, it is possible to use conventional transistors with a rich technical heritage, without having to specifically adopt a self-aligned structure, so that a dramatic increase in performance can be achieved technically with great ease.

Of course, since the main focus of the present invention is to reduce externally based parasitic capacitance, as described in the third embodiment,
It is also clear that performance can be improved by using it in self-aligned transistors.

[Brief explanation of drawings]

1(a) to (e) are cross-sectional views of a semiconductor chip for explaining a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of a semiconductor chip for explaining a 10-2 and a third embodiment of the present invention. 5 and 6 are cross-sectional views of a semiconductor chip for explaining a conventional example. DESCRIPTION OF SYMBOLS 1...N+ type semiconductor substrate, 2...N type epitaxial layer, 3...Isolation oxide film, 4...
... Oxide film, 5 ... Base, 6 ...
...Contact hole, 7...Polysilicon, 8.
...Resist, 9...M ([,], 0
...Oxide film (SiOx) region, 11...
・Emitter, 12...Base contact, 13
B...Base electrode [i, 13E...Emitter electrode, 13C...Collector electrode, 14...
...P type semiconductor substrate, 15...N+ type buried collector region, 16...N+ type collector pulling part, 17...P type polyester doped with poron. Silicon, 18...P+ type graft base, 19.
... P+ type intrinsic base, 20 ... external base region, 21 ... base contact.

Claims (1)

[Claims] a step of selectively forming an element region in the first conductivity type semiconductor substrate; a step of selectively forming a second conductivity type region in the element region; and a step of selectively forming a second conductivity type region in the second conductivity type region. The method is characterized by comprising a step of forming a conductivity type region, and a step of performing O^+ ion implantation directly under the second conductivity type region other than the second first conductivity type region to form an oxide film region. A method for manufacturing a semiconductor device.