JPH02199868A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce a capacitance between a base and an emitter due to a minimum emitter and to operate at a high speed by covering the surface and side face of the electrode material of an emitter electrode in contact with an emitter region through a contact hole opened at a hollow region of the electrode material with insulating films to insulate. CONSTITUTION:An oxide film 12 is formed on an element forming region 7 of a bipolar transistor, an impurity-doped polysilicon and subsequently an Si3N4 film are grown, and a polysilicon electrode 19 covered on the surface with an Si3N4 film 18 then remains by etching. The polysilicon electrode 19 is so disposed in a frame shape as to surround a region 20 to become an emitter so that a hollow region is contained in a base region 10. Then, a PSG film 34 is grown on a substrate, and etched to form a sidewall oxide film 21 of the polysilicon electrode 19. The substrate is coated with a photoresist 22, a window is opened at a slightly wider region 25 than the region to become the emitter, and As ions are implanted. In this case, As is implanted to the base region 10 through the oxide film 12 at a part of an arrow 31 of the region 20, and an emitter layer 26 of minimum size can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor integrated circuit device in which a bipolar transistor and a MOS transistor are formed on the same substrate, and a method for manufacturing the same.

[Prior Art] The technology of forming a bipolar transistor and a MOS transistor on the same substrate is now widely known. In particular, CMOS transistors are
D D (Lightly Doped Drain
) structure is attracting attention (for example, literature 1)
:L, 0μm n-cell CMO3/Bip
olar Technology IEEETRA
NSACTION ON ELECTRON DEVI
CE, VOL, ED-32NO2Feb, '85, or Document 2: ^n Enhanced FullyS
caled 1.2-, US C] 10S Proce
ss For Analog Application
s IEEE Journal o! 5olid-s
tate circuits, VOL, 5C-21
, NO2April' 86). Here, referring to the manufacturing method of BiCMO5 structure disclosed in the above-mentioned document, the prior art will be explained using FIG. 2.

First, as shown in FIG. 2(a), a P-type silicon group is formed.

A N0 buried layer (sheet resistance 20Ω10 by s b diffusion, depth of diffusion 5μm) 102 is formed on a plate ((100) plane, resistivity 10LcIIIHO1), resistivity 1.OΩ・cI1
1. A P-type boron-doped epitaxial layer 103 having a thickness of 2.0 μm is formed.

After that, N region 1 forming a bipolar transistor is formed.
04 and the N region 105 forming the PMO3 transistor.
is formed at the same time with a surface concentration of 2×10″1 ons/c@3° and a diffusion depth of 2 μm, and is continuous with the N0 buried layer 102 buried in advance.

Furthermore, 7,000 LOCO3 oxide films 106 are formed in the field area using the LOCO3 method.

Note that the element formation region 10 without the LOGO8 oxide film 106
Reference numerals 7, 108, and 109 are regions for forming bipolar transistors, NMOS transistors, and PMOS transistors, respectively.

Next, as shown in FIG. 2(b), P was deposited on the surface of the substrate to form the base of the bipolar NPN transistor.
The surface concentration of the type diffusion layer (base region) 11O is 5
O"1 ons/am3. After forming the diffusion to a depth of 0.5 μm, a gate oxide film 111, which will become the gate insulating film of the MOS transistor, is formed to a thickness of 200 μm. At the same time, a Sin film 112 is formed with the same thickness of 200 layers.

Subsequently, as shown in FIG. 2(C), a polysilicon film was grown on the substrate surface to a thickness of 4000 nm by low pressure CVD, and N was etched by well-known photolithography and etching techniques.
Gate electrode 113 of MO3 transistor. After forming the gate electrode 114 of the PMOS transistor, the low m degree N-drain region 115 of the NMOS transistor (with a surface concentration of 4 x 10" 1 ounces) is formed using self-line technology.
/cm', diffusion depth 0.2 μm).

Further, as shown in FIG. 2(d), p,
o. A PSG film 154 having a weight concentration of t5wt% is grown by 4000 people using the CVD method.

Next, as shown in FIG. 2(e), the PSG film 154 is etched by RIE (reactive ion etching) to form a sidewall oxide film (sidewall) 116 necessary for forming the LDD structure on the polysilicon gate electrode 113, 114. This LDD structure and its manufacturing method are described in, for example, "Ultra High Speed MOS Devices" edited by Takuo Kanno and edited by Susumu Kayama, Baifukan, pages 40 to 41, so a detailed explanation will be omitted here.

Further, as shown in FIG. 2(f), a thickness of 1 mm is applied to the surface of the substrate.
, 0 μm negative type photoresist (negative resist) 117, and windows are opened in the regions 118 and 119 that will become the emitter and collector of the bipolar transistor and the region 120 that will become the source and drain of the NMO3 transistor using the well-known photoringraph technique. The acceleration voltage was set to 40 K eV using the ion implantation method.
Inject As in an amount of 1.2×10”1 ons/cm”.

At this time, by performing ion implantation using the resist 117 as a mask, the emitter 121 and collector 122 of the bipolar NPN transistor and the sources and drains 123 and 124 of the NMOS transistor are formed simultaneously.

Further, as shown in FIG. 2(g), after removing the resist 117 on the substrate, a negative resist 125 is applied to a thickness of 1.0 mm.
µm coating, windows are opened in the extraction region 126 of the base contact of the bipolar transistor and the region 127 which will become the source/drain of the PMO3 transistor using the well-known photolithographic technique, and BF is applied using the ion implantation method, and the acceleration voltage of 50 K eV, D osef
Inject 1 oz/am of fi 3 X l O. By ion implantation using this resist mask, the base contact extraction region 128 of the bipolar transistor and PM
Sources and drains 129 and 130 of the OS transistors are formed.

Finally, as shown in FIG. 2(h), after removing the resist 125, the PSG film 131 as an interlayer insulating film is
The base contact hole 132 of the bipolar transistor is grown using the VD method to a thickness of 6,000 yen at a concentration of 20 wt% and a glass flow (flattening by heat treatment). Emitter contact hole 133. Collector contact hole 134, NMOS transistor source contact hole 135. Drain contact hole 136° A source contact hole 137 and a drain contact hole 138 of the PMOS transistor are simultaneously opened, and the base electrode 13 of the bipolar transistor is opened.
9. Emitter electrode 140. Collector electrode 141 and NM
O3 transistor source electrode 142° drain'1 pole 143. PMOS transistor source electrode 144. Drain electrodes 145 are each formed using AQ, and BiCMO8
The structure is completed.

[Problems to be Solved by the Invention] However, the semiconductor integrated circuit device having the above structure has a drawback in that a bipolar NPN transistor capable of high-speed operation cannot be formed for the following reason.

In general, the operating speed of a bipolar NPN transistor is determined by the current gain-bandwidth product ((gain-band width)
or cut-off frequency (cut-oCf' frequency)
cy), hereinafter expressed as fT), and fr is thick (
I see, high-speed operation is possible. This f7 is 1/(2πfT)=τe×τb+τx+ r c−-■
It is expressed as For details, please refer to reference books such as "Ultra-high-speed digital devices, ultra-high-speed bipolar devices" edited by Takuo Kanno and edited by Minoru Nagata, published by Baifukan, etc., but fT can be improved by reducing each term on the right-hand side of the above equation (■). High-speed operation can be obtained. Particularly in the low current region, the first term is said to be dominant (page 45, line 9 of the same book), and this first term τe (charging/discharging time constant of the emitter-base junction) is T e = (k T / q I E )CTE・” ”
・■Here, CTll: Base-emitter junction capacitance: Borckmann constant (constant) q: Amount of ii load (constant) T: Temperature 0K I8: Given by emitter current. If the temperature is constant, the base-emitter junction capacitance is small (as fT is large, high-speed operation is possible).

The reason why the low current range is particularly problematic here is as follows. Taking as an example the basic circuit of a gate constituting an LSI circuit with a BiCMO3 structure, such as a two-man NAND gate, the circuit configuration is shown in FIG. That is, the input stage is the 0M03 part, and the output stage is the 0M03 part which is the input stage of the next stage gate by a bipolar transistor.
It is designed to drive parts. In this way, the gate output drives 0M with high input impedance.
03, even if the fan-out is large, a relatively small drive current or sink current for charging and discharging the load capacitance is sufficient.

In other words, it is sufficient if the bipolar transistor can quickly start up in the low current range. This means increasing fT in the low current range, which is sloping to the left in Figure 4, and this makes high-speed operation possible, so the low current range is particularly important as mentioned above. It is.

By the way, the base-emitter junction capacitance C711 is given by the base region (P type) 110 and emitter region (N type) 121 shown in FIG. 2(h). 11th
In the figure, a portion including this emitter region 121 is enlarged and shown three-dimensionally. Here, 103 is an N-epitaxial layer, 110 is a P-type base region, and 121 is an N-type emitter region formed in this base region 110. This N-type emitter region 121 forms a PN junction and at the same time has a junction capacitance CTII on a surface in contact with the P-type base region 110.

If this CTB is further divided into components, Ctg” component element of C base component of CIi = Cr
+C,...■ That is, CIi indicated by diagonal lines in the figure
ff1fl(Cs) l 46 and the component of the bottom surface of C (CT
) can be divided into 147i pieces.

For example, this Ctg has an emitter area of 2°8 μm.
Considering an emitter region of 7) iT
[)-(2.8μmX2.8μm)/(0.3μmX2
．． 8μm×4)ζ2.3
......As shown in formula 00, the area of the bottom surface is approximately 2.3 times that of the side surface, and the area of the bottom surface, that is, the emitter area geometrically viewed from directly above the emitter region 121. It can be seen that it greatly depends on the area.

(-) In order to improve the operating speed of a transistor, that is, fT, it is necessary to manufacture a transistor with as small an emitter area as possible.

However, with conventional technology, even if an attempt is made to form a transistor with as small an emitter area as possible, the emitter area is controlled by the size of the contact hole formed in the emitter, making it difficult to form a transistor with a small emitter area. there were. The reason for this will be explained below using FIG. 6.

Generally, in the manufacture of semiconductor integrated circuit devices, the minimum resolution capability of the manufacturing line is often called the design rule for integrated circuit patterns. This will be explained first.

Assuming that the minimum line resolution is 1.2 μm, each of the contact holes 132 to 13 shown in FIG. 2(h)
8, or the polysilicon gate electrodes 113, 114, etc. shown in FIG. 2(c) have this minimum resolution dimension of 1.8.
It becomes possible to form the film with a thickness of 2 μm. Also, in order to actually reduce the size of integrated circuits as much as possible (this increases the number of integrated circuits that can be obtained from one silicon wafer,
As a result, costs are reduced. ), these dimensions are often designed with minimum dimensions, and as a result, the contact holes 132 to 138 shown in FIG. 2(h) and the contact holes 132 to 138 shown in FIG. 2(C)
The polysilicon gate electrodes 113 and 114 shown in FIG.
Designed in μm. In this case, designing the mask pattern of this integrated circuit with a thickness of 1.2 μm is called the 1.2 μm design rule.

In the case of this 1.2 μm design rule, the minimum resolution pattern is 1.2 μm and 81.2 μm, so Fig. 6(a)
The size of the contact 148 shown in FIG. 1 is designed with its minimum resolution pattern. The emitter 149 is made one rotation larger than the contact 148, and the distance (alignment margin) between the contact 148 and the emitter 149 is maintained at any position.
2.8μm x 2.8μ so that 150 is 08μm or more
It is designed with a size of m.

Therefore, field = t for 1,2 μm design rule.

Bipolar N with emitter area of 2μm x 1.2μm
Rather than forming a PN transistor, the minimum emitter area is increased to 2.8 μm×2.8 μm.

This makes it difficult to form a transistor that operates at high speed, as explained earlier.

Conventionally, as a method for reducing the emitter area, one method is to reduce the alignment margin of 0.8 μm by mask alignment between the emitter 149 and the contact 148 shown in FIG. 6(a), as shown in FIG. 6(b). For example, 2.
It is also possible to form an emitter 151 of 0 μm×2.0 am. However, in the semiconductor manufacturing process, this may occur due to misalignment of the mask and the contact position relative to the emitter 151 position is 15 where it should be, as shown by the dotted line.
If the position shifts by 0.6 μm to the right from 2 and becomes position 153 shown by the solid line (this is a well-known fact in the semiconductor manufacturing process, the alignment margin between the two masks is generally
Although this depends on the accuracy of the mask alignment device, it is necessary to have at least 0.8 μm or more. ) The contact hole 154 protrudes from the emitter 151. Therefore, if a metal electrode is buried in this contact hole 154 in a subsequent process, the emitter-base junction will be short-circuited, causing abnormal transistor operation depending on the amount of misalignment, which will reduce the yield of the integrated circuit. was decreasing.

Another method is to use self-line technology (DOPOS transistor formation technology) using an oxide film and a polysilicon film to achieve a minimum design rule of 1.2 μm.
The technology to obtain an emitter area of 81.2 μm is also described in document 3:
IEEE TRANSACTION 0NELECT
RON DEVICES VOL ED34 NO6J
une1987 P1304-1309, etc. This is because if only the self-line technology using an oxide film is used, there is a risk that contact deviation as shown in FIG. 6, which has already been explained, may occur, so a second polysilicon process is added.

Therefore, a new process is required to open a window for the emitter and to pattern the polysilicon formed on the emitter. This will be explained in detail with reference to FIG. 7, especially the process of forming the emitter of a BiCMO8 bipolar NPN transistor.

The process shown in FIG. 7(a) corresponds to the stage shown in FIG. 2(b) in FIG.
After forming the gate oxide film 207, a gate oxide film 208 which becomes the gate of the NO3 transistor is formed.

Next, a window is opened in the gate oxide film 208 for emitter positioning. The size of this window 211 is 1.2 μm (FIG. 7(b)).

Next, in addition to forming a gate electrode using a polysilicon film for the gate in the 0M08 section, a second polysilicon film 309 is formed.
is grown over the entire surface of the substrate (FIG. 7(C)).

Further, As ions for forming an emitter are implanted from above this polysilicon film 309 using the self-line technique using the remaining oxide film 208 as a mask (FIG. 7(d)).

Next, patterning is performed on the polysilicon film 309 to make a base contact, and the emitter region is left and other parts are etched off. As a result, a polysilicon electrode 251 is formed (FIG. 7(e)).

Then, the As remaining in the polysilicon film 309 is pushed out through the window 211 into the base region 207 by thermal diffusion.
An emitter region 214 is formed.

At this time, an oxide film 300 is formed on the surface of the polysilicon electrode 251 (FIG. 7(r)).

Finally, an emitter contact hole 222 is formed in the oxide film 300.
A hole is opened and an A12 emitter electrode 227 is formed on the polysilicon electrode 251 within the window 222 to complete the BiCMO3 structure (FIG. 7(g)).

As described above, in this conventional example, the emitter region 214
The emitter contact hole 222 is not made above, but is made in the oxide film 300 on the polysilicon electrode 251. Therefore, even if the position of the contact hole 222 shifts, the position of the hole 222 on the polysilicon electrode 251 only moves, so that the problem of base-emitter short circuit as shown in FIG. 6(b) is eliminated. Therefore, using the self-line technology using the oxide film 208 as a mask, a 1.2 μm×
It becomes possible to obtain an emitter area of 1.2 μm.

However, since the number of masks increases by at least two steps (FIGS. 7(b) and 7(e)), this increases the cost of the semiconductor device.

Furthermore, since the emitter electrode 227 is in contact with the emitter via the polysilicon electrode 251, the emitter electrode 227
The contact resistance, that is, the emitter resistance, is greater than that in which the emitter 7 is in direct contact with the emitter. The emitter resistance is ■
Since it corresponds to the part in the parentheses on the right side of the equation, it is thick (therefore, τe becomes large, and as a result, fr decreases).

The purpose of the present invention is to utilize the self-line technology used in the MO8 process as is, to reduce the emitter area without increasing the number of mask steps, thereby solving the problems of the conventional technology described above, and achieving high-speed operation. An object of the present invention is to provide a semiconductor integrated circuit device in which a bipolar transistor can be formed on BiVO4, and a method for manufacturing the same.

[Means for Solving the Problems] The semiconductor integrated circuit device of the present invention has a BiMO3 structure in which a bipolar transistor and a MOS transistor are formed on the same substrate, in which the electrode material forming the gate electrode of the MOS transistor is the same as that of the bipolar transistor. is arranged on the base region of the electrode material with an insulating film interposed therebetween, and has a geometrically closed frame shape when the electrode material is viewed from above, and at least a hollow region of the electrode material having the frame shape. is within the base area.

Further, the surface and side surfaces of this frame-shaped electrode material are covered with an insulating film, and an emitter region is provided in a hollow region surrounded by the frame-shaped electrode material covered with this insulating film, An emitter electrode is in contact with the emitter region through a contact hole made in the punched region.
The electrode material is insulated from the electrode material by an insulating film covering the surface and side surfaces of the electrode material.

Further, in the method of manufacturing a semiconductor integrated circuit device of the present invention, a semiconductor substrate having at least a bipolar transistor region and a MOS transistor region of the same conductivity type as the bipolar transistor formed in this region is prepared, and a collector is provided in the bipolar transistor region. After forming a base region in the region and the collector region and forming an insulating film on the surface of the semiconductor substrate thus formed, a gate electrode is formed in the MOS transistor region, and at the same time, the electrode material for forming the gate electrode is formed. A closed frame-shaped mask body is formed in a region on the base region where an emitter is to be formed.

Thereafter, an insulating film is formed on the surface and side surfaces of the gate electrode and the mask body, and ions are implanted into a hollow region surrounded by a frame-shaped mask body having at least the insulating film, using the mask body as a mask to form an emitter. At the same time as forming the regions, ions are selectively implanted into the regions where the source and drain of the MOS transistor are to be formed.
The source and drain regions of the transistor are formed, and then, using the mask body as a mask, an emitter contact hole is formed in a hollow region surrounded by the mask body.

Further, in the integrated circuit device and the manufacturing method thereof, the MoS transistor has an LDD structure, and the insulating film formed on the side surface of the gate electrode and the electrode material or the mask body is a sidewall necessary for the LDD structure. You can also do it.

MOS of the same conductivity type as the bipolar transistor mentioned above
For example, a bipolar transistor is an NP transistor.
If it is an N type, it becomes an N channel type MOS transistor.

Further, the semiconductor substrate having at least a bipolar transistor region and a MOS transistor region of the same conductivity type as the bipolar transistor formed in this region means that it can also be applied to a semiconductor substrate having a MOS transistor region of the opposite conductivity type.

Similarly, an emitter region is formed by implanting ions into a hollow region surrounded by a frame-shaped mask body having at least the insulating film, using the mask body as a mask, and at the same time, an emitter region is formed in the region where the source/drain of the MOS transistor is to be formed. Forming the source/drain regions of the MOS transistor by selectively implanting ions into the area, and then forming an emitter contact hole in the hollow region surrounded by the mask body using the mask body as a mask means that the source/drain regions of the MOS transistor are formed by selectively implanting ions in the area other than these regions. This means that it is also possible to form

[Is the working coemitter contact hole equal to the emitter area?
If it is thicker than this, it becomes possible to form the emitter region with the minimum size.

Furthermore, when opening an emitter contact hole directly in the emitter region, if the mask material used to position the emitter region is not etched with the etching solution used to open the emitter contact hole, the contact hole will open only in the emitter region and will not open in the base region. won't open.

The present invention has been made based on the above-mentioned findings.

The electrode material used for the gate electrode of the MO transistor is used as a mask for positioning the emitter of the bibolar transistor. Therefore, at least there is no increase in the number of masks.

Then, by using the hollow region surrounded by the frame-shaped mask body as an emitter region, the emitter and emitter contact hole of the bipolar transistor are formed by self-alignment. The emitter contact hole is formed to be as large as or larger than the emitter region. Even if a contact hole of such a size is formed, since the electrode material is not etched, the contact hole will not open in the base region.

When forming the emitter and emitter contact hole, if an insulating film is formed on the side surface of the frame-shaped mask body, the hollow area will be narrowed by the thickness of the insulating film in the width direction. It is possible to form a bipolar transistor with a larger emitter area compared to the conventional method.

Furthermore, by forming an insulating film on the surface and side surfaces of the gate electrode and the mask body in advance (this prevents a short circuit between the emitter electrode of the bipolar transistor and the conductive mask body used for positioning. - Oxide film capacitance between bases is reduced.

[Example] The present invention will be described in detail below with reference to FIGS. 1(a) to (h) and FIGS. 8 to 12.

FIG. 1 shows a manufacturing process for forming a bipolar NPN transistor and a CMOS transistor having an LDD structure on the same substrate using the present invention.

First, as shown in FIG. 1(a), a P-type silicon substrate ((
100) surface, specific resistance 10 (hcm) 1 and N buried layer (sheet resistance 20Ω with Sb diffusion 10.Diffusion depth 5μ
m)2, with a specific resistance of 1. OQ-cm2. O
P-type boron-doped epitaxial layer 3 with a thickness of ttm
form. Next, an N region 4 forming a bipolar transistor and an N region 5 forming a PMOS transistor are formed.
is simultaneously formed with a surface concentration of 2 x 10'' 1 ons/cm3 and a diffusion depth of 2 μm, and is made continuous with the iN+ buried layer 2 which is buried in advance.Furthermore, a LOGO3 oxide film 6 is formed to a thickness of 7000 nm by the LOCO8 method.

Note that the element formation region 7.8. in which the LOCO8 oxide film 6 is not provided.
9 are bipolar transistors.

This is a formation region for an NMOS transistor and a PMO3 transistor.

Next, as shown in FIG. 1(b), a P-type diffusion layer 10 for forming a base of a bipolar transistor is formed on the entire surface of the substrate at a surface concentration of 5×10”1 ons/C@3.
．． After forming the diffusion to a depth of 0.5 μm, a gate oxide film 11, which will become the gate insulating film of the MOS transistor, is deposited at a depth of 200 μm.
Form with the thickness of a person. At this time, the oxide film 12 is also applied to the element formation region 7 of the bipolar transistor to the same thickness 2.
It is formed by 00 people.

Next, as shown in Figure 1 (C), a polysilicon film doped with impurities was grown to a thickness of 4000 nm by low-pressure CVD, and subsequently Si, N, and films were grown to a thickness of 2000 nm. Later, using well-known photolithography and etching techniques, the surface portions were made to have 5i2N and 13 and 14 layers, respectively.
Polysilicon gate electrode of the NMOS transistor covered with 15. A polysilicon gate electrode 16 of a PMOS transistor is formed. At this time, a polysilicon electrode 19 whose surface is covered with an S;sN4 film 18 is also left in the bipolar transistor region.

Note that the growth of the Si, N, and films described above is based on an LDD structure MOS.
This is a step that is not present in the process, and the number of steps increases in this respect, but it does not involve an increase in the number of masks, which is a problem in manufacturing semiconductor integrated circuit devices.

The shape of the polysilicon electrode 19 left in the above-mentioned bipolar transistor region will be explained using FIG. 8.

FIG. 8 is an enlarged three-dimensional view of the base portion of a bipolar NPN transistor. A polysilicon electrode 19, which is used for emitter positioning and has a Si, N4 film 18 on its surface, is closed on the base region 10 and geometrically surrounds a region 20 that will become an emitter in the future when viewed from above. Place it in a frame shape. Furthermore, at least the hollow region of the frame-shaped polysilicon electrode 19 is arranged to fit within the base region IO.

The reason why the hollow region is placed within the base region 10 in this way is to avoid a short circuit between the base and the emitter.

Furthermore, although the polysilicon electrode 19 has a hollow square shape in the illustrated example, this shape is the same as the emitter shape, so if the emitter is a circle, it will be a circle, and therefore, the shape is not limited. The dimensions of the region 20 that will become an emitter in the future will be further explained using FIG. 9.

FIG. 9 shows a polysilicon electrode 19 (and it has 5
i3N418) viewed from directly above. As explained in the conventional example, in the integrated circuit manufacturing process, the minimum resolution capability of the line is generally called the design rule.
For example, in a line to which the 1.2 μm rule is applied, the width W1 of the hole shown in FIG. 9 is also the width W of the remaining Si3N, polysilicon with film! It is also 1.2 μm. In other words, in this process 1.
2 μm x l.

It becomes possible to form a polysilicon window 70 for a minimum emitter of 2 μm.

Now, returning to FIG. 1(c), the area other than the PMOS transistor element formation region 8 is covered with resist, and the LOCO3 structure is formed using the self-line technique (the low concentration N-drain region 17 of the PMO3 transistor is formed on the surface). Concentration 4
X 10” tons/am3.Diffusion depth 0.2μm
to form.

Next, as shown in FIG. 1(d), P was applied to the substrate.

0. A PSG film 34 having a weight concentration of 15 wt % is grown to a thickness of 4,000 yen by CVD.

Furthermore, as shown in Fig. 1(e), PS
The G film 34 is isotropically etched to form polysilicon gate electrodes 15, 16 . Polysilicon'l pole 19° sidewall oxide film,
That is, the sidewall 21 is formed.

Then, as shown in FIG. 1(f), a thickness of 1 μm was applied to the above substrate.
A region 231, which will become the collector of a bipolar transistor, and a region 24, which will become the source and drain of an NMOS transistor, are coated with a negative-type photoresist 22 of 23. A window is opened in a region 25 that is slightly wider than the region that will become the emitter, and an acceleration voltage of 40 KeV is applied using the ion implantation method.
Inject 2X IO"1 ons/cIa" of As.

This allows the emitter 26 of the bipolar transistor to
．． Four collector 27° NMOS transistor source/drain regions 28 and 29 are simultaneously formed.

At this time, in the NMOS transistor, LOGO
The region 30.31 of the trioxide film not covered with the photoresist 22 and the polysilicon electrode 15 having the side wall 21 are automatically positioned using self-alignment lines, and the source/drain 28.29 is formed. Ru. Also, the emitter 26 of the bipolar NPN transistor
A polysilicon electrode 1 having sidewalls 21 on its side walls
It is formed only in the area automatically positioned by 9.

The automatic positioning of the emitter 26 mentioned above will now be explained in more detail using FIG. 10.

FIG. 10 is an enlarged cross-sectional view of the area around the polysilicon electrode 19 on the bipolar transistor element formation region. In the figure, 1.2, 4, 10.12, 18.19
, 22, and 26 are the same as in FIG. 1, so detailed explanation will be omitted here. As ions are implanted into this portion at an accelerating voltage of 40 eV as shown by the arrow. At this time, As is implanted into the base region 10 through the 200-layer oxide film 12 in the window area 20 surrounded by the polysilicon electrode 51 and indicated by the arrow 32.
An emitter layer 26 is formed. However, the window opening shown by the arrow 33 is located outside the sidewall 21 outside the region 20.
Alternatively, a polysilicon electrode 19 covered with a Si3N film 18. As is masked by the resist 22, As cannot reach the base layer IO.

In this way, when the minimum dimension, for example, 1.2 μm design rule, the emitter layer 26 whose − side is 1.2 μm or less
can be formed.

The first reason why this emitter of 1.2 μm or less can be formed is explained below.
This will be explained using Figure 1.

FIG. 11 shows a further enlarged view of the emitter section in FIG. 10. As explained above with reference to FIG. 9, the removal width Wl and the remaining width W of the polysilicon for positioning the emitter can all be 1.2 μm. As explained in FIGS. 1(d) to 1(e), a PSG film 34 is grown on this, and the PSG film 34 is isotropically etched by RIE, so that the width W3 of the sidewall 21 is, for example, 0.2 μm. Obtainable. Incidentally, this width W can be arbitrarily selected by setting the film thickness of the PSG film and the RIE etching condition of 2 hours.

In this way, if w, = Q, 2 μm is obtained, the emitter aperture size is w, -2xw, = 1.2 - 2x0.2 = 0.8 μm, which is smaller than the 1.2 μm design rule. 0.8μ
An emitter with an aperture size of m can be formed.

Next, returning to FIG. 1(g), the above-mentioned substrate is coated with a thickness of 1 μm.
coated with negative type photoresist 34,
Base contact regions 35 and 5. of the bipolar transistor are formed by well-known photolithographic techniques. A window is opened in the source/drain region 36 of the PMOS, and B F t+ is accelerated at a voltage of 50 Key, D o by ion implantation.
Inject se amount 3 x 10 l5ions/cm'.

By ion implantation using this resist mask, the base contact extraction region 37 of the bipolar transistor and the PMO
S sources and drains 38 and 39 are formed.

Finally, as shown in FIG. 1(h), a PSG film 54 as an interlayer insulating film is deposited by CVD at a concentration of 20
After growing to a thickness of 6,000 vt% and glass flow, a base contact hole of a bipolar transistor 40. Emitter contact hole 411 Collector contact hole 42 NMOS transistor source contact hole 43, drain contact hole 44
．． PMOS transistor source contact hole 45
．． A drain contact hole 46 is simultaneously opened,
Base electrode of bipolar transistor 47. Emi.

Ta electrode 48. Collector electrode 49 and source electrode 50 of the NMOS transistor. Drain electrode 51°PMO
Source electrode 52 of S transistor. Drain electrodes 53 are formed using AQ to complete the B1CMOS structure.

Now, how to form the emitter contact hole 40 of the bipolar transistor will be explained using FIG. 12. Regarding the reference numerals in the drawings that are the same as those used in FIGS. 1 and 8 to 11, individual explanations will be omitted here.

When opening a window in the contact region 55 by contact photolithography and etching, a resist 56 is coated on the substrate surface, and a window is opened in the contact region 55 using a well-known photolithography technique. At this time, the width of the contact region 55 is the same minimum dimension as the emitter previously opened in the polysilicon electrode 19, and in this embodiment, the width is 1.
．． Although it is possible to open the window with a diameter of 2 μm, it is preferable to open the window with a dimension slightly larger than this dimension, for example, 2.0 μm, so as to largely surround the emitter aperture region 57 as shown in the figure.

This is because when the resist is formed with a minimum dimension of 1.2 μm and there is a misalignment of, for example, 0.8 μm in the mask alignment process, the position 60 of the resist when the misalignment is in the direction of the arrow 59, and the opening Hole size 58 is 1
．． As is clear from the fact that the diameter is 2 μm, only narrow contact holes are formed, and the contact resistance is large (
This is because problems such as

Then, by etching away the PSG film 54° oxide film 12 in the shaded portion 61 using isotropic etching, an emitter contact opening width 62 approximately equal to the inter-emitter hole width 57 can be obtained. This etching uses isotropic etching, so the sidewall 2
The side surface of 1 is only slightly etched as shown by the broken line 63 in the figure, and the opening width 62 does not exceed the diffusion region 26. For example, the depth 64 of the emitter 26 diffused during glass flow heat treatment (indicated by an arrow in the figure) is 0.1
If it is 5 μm, the spread of diffusion in the lateral direction (indicated by arrow 65 in the figure) is generally considered to be 0.15 μm x (60 to 70%), so it is 0°095 to 0.105 μm.
It is unlikely that the aperture width 62 extends beyond the emitter diffusion region 26.

In this way, by using the present device and the present method, the emitter and contact hole of a bipolar NPN transistor can not only be automatically positioned with almost the same size and shape, but also with a size that is less than the minimum photoresolution size. Can be formed.

Further, in this structure, the Si, N, film 18 as an insulating film is formed in advance on the polysilicon electrode 19, so that the emitter electrode 48 and the polysilicon electrode as a conductive film are then formed in the contact hole 41. 19 is insulated, and the presence of this S L3N Ji 18 prevents a short circuit between the emitter electrode 48 and the polysilicon electrode 19 that would occur when this film 18 was not present. Therefore, the junction capacitance formed by the junction between the emitter 26 and the base 10 due to the fact that the polysilicon electrode 19 is at the same potential as the emitter 26, and the junction capacitance formed by the junction between the emitter 26 and the base 10,
0 and MO3 capacity are effectively prevented. As a result, there is no problem of a decrease in ft due to the polysilicon electrode.

Note that in the above embodiment, the bipolar transistor is CM
We have described the case where it is formed on the same substrate as O3, but when combined with CMO3, the power consumption is particularly low, and therefore the current required for the bipolar transistor is small, so high-speed operation is most effectively achieved. I have to do it because I can.

However, it is sufficient that the combination with the bipolar transistor is a MoS transistor using a silicon gate process. Therefore, the combination with bipolar transistors is not limited to CMO3, but as long as a silicon gate process is adopted, NMO3
, PMO3DMO3, various combinations are possible.

Further, in the above embodiment, the bipolar transistor is NP
Although the description has been made for an N transistor, it can also be applied to a PNP transistor in the sense of reducing the emitter area.

Note that although polysilicon is used as the gate material in the present invention, a material equivalent to this, such as silicide or polycide, may be used.

[Effects of the Invention] Since the present invention is configured as described above, it produces the following effects.

In the device according to the first aspect, since the emitter of the bipolar transistor and its contact hole are positioned by self-alignment lines using an electrode material whose front and side surfaces are covered with an insulating film, the smallest emitter can be formed. In addition, the insulating film covering the surface and side surfaces of the electrode material prevents short circuits between the emitter electrode and the conductive electrode material, reducing the MO3 capacitance between the emitter and the base. - Together with the reduction in emitter capacitance, a bipolar transistor capable of high-speed operation can be formed on the same substrate as a MOS transistor.

In the manufacturing method of claim 2, since the mask body for emitter positioning is formed using the same electrode material as the gate electrode, the number of masks does not increase, and in particular, a frame-shaped mask whose side surfaces are covered with an insulating film is used. Since the emitter of the bipolar transistor and its contact hole are positioned using self-alignment lines, the emitter and contact hole can be formed within the minimum design rule.

In the device according to claim 3, the insulating film formed on the side surface of the gate electrode and the mask body serves as a sidewall necessary for the LDD structure, and the MOS transistor has an LDD structure, so that the bipolar transistor and the MOS transistor can be minimized. Therefore, the high-speed operation of the BiMOS semiconductor integrated circuit can be further improved.

In the manufacturing method according to claim 4, an MO having an LDD structure
Since we adopted an S transistor and formed the insulating film on the sidewalls of the gate electrode and mask body with the sidewalls required for the LDD structure, we
without increasing the number of mask steps in the S process.
Minimum emitter dimensions can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a manufacturing process diagram illustrating an example of the method for manufacturing a semiconductor integrated circuit device of the present invention, FIG. 2 is a conventional manufacturing process diagram, and FIG. 3 is a circuit diagram of a two-manpower AND gate employed in a BiCMO3 structure. Fig. 4 is a cut-off frequency and collector current characteristic diagram, Fig. 5 is a partially enlarged view of the emitter region, Fig. 6 is an explanatory diagram of the emitter contact, Fig. 7 is a manufacturing process diagram of another conventional example, and Fig. 8 The figure is a partially enlarged view of the emitter according to this embodiment.
The figure is an explanatory diagram of the emitter of this embodiment, FIG. 10 is an explanatory diagram of automatic positioning of this embodiment, FIG. 11 is an explanatory diagram of emitter dimensions of this embodiment, and FIG. 12 is an explanatory diagram of the emitter contact of this embodiment and its It is an explanatory view of positional shift. 1 is a substrate, 4 is an N region which becomes a collector region, 7 is an element formation region of a bipolar transistor, 8 is an element formation region of an NMOS transistor (a MOS transistor region of the same conductivity type), 9 is an element formation region of a PMOS transistor,
10 is a base region, 12 is an oxide film as an insulating film, 13
．． 14 is a Si3N4 film as a surface insulating film, 15.16
17 is a polysilicon gate electrode, 17 is a low concentration drain region, 18 is a Si3N film as a surface insulating film, 19 is a polysilicon electrode as an electrode material (mask body), and 20 is a tJ region which will be an emitter as a hollow region. , 21 is a side wall as a side insulating film, 24 is a source/drain formation region, 26 is an emitter region, 28.29 is a source/drain region, 41 is an emitter contact hole, and 48 is an emitter electrode.

Claims (4)

[Claims] (1) In a BiMOS structure in which a bipolar transistor and a MOS transistor are formed on the same substrate, the electrode material forming the gate electrode of the MOS transistor is placed on the base region of the bipolar transistor with an insulating film interposed therebetween, and the electrode material forms the gate electrode of the MOS transistor. When the material is viewed from above, it has a geometrically closed frame shape, and at least the hollow region of the frame-shaped electrode material fits within the base region, and the frame-shaped electrode material has a closed frame shape. The surface and side surfaces are covered with an insulating film, and an emitter region is provided in a hollow region surrounded by a frame-shaped electrode material covered with this insulating film, and an emitter region is opened in the hollow region of the electrode material using the electrode material as a mask. A semiconductor integrated circuit characterized in that an emitter electrode that is in contact with the emitter region through a contact hole formed in the contact hole is insulated from the electrode material by an insulating film that covers the surface and side surfaces of the electrode material. Device. (2) preparing a semiconductor substrate having at least a bipolar transistor region and a MOS transistor region of the same conductivity type as the bipolar transistor formed in this region; forming a collector region in the bipolar transistor region and a base region in the collector region; After forming an insulating film on the surface of the semiconductor substrate thus formed, a gate electrode is formed in the MOS transistor region, and at the same time, a closed frame is formed in the emitter formation region on the base region using the electrode material for forming the gate electrode. a shaped mask body, an insulating film is formed on the surface and side surfaces of the gate electrode and the mask body, and ions are applied to a hollow region surrounded by the frame-shaped mask body having at least the insulating film, using the mask body as a mask. At the same time, by selectively implanting ions into the regions where the source and drain of the MOS transistor are to be formed, the source and drain of the MOS transistor are formed.
1. A method of manufacturing a semiconductor integrated circuit device, comprising forming a drain region, and then using the mask body as a mask to form an emitter contact hole in a hollow region surrounded by the mask body. (3) The semiconductor integrated circuit according to claim 1, wherein the MOS transistor has an LDD structure, and the insulating film formed on the side surfaces of the gate electrode and the electrode material is a sidewall necessary for the LDD structure. Device. (4) The step of forming an insulating film on the surfaces and side surfaces of the gate electrode and the mask body includes the step of forming an insulating film on the surfaces of the gate electrode and the mask body, and the low concentration necessary for the LDD structure in the MOS transistor region. The process of forming the drain region and the LD on the side of the gate electrode and mask body.
3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, further comprising the step of forming sidewalls necessary for the D structure.