JPH0338042A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0338042A
JPH0338042A JP17321489A JP17321489A JPH0338042A JP H0338042 A JPH0338042 A JP H0338042A JP 17321489 A JP17321489 A JP 17321489A JP 17321489 A JP17321489 A JP 17321489A JP H0338042 A JPH0338042 A JP H0338042A
Authority
JP
Japan
Prior art keywords
metal film
film
substrate
via hole
deposited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17321489A
Other languages
Japanese (ja)
Inventor
Takenori Hario
針生 武徳
Masaaki Ichikawa
雅章 市川
Kiyoshi Watabe
渡部 潔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17321489A priority Critical patent/JPH0338042A/en
Publication of JPH0338042A publication Critical patent/JPH0338042A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain uniform step-coverage independent of the aspect ratio of a via hole by raising substrate temperature, applying a bias to a substrate, and using a first metal film whose surface energy is larger than that of a second metal film. CONSTITUTION:A first metal film 13 is stuck on an insulating film 12 in which a via hole is formed. The thickness of a first metal film 13 is thinned so as not to cause self-shadowing effect. Thereby the first metal film 13 can be almost uniformly stuck independently of the amount of surface energy of an insulating film 12 turning to a substratum. A second metal film 14 is sequential stuck. In this case, a substrate is heated and a bias is applied to the substrate. In addition, the first metal film 13 whose surface energy is larger than a second metal film 14 is used, thereby improving the wetability of the second metal film 14 on the first metal film 13. Hence the wiring metal layer 14 can be uniformly stuck independently of the aspect ratio of a via hole.

Description

【発明の詳細な説明】 〔概 要〕 配線金属膜の形成方法に関し、 アスペクト比のいかんにかかわらず均一にビアホー゛ル
を配線金属膜で埋め込む方法を提供することを目的とし
、 ビアホールを有する絶縁膜が形成された基板上にセルフ
シャドウィング効果の生じない程度の膜厚に第1の金属
膜をスパッタ蒸着し、続いて第1の金属膜より表面エネ
ルギーの小さな第2の金属膜をスパッタ蒸着する際該第
2の金属膜を構成する原子の該第1′の金属膜表面にお
ける表面拡散が促進される程度に基板温度を上昇させか
つ該ビアホール段差部に被着された該第2の金属膜がセ
ルフシャドウィング効果を生じない程度に基板パイ、ア
スを印加して該ビアホール内に配線金属膜を形成するよ
うに構成する。
[Detailed Description of the Invention] [Summary] The purpose of this invention is to provide a method for uniformly filling via holes with a wiring metal film, regardless of the aspect ratio, with respect to a method for forming a wiring metal film. A first metal film is sputter-deposited on the substrate on which the film is formed to a thickness that does not cause a self-shadowing effect, and then a second metal film having a surface energy smaller than that of the first metal film is sputter-deposited. In this case, the temperature of the substrate is raised to such an extent that surface diffusion of atoms constituting the second metal film on the surface of the first metal film is promoted, and the second metal deposited on the stepped portion of the via hole is heated. The wiring metal film is formed in the via hole by applying substrate pi and as to such an extent that the film does not cause a self-shadowing effect.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置の製造方法に係り、特に配線金属膜
の形成方法に関する。
The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a wiring metal film.

ICの信頼性向上のためには、大小さまざまなアスペク
ト比(ビアホールの深さと直径との比)を有するビアホ
ール全てに均一に配線金属膜を埋め込んで良好な段差被
覆性を得ることが要求される。
In order to improve the reliability of ICs, it is necessary to uniformly fill all via holes with various aspect ratios (the ratio between the depth and the diameter of the via hole) with a wiring metal film to obtain good step coverage. .

〔従来の技術〕[Conventional technology]

アスペクト比の異なるビアホールを有する絶縁膜上に通
常のスパッタ蒸着法を用いて配線金属膜を被着したとき
の断面図を第4図に示した。同図において31は基板、
32はビアホールを有する絶縁膜、33は配線金属膜例
えばAt膜である。被着されるAI膜33の膜厚が厚く
なるにつれて^l膜被着表面は同図中a、b、cで示す
ように変化する。即ち、被着初期においてAt膜33は
比較的均一にビアホール段差部に被着するものの、膜厚
が厚くなるにつれてビアホールの上面にひさし状となっ
て被着され、その後に飛来するAI原子がこのひさし状
A1膜に遮られてビアホール内壁に到達できなくなると
いうセルフシャドウィング効果が生じ、その結果、ビア
ホール段差部でAl膜33の膜厚は不均一となる。
FIG. 4 shows a cross-sectional view of a wiring metal film deposited on an insulating film having via holes with different aspect ratios using a conventional sputter deposition method. In the figure, 31 is a substrate;
32 is an insulating film having a via hole, and 33 is a wiring metal film such as an At film. As the thickness of the AI film 33 to be deposited increases, the surface to which the film is deposited changes as shown by a, b, and c in the figure. That is, at the initial stage of deposition, the At film 33 is relatively uniformly deposited on the step part of the via hole, but as the thickness of the At film 33 increases, it is deposited on the upper surface of the via hole in the shape of a canopy, and the AI atoms that fly in after that are deposited on the top surface of the via hole. A self-shadowing effect occurs in which the inner wall of the via hole cannot be reached because it is blocked by the eaves-like Al film, and as a result, the thickness of the Al film 33 becomes non-uniform at the step portion of the via hole.

そのため同図に示したようにアスペクト比の太きなビア
ホール内部にはボイド(空隙)が生じ、アスペクト比の
小さなビアホール段差部ではAt膜の断面形状が逆台形
状となる。このような現象はA1膜の断線あるいは抵抗
の増加等の弊害をもたらす原因となる。
Therefore, as shown in the figure, voids are generated inside the via hole with a large aspect ratio, and the cross-sectional shape of the At film becomes an inverted trapezoid in the stepped portion of the via hole with a small aspect ratio. Such a phenomenon causes problems such as disconnection of the A1 film or an increase in resistance.

上述のような問題を回避するために、基板加熱を行いか
つ基板にバイアス電圧を印加しつつスパッタ蒸着を行う
いわゆる高温高バイアススパッタ蒸着法が提案されてい
る。基板温度の上昇は、飛来したAI原子の基板表面に
おける表面拡散を促進し、At膜の基板に対するぬれ性
を向上させる作用をし、これによってAt膜の膜厚の均
一化が促進さ、れる。被着される金属膜の融点T、に対
し、基板温度T、。をT、 >T、、b >0.6 T
、となるように設定したときに蒸着原子の表面拡散が促
進されることが知られている。また、基板に対するバイ
アス電圧の印加によってビアホール段差部におけるひさ
し状のAt膜がスパッタエツチングされるため、前述し
たセルフシャドウィング効果は防止される。
In order to avoid the above-mentioned problems, a so-called high-temperature, high-bias sputter deposition method has been proposed in which sputter deposition is performed while heating the substrate and applying a bias voltage to the substrate. An increase in the substrate temperature promotes the surface diffusion of the incoming AI atoms on the substrate surface, which acts to improve the wettability of the At film to the substrate, thereby promoting uniformity of the thickness of the At film. The substrate temperature T, with respect to the melting point T, of the metal film to be deposited. T, >T,, b >0.6 T
It is known that the surface diffusion of deposited atoms is promoted when the temperature is set so that , . Further, since the eaves-shaped At film at the step portion of the via hole is sputter-etched by applying a bias voltage to the substrate, the above-mentioned self-shadowing effect is prevented.

第5図は上述の高温高バイアススパッタ蒸着法を用いて
被着されたAt膜の断面図を示したものであり、第4図
と同一のものには同一番号を付した。
FIG. 5 shows a cross-sectional view of an At film deposited using the above-described high-temperature, high-bias sputter deposition method, and the same parts as in FIG. 4 are given the same numbers.

同図から明らかなように、ビアホール段差部でのAt膜
のひさし形状が緩和されボイドの発生あるいは逆台形状
が見られなくなる。
As is clear from the figure, the shape of the eaves of the At film at the step portion of the via hole is relaxed, and no voids or inverted trapezoidal shapes are observed.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところが上述の方法を用いた場合にも第5図に見られる
ように、ビアホールの内壁に被着されたAt膜の膜厚は
それ以外の部分に被着されたAt膜に比べて薄く、その
結果、アスペクト比の大きなビアホールはAIIQで埋
め込まれるものの、アスペクト比の小さなビアホールの
段差部では同図中Jで示した部分の膜厚が薄くなること
を本発明者等は実験的に確認した。即ち、基板バイアス
印加によってセルフシャドウィング効果の生しることを
防ぐことはできるものの、ビアホール内壁とそれ以外の
部分におけるAt膜の膜厚差を解消するためには基板加
熱だけでは充分でないことが明らかになった。
However, even when the above method is used, as shown in Figure 5, the thickness of the At film deposited on the inner wall of the via hole is thinner than that of the At film deposited on other parts. As a result, the present inventors experimentally confirmed that although via holes with a large aspect ratio are filled with AIIQ, the film thickness at the step portion of the via hole with a small aspect ratio, indicated by J in the figure, becomes thinner. In other words, although it is possible to prevent the self-shadowing effect from occurring by applying a substrate bias, heating the substrate alone is not sufficient to eliminate the difference in the thickness of the At film between the inner wall of the via hole and other parts. It was revealed.

そこで本発明はビアホールのアスペクト比のいかんにか
かわらず均一な段差被覆性を得ることを目的とする。
Therefore, an object of the present invention is to obtain uniform step coverage regardless of the aspect ratio of the via hole.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題の解決は、ビアホールを有する絶縁膜が形成さ
れた基板上にセルフシャドウィング効果の生じない程度
の膜厚に第1の金属膜をスパッタ蒸着し、続いて第1の
金属膜より表面エネルギーの小さな第2の金属膜をスパ
ッタ蒸着する際該第2の金属膜を構成する原子の該第1
の金属膜表面における表面拡散が促進される程度に基板
温度を上昇させかつ該ビアホール段差部に被着された該
第2の金属膜がセルフシャドウィング効果を生じない程
度に基板バイアスを印加して該ビアホール内に配線金属
膜を形成することを特徴とする半導体装置の製造方法に
よって達成される。
To solve the above problem, a first metal film is sputter-deposited on a substrate on which an insulating film having via holes is formed to a thickness that does not cause self-shadowing, and then a surface energy When sputter-depositing a second metal film with a small
raising the substrate temperature to an extent that surface diffusion on the surface of the metal film is promoted, and applying a substrate bias to an extent that the second metal film deposited on the step portion of the via hole does not cause a self-shadowing effect; This is achieved by a method for manufacturing a semiconductor device characterized by forming a wiring metal film within the via hole.

〔作 用〕[For production]

一般に基板に被着された物質の膜厚均一性は該基板に対
する該物質のぬれ性に影響され、これは両者の表面エネ
ルギーの相対的な大小関係によって決まることが知られ
ている。第1図には同一基板に表面エネルギーの異なる
物質が部分的に被着したときの断面形状を模式的に示し
たものである。
It is generally known that the uniformity of the film thickness of a substance deposited on a substrate is affected by the wettability of the substance to the substrate, and that this is determined by the relative size relationship of the surface energies of the two. FIG. 1 schematically shows a cross-sectional shape when substances having different surface energies are partially deposited on the same substrate.

同図において第1の物質2の表面エネルギーは基板lの
それより大きく第2の物質3の表面エネルギーは基板1
のそれより小さい場合を示している。
In the figure, the surface energy of the first substance 2 is larger than that of the substrate l, and the surface energy of the second substance 3 is greater than that of the substrate l.
It shows the case where it is smaller than that of .

同図に見られるように、被着された物質の表面エネルギ
ーが基板のそれより小さい場合にはこの物質の膜厚はよ
り均一となる。表面エネルギーは表1にその一例を掲げ
たように物質固有の値を有している。
As can be seen in the figure, if the surface energy of the deposited material is lower than that of the substrate, the thickness of the deposited material will be more uniform. Surface energy has a value specific to each substance, as shown in Table 1.

表1 本発明は以上の現象を利用したものであり、まず、ビア
ホールの形成された絶縁股上に第1の金属膜を被着させ
る。第1の金属膜の膜厚をセルフシャドウィング効果が
生じない程度に薄くすることによってこの第1の金属膜
は下地となる絶縁膜の表面エネルギーの大小とは無関係
にほぼ均一に被着させることができる。vtいて第2の
金属膜を被着するが、この際、基板加熱及び基板バイア
ス印加のみではセルフシャドウィング効果は抑制される
もののビアホール内壁におけるAI膜の膜厚が薄くなり
、その結果、ビアホール段差部での膜厚均一性に問題が
生しることは従来方法に関連して述べたところである。
Table 1 The present invention utilizes the above phenomenon, and first, a first metal film is deposited on the insulation crotch in which the via hole is formed. By reducing the thickness of the first metal film to such an extent that no self-shadowing effect occurs, the first metal film can be deposited almost uniformly regardless of the surface energy of the underlying insulating film. I can do it. A second metal film is deposited by applying vt, but at this time, although the self-shadowing effect is suppressed only by heating the substrate and applying a substrate bias, the thickness of the AI film on the inner wall of the via hole becomes thinner, and as a result, the height difference in the via hole As mentioned above in connection with the conventional method, there is a problem with the uniformity of the film thickness in some areas.

そこで本発明では、上記基板加熱及び基板バイアス印加
に加えて第1の金属膜として第2の金属膜より表面エネ
ルギーの大きなものを用いる。これにより第1の金属膜
上における第2の金属膜のぬれ性を向上させてビアホー
ル内壁とそれ以外の部分に被着した第2の金属膜の膜厚
差を解消させるものである。
Therefore, in the present invention, in addition to the above-described heating of the substrate and application of a substrate bias, a film having a surface energy larger than that of the second metal film is used as the first metal film. This improves the wettability of the second metal film on the first metal film and eliminates the difference in thickness between the inner wall of the via hole and the second metal film deposited on the other parts.

以上のように本発明では第2の金属膜の均一性を向上さ
せるために、基板温度を上昇させかつ基板バイアスを印
加するとともに第2の金属膜より表面エネルギーの大き
な第1の金属膜を用いることによってビアホールの内壁
面のAI膜が薄くなることを防ぐものであり、これによ
ってビアホールの段差部における膜厚の不均一性を改み
することができる。
As described above, in the present invention, in order to improve the uniformity of the second metal film, the substrate temperature is increased, a substrate bias is applied, and the first metal film having a higher surface energy than the second metal film is used. This prevents the AI film on the inner wall surface of the via hole from becoming thinner, thereby making it possible to correct the non-uniformity of the film thickness at the stepped portion of the via hole.

〔実施例〕〔Example〕

第2図は本発明の詳細な説明するための断面図である。 FIG. 2 is a sectional view for explaining the present invention in detail.

同図(a)に示すように、基板11上にCVD法により
形成した膜厚1#mの酸化膜12に直径1μm及び3μ
麿のビアホールを形成する。次にこれを第3図に示した
スパッタ蒸着装置にセットする。
As shown in Figure (a), an oxide film 12 with a thickness of 1 #m formed on a substrate 11 by the CVD method has a diameter of 1 μm and a diameter of 3 μm.
Forms Maro's beer hall. Next, this is set in the sputter deposition apparatus shown in FIG.

第3図において、21は基板、22はヒーター、23は
基板支持台、24はターゲット、25はターゲット支持
台、26はガス導入口、27はガス排気口、28は高周
波電源、29は直流電源である。ガス導入口26よりA
rガスを30 SCCM流し、装置内圧力を0.03T
orrとし、直流電源29より直流電力15KWをTi
からなるターゲット24に供給して基板21上にTi膜
のスパッタ蒸着を行う、この段階における基板加熱及び
基板バイアス印加は、本実施例では行わなかったが、実
施しても後の結果に相違は生じない。以上のようにして
第2図(b)に示すように、膜厚0.1pm+のTi膜
13を被着させる。本発明者等の実験によれば、Ti膜
厚0.2−以下ではセルフシャドウィング効果は生ぜず
、従ってTi膜厚はビアホール内壁にほぼ均一に被着さ
れる。ついでヒーター22により基板温度を400 ’
Cに設定するとともに周波数13.56Mllzの高周
波電源28を用いて基板電圧500vを印加し、^lか
らなるターゲット24を用いてAI膜を1μm被着させ
ると、第2図(C)に示すように、小さなビアホールは
埋め込まれ大きなビアホールの段差部での膜厚は均一と
なる。
In FIG. 3, 21 is a substrate, 22 is a heater, 23 is a substrate support stand, 24 is a target, 25 is a target support stand, 26 is a gas inlet, 27 is a gas exhaust port, 28 is a high frequency power supply, and 29 is a DC power supply. It is. A from gas inlet port 26
Flow r gas at 30 SCCM and set the pressure inside the device to 0.03T.
orr, and apply 15KW of DC power from the DC power supply 29 to Ti
The substrate heating and substrate bias application at this stage, which sputter-deposit a Ti film on the substrate 21 by supplying it to the target 24 consisting of Does not occur. As described above, as shown in FIG. 2(b), a Ti film 13 having a thickness of 0.1 pm+ is deposited. According to experiments conducted by the present inventors, the self-shadowing effect does not occur when the Ti film thickness is 0.2 mm or less, and therefore the Ti film thickness is almost uniformly deposited on the inner wall of the via hole. Then, the substrate temperature was increased to 400' using the heater 22.
C and applying a substrate voltage of 500 V using the high frequency power source 28 with a frequency of 13.56 Mllz, and depositing an AI film of 1 μm using the target 24 made of ^l, as shown in FIG. 2 (C). In this case, the small via hole is filled in, and the film thickness at the step of the large via hole becomes uniform.

なお、上記実施例において、第1の金属膜としてW、 
TiW 、TiN等を、第2の金属膜として各棟のA1
合金膜を用いることができる。
Note that in the above embodiments, W, W,
TiW, TiN, etc. are used as the second metal film on A1 of each building.
An alloy film can be used.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明によれば、ビアホールのアスペクト
比にかかわらず均一に配線金属膜を被着させることがで
きるためICの信頼性の向上に有益である。
As described above, according to the present invention, a wiring metal film can be uniformly deposited regardless of the aspect ratio of a via hole, which is useful for improving the reliability of an IC.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理説明図、 第2図は本発明の実施例を示す断面図、第3図は本発明
の実施に用いるスパッタ蒸着装置の断面図、 第4図、第5図は従来例の問題点を示す断面図、である
。 図において、 1111.21.31は基板、 2は第1の物質、 3は第2の物質、 12は酸化膜、 13はTi膜、 14.33はAIB!A。 22はヒーター 23は基板支持台、 24はターゲット、 25はターゲット支持台、 26はガス導入口、 27はガス排気口、 28は高周波電源、 29は直流電源、 32は絶縁膜、 不発日月の、ffi理説B月図 第 一3?−eTA /) ’l ’f”−・ブ71i’a
$v#、g3暑 丁Fes、Ei4f!+:At+6x、・ぐ・ンタE、
、41!第 第 配 イ足釆ダ11の間弗k、Σ示ず前面ロ ガ 5 囮
Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a cross-sectional view showing an embodiment of the present invention, Fig. 3 is a cross-sectional view of a sputter deposition apparatus used for carrying out the present invention, Figs. FIG. 3 is a cross-sectional view showing problems in the conventional example. In the figure, 1111.21.31 is the substrate, 2 is the first material, 3 is the second material, 12 is the oxide film, 13 is the Ti film, 14.33 is AIB! A. 22 is a heater 23 is a substrate support base, 24 is a target, 25 is a target support base, 26 is a gas inlet, 27 is a gas exhaust port, 28 is a high frequency power supply, 29 is a DC power supply, 32 is an insulating film, , ffi theory B moon map 13? -eTA/) 'l 'f'-・bu71i'a
$v#, g3 Hotting Fes, Ei4f! +: At+6x,・gu・ntaE,
, 41! 5th decoy

Claims (1)

【特許請求の範囲】[Claims] ビアホールを有する絶縁膜が形成された基板上にセルフ
シャドウイング効果の生じない程度の膜厚に第1の金属
膜をスパッタ蒸着し、続いて第1の金属膜より表面エネ
ルギーの小さな第2の金属膜をスパッタ蒸着する際該第
2の金属膜を構成する原子の該第1の金属膜表面におけ
る表面拡散が促進される程度に基板温度を上昇させかつ
該ビアホール段差部に被着された該第2の金属膜がセル
フシャドウイング効果を生じない程度に基板バイアスを
印加して該ビアホール内に配線金属膜を形成することを
特徴とする半導体装置の製造方法。
A first metal film is sputter-deposited on a substrate on which an insulating film having via holes is formed to a thickness that does not cause a self-shadowing effect, and then a second metal film having a surface energy smaller than that of the first metal film is deposited. When the film is sputter-deposited, the substrate temperature is raised to such an extent that surface diffusion of atoms constituting the second metal film on the surface of the first metal film is promoted, and the second metal film deposited on the stepped portion of the via hole is 2. A method of manufacturing a semiconductor device, characterized in that a wiring metal film is formed in the via hole by applying a substrate bias to such an extent that the metal film does not cause a self-shadowing effect.
JP17321489A 1989-07-05 1989-07-05 Manufacture of semiconductor device Pending JPH0338042A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17321489A JPH0338042A (en) 1989-07-05 1989-07-05 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17321489A JPH0338042A (en) 1989-07-05 1989-07-05 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0338042A true JPH0338042A (en) 1991-02-19

Family

ID=15956243

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17321489A Pending JPH0338042A (en) 1989-07-05 1989-07-05 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0338042A (en)

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