JPH0337949A - Ion implantation device and manufacture of semiconductor integrated circuit device using same - Google Patents

Abstract

PURPOSE:To effectively prevent contamination of a substrate caused by sputtering of an ion implantation device by constituting at least the surfaces of members provided on a course of an ion beam of high purity silicon. CONSTITUTION:Of the members constituting an ion implantation device 1, respective surfaces and members of the members provided on the cource of an ion beam IB, that is, a leader slit 4, leader electrodes 3, an analysis slit 7, liners 8, acceleration electrodes 10, focusing lenses 11, a slit 18, a substrate holder 15 and a beam stopper 14 are constituted of high-purity silicon. Thereby, a substance produced when the surfaces of the members provided on the ion beam cource are sputtered is a substance (silicon) of the same composition with a substrate thus becoming no contamination source of the substrate.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to ion implantation technology used in the manufacturing process of semiconductor integrated circuit devices, and in particular to technology that is effective when applied to cleaning ion implantation equipment. It is.

[Conventional technology]

In the manufacturing process of semiconductor integrated circuit devices, impurities are introduced into the semiconductor substrate (wafer) using ion implantation technology to form semiconductor regions (pn junctions) such as well regions, channel stopper regions, source and drain regions. The ion implantation method has the advantage that the impurity concentration of the substrate can be controlled more precisely than the thermal diffusion method because the dose of impurity ions can be measured. This ion implantation technique has the advantage that the impurity profile of the substrate can be controlled more precisely than the thermal diffusion method.This ion implantation technique is described, for example, in Japanese Patent Application No. 63-280779.

[Problem to be solved by the invention]

However, since the ion implantation method introduces high-energy impurities into the substrate, there is a problem in that defects are easily induced in the substrate, and the electrical characteristics of the device deteriorate due to these defects. Therefore, after ion implantation, annealing treatment is essential to recover defects induced in the substrate and to electrically activate the implanted impurity ions.

However, in recent years megabit (Mbit) class memory LS
In VLSIs manufactured using submicron design rules such as I, the active region of the substrate has a thickness of 0.1 to 0.2μ.
Since it is necessary to reduce the temperature of the process in order to reduce the extremely shallow pn junction of about 100 m, the annealing process after ion implantation must also be performed at a low temperature. Therefore, in the VLSI manufacturing process, it is necessary to reduce as much as possible the contamination of the substrate during ion implantation, which hinders defect recovery, and to efficiently recover defects.

One of the causes of substrate contamination during ion implantation is sputtering from an ion implanter using an ion beam. this is,
When the ion beam generated from the ion source of the ion implantation device passes through the extraction electrode, analyzer, analysis slit, etc. inside the device, a portion of the ion beam collides with these and sputters the surface, and the generated substances are This is a phenomenon in which ions are attached to the surface of a substrate or are driven into the substrate by ions. Members such as extraction electrodes, analyzer inner walls, and analysis slits of the ion implantation device are made of graphite or aluminum, so if their surfaces are sputtered, the substrate will be contaminated with carbon or aluminum. Further, for example, graphite has a low purity of about 99.99 to 99.999%, so contamination by heavy metals such as Fe and Cu contained as impurities in graphite cannot be avoided. Especially MOS-F
10” (ato
ms/ci), a high current type ion implanter with a large beam current is used, which generates a large amount of contaminants due to sputtering and contamination of the substrate becomes a serious problem. becomes.

An object of the present invention is to provide a technique that can effectively prevent contamination of a substrate caused by sputtering of an ion implanter.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

One invention of the present application is an ion implantation device in which at least the surface of a member provided on the path of an ion beam is made of high-purity silicon.

[Effect]

According to the above means, the substance generated when the surface of the member provided on the path of the ion beam is sputtered is
Because it is a substance (silicon) that has the same composition as the substrate, it does not become a source of contamination for the substrate.In addition, silicon has a purity of 9.
Since the purity can be increased to 9.99999999% or more, contamination of the substrate by impurities such as heavy metals contained in the above substances can be avoided.

〔Example〕

FIG. 4 shows the main parts of an ion implantation apparatus which is an embodiment of the present invention.

This ion implanter l is a large current type ion implanter that generates a beam current of 1 (mA) or more at maximum, and an ion source 2 installed at one end of the ion implanter generates thermoelectrons emitted from a filament in a magnetic field. It has a mechanism to generate ions from gaseous elements using This ion source 2
The generated ions are extracted from the extraction slit 4 by a voltage applied between the ion source 2 and the extraction electrode 3, and then a pair of electrodes (acceleration electrode, deceleration electrode) 3a, 3b forming the extraction electrode 3. The beam is focused into an ion beam In.

A mass spectrometry system 5 provided adjacent to the extraction electrode 3 selects ion species necessary for implantation from among the various ions generated by the ion source 2. This mass spectrometry system 5 is composed of a fan-shaped mass spectrometry electromagnet (analyzer) 6 and an analysis slit 7 placed at its focal point. A liner 8 is attached to the side wall of the path through which the ion beam L 2 passes, to prevent melting of the side wall and incorporation of impurities due to irradiation with the ion beam In 2 .

The acceleration tube 9 provided adjacent to the mass spectrometry system 5 applies a predetermined energy to the ion species selected by the mass spectrometry system 5. This accelerating tube 9 has a multi-throw structure consisting of a plurality of accelerating electrodes 10, and has a structure in which ions are accelerated by an electric field created between each accelerating electrode 10.

The ion beam (2), which has been given energy by the accelerating tube 9, is focused by a converging lens 11 and introduced into the implantation chamber 12 through the pickpocket 1) 18.

A rotating disk 13 is provided at the center of the injection chamber 12, and a beam stopper 14 for absorbing the ion beam (2) is provided behind it. Substrate holders 15 for fixing substrates (wafers) 20 are provided on the peripheral edge of the rotating disk 13 at predetermined intervals of l'1Jll. In other words, this ion implantation device 1 is
A batch method is adopted in which ions are implanted into a plurality of substrates 20 at once. During ion implantation, the rotating disk 1
The substrate 20 is fixed to the substrate holder 15 by moving vertically or horizontally while rotating at high speed.
The entire surface of the substrate is uniformly irradiated with the ion beam In.

In this embodiment, among the members constituting the ion implantation apparatus 1, those provided on the path (beam line) of the ion beam (3), namely, the extraction slit 4, the extraction electrode 3, the analysis slit 7, the liner 8, Each surface or member of the accelerating electrode 10, converging lens 11, slit 18, substrate holder 15, and beam stopper 14 is made of high-purity silicon.

For example, the analysis slit 7 shown in FIGS. 1 and 2 has a structure in which a thin film 17 of high-purity silicon is adhered to the surface of a graphite core material 16 processed into a disk shape.

Although not shown, the extraction slit 4 and the extraction electrode 3
, the liner 8, the accelerating electrode 10, the converging lens 11, the slit 18, the substrate holder 15, and the beam stopper 14 each have a core material 1 made of graphite or aluminum.
It has a structure in which a thin film 17 of high purity silicon is deposited on the surface of 6.

The thin film 17 is made of amorphous silicon deposited on the surface of the core material 16 by, for example, the CVD method,
It has a film thickness of about 100 μm. This amorphous silicon has a purity of 99.99999999% (so-called ten nines) or more. thin film 1
Amorphous silicon 7a can also be deposited by sputtering. In this case, sputtering is performed using a target of single crystal silicon or polycrystalline silicon having a purity of ten nines or higher.

Each of the members provided on the path of the ion beam 3 has its core material 16 made of low resistance silicon (doped silicon) into which impurities have been introduced, for example, having a resistance value of about 10 to several hundreds of ΩCl11. The thin film 17 may be made of not only the amorphous silicon described above but also
Silicon having a purity of ten nines or higher grown on the surface of the core material 16 by an epitaxial method.
It may be.

A part of the member provided on the path of the ion beam (3) may be made of silicon having a purity of ten nines or higher. In this case, since the member is insulating, at least its surface is made to have a low resistance by irradiation with a neutron beam or doping with impurities in order to prevent the adverse effects of charge-up.

Each of the members placed on the path of the ion beam (1) may be made of high-purity silicon only at the portions that are irradiated with the ion beam (I++).

That is, the analysis slit 7 shown in FIGS. 1 and 2 is
A thin film 17 of high-purity silicon was deposited on the entire surface of the graphite core material 16, for example, as in the analysis slit 7 shown in FIG.
A thin film 17 of high-purity silicon is applied only to the areas that are irradiated.
may be coated with

As described above, the ion implantation apparatus 1 of this embodiment includes the extraction slit 4, the extraction electrode 3, the analysis slit 7, the liner 8, the accelerating electrode 10, and the extraction electrode 3 provided on the path of the ion beam.
Since each surface of the converging lens 11, slit 18, substrate holder 15 and beam stopper 14 is made of silicon having a purity of ten nines or higher,
The substances generated when the surfaces of these members are sputtered with the ion beam I have the same composition as the substrate 20, so that contamination of the substrate 20 is avoided.

Further, since the content of elements other than silicon contained in this substance is extremely small, contamination of the substrate 20 by impurities such as heavy metals is also avoided.

Next, an example of a method for manufacturing a semiconductor integrated circuit device using the ion implantation apparatus 1 will be described. This manufacturing method is D
RAM (Dynamic Random Accesses)
MO3-FETQs for memory cell selection which constitutes the memory cell of s Memory), n-channel MO3-FETQn, p-channel MO3-FETQ which constitutes the peripheral circuit.
This method was applied to the manufacturing method of p. Hereinafter, the specific manufacturing method will be explained using FIGS. 5 to 18 (cross-sectional views of main parts shown for each manufacturing process). Furthermore, this D
The RAM has a capacity of, for example, 16 megabits (Mbit), and is manufactured according to the so-called 0.5 [μm] design rule, in which the minimum processing size is 0°5 [μm].

FIG. 5 is a sectional view of a main part of a semiconductor substrate (wafer) 20 in the middle of the manufacturing process of this DRAM.
The memory cell formation region (left side of the figure) of the substrate 20 made of silicon single crystal and the n-channel MOS of the peripheral circuit.
A p-type well region 22 is provided on each main surface of the FETQ (the center of the n-type predetermined region). This p-type well region 22 is, for example, 10'2 to 10'' (at
B (or BF2) with an impurity concentration of about oms/cm
is introduced by ion implantation with an energy of about 20 to 30 (K e V), and then the substrate 20 is heated at 1100 to 130 fM.
It is formed by heat treatment in an atmosphere at a high temperature of about t). Peripheral circuit p-channel MOS-F ETQ
There is an n-type well region 2 on the main surface of the p-formation region (on the right side of the figure).
1 is provided. This n-type well region 21 is formed by introducing B (or BF2) with an impurity concentration of, for example, about 10'3 (atoms/cIll) by ion implantation with an energy of about 20 to 30 [KaV], and then inserting the substrate 20 into the substrate 20. 1
It is formed by heat treatment in an atmosphere at a high temperature of about 100 to 1300 (t).

The main surface of each of the well regions 21 and 22 has a 400
A field insulating film 23 for element isolation having a film thickness of about 600 (nm) is provided. This field insulating film 23 is formed by a selective oxidation method (LOCO5 method).

In the peripheral circuit formation region, the p″ type Towel region 22
A p-type channel stopper region 24 is provided below the field insulating film 23. The p-type channel stopper region 24 is, for example, 10'' on the main surface of the p-type well region 22.
After introducing BF2 with an impurity concentration of about [atoms/cIII] by ion implantation with an energy of about 50 to 70 (KeV:), the substrate 20 is placed in a nitrogen gas atmosphere containing a trace amount of oxygen (approximately 1% or less). 1050-1150
It is formed by heat treatment at a high temperature of about Ct) for about 30 to 40 [minutes], and then oxidation by a steam oxidation method for about 30 to 50 [minutes]. This heat treatment results in p-
The impurity introduced into the main surface of the type well region 22 is stretched and diffused, and the p-type channel stopper region 24 is formed by substantially the same manufacturing process as the formation of the field insulating film 23.

A p-type channel stopper region 25A and a p-type semiconductor region 25B are provided on the main surface of the memory cell formation region.

The p-type channel stopper region 25A is provided under the field insulating film 23, and the p-type semiconductor region 25B is provided in the active region.

p-type channel stopper region 25ASp-type semiconductor region 25
Each of B is, for example, 10'2 to 10'' (atoms
B with an impurity concentration of about /ca[] is 200~30Q (
It is formed by introducing high energy ion implantation of about KeV:1. p-type channel stopper region 25
A is formed by introducing the above-mentioned impurity through the field insulating film 23, and the p-type semiconductor region 25B is located deep in the main surface of the p-type well region 22 by an amount corresponding to the thickness of the field insulating film 23. is formed.

The active area of each well region 22.21 includes 12
Gate insulating film 26 having a film thickness of about 18 (Tlm)
is provided. This gate insulating film 26 is, for example, 8
It is formed by steam oxidizing the substrate 20 at a high temperature of about 0.00 to 1000 (t).

On each of the field insulating film 23 and gate insulating film 26 in the memory cell formation region, MO3 for memory cell selection is provided.
- A gate electrode 27 of FETQs is provided. The gate electrode 27 of MO3-FETQs for memory cell selection is
Also serves as a word line (WL). In the peripheral circuit formation region, on the gate insulating film 26 of the p-type well region 22, there is a gate electrode 27 of the n-channel MO3-FETQn.
is provided, and the gate insulating film 26 of the n-type well region 21 is
A gate electrode 27 of the p-channel MO3-FETQp is provided above. These gate insulating films 27 are
For example, a polysilicon film having a film thickness of about 200 to 300 nm is used. An n-type impurity (P or As) is introduced into this polysilicon film to reduce the resistance value of the gate. To form the electrode 27, for example, a polysilicon film is deposited on the entire surface of the standing substrate 20 by the CVD method, an n-type impurity is introduced into this polysilicon film by a thermal diffusion method, and then 5iO2 (not shown) is deposited on the surface of the polysilicon film. - A film is formed by a thermal oxidation method, and then in S10, on the entire surface of the film,
For example, an interlayer insulating film 28 having a film thickness of about 250 to 350 (nm) is deposited. This interlayer insulating film 28 is formed by, for example, a CVD method using inorganic silane gas and nitrogen oxide gas as source gases.Next, The gate electrode 27 is etched by anisotropically etching the interlayer insulating film 28 and the polysilicon film using a photoresist mask (not shown).
is formed. Note that the gate electrode 27 is made of a high melting point metal (
Mo, Ti, Ta, W) films and high melting point metal silicide (M
oSi,, Ti5izTaSL, WSiz)
It may be composed of a single layer of membrane. Further, the gate electrode 27 is
It may be constructed of a composite film in which the above-mentioned high melting point metal film or high melting point metal silicide film is laminated on a polysilicon film.

Next, as shown in FIG. 6, an n-type impurity 29n is introduced into the main surface of the p-type well region 22 using the field insulating film 23 and the interlayer insulating film 28 (gate electrode 27) as an impurity introduction mask. This n-type impurity 29n is introduced into the gate electrode 27 in a self-aligned manner. The n-type impurity 29n is, for example, 10'' (atoms/cuf:
Using P (or As) with an impurity concentration of about 30~
It is introduced by ion implantation with an energy of about 50 [Key]. Although not shown, when introducing the n-type impurity 29n, the main surface of the n-type well region 21 is covered with an impurity introduction mask (for example, a photoresist film).

Next, a p-type impurity 30n is introduced into the main surface of the n-type well region 21 using the field insulating film 23 and the interlayer insulating film 28 (gate electrode 27) as an impurity introduction mask.

This p-type impurity 30n is introduced into the gate electrode 27 in a self-aligned manner.

The p-type impurity 30n is, for example, l Q” (atoms/
Using B (or BFa) with an impurity concentration of about c++, it is introduced by ion implantation with an energy of about 20 to 30 (KeV). Although not shown, when introducing the p-type impurity 30, the main surface of the p-type well region 22 is covered with an impurity introduction mask (photoresist film).

Next, as shown in FIG. 7, sidewall spacers 31 are formed on each sidewall of the gate electrode 27 and the interlayer insulating film 28 thereon. The side wall spacer 31 is
For example, after depositing a 5iOa film using inorganic silane gas and nitrogen oxide gas as source gases by the CVD method,
It is formed by performing anisotropic etching such as RIE to a thickness corresponding to the thickness of the 102 film (for example, about 130 to 180 (nm)). The length of the sidewall spacer 31 in the gate length direction (channel length direction) is approximately 150C.
nm).

Next, in this embodiment, the large current type ion implantation device 1 is used to introduce the n-channel MOS-FET Qn type short-region type impurity 32n of the peripheral circuit.

When introducing this n-type impurity 32n, the sidewall spacer 31 is mainly used as an impurity introduction mask.

In addition, the region where the n-channel MOS-FET Qn-type predetermined region is formed is covered with an impurity introduction mask (photoresist film, not shown).
covered with. The n-type impurity 32n is, for example, lQ'S
As (or P) with an impurity concentration of about (atoms/cat) is introduced by ion implantation with an energy of about 70 to 90 (KeV). At that time, the rotating disk I3 of the ion implanter 1 is rotated at a speed of 1250 rpm. Ion implantation is carried out for about 10 minutes while rotating.

Next, as shown in FIG. 8, by heat-treating the substrate 1, the above-mentioned n-type impurities 29n, n-type impurities 32n,
Each p-type impurity 30p is stretched and diffused to form an n-type semiconductor region 2 of MO3-FETQs for memory cell selection.
9. n of peripheral circuit n-channel MOS l FETQn
n-type semiconductor region 29, n-type semiconductor region 32, n-type semiconductor region 30 of n-channel MOS-FETQp in the peripheral circuit
form each of them. For example, the heat treatment described above is performed at 90%
It is carried out at a high temperature of about 0 to 1000 C'e:I for about 20 to 40 [minutes]. By forming the n-type semiconductor region 29, the memory cell selection MOS/FETQs of the memory cell is completed. Further, by forming the n-type semiconductor region 29 and the n-type semiconductor region 32, the n-channel MOS-FETQn of the peripheral circuit having the LDD structure is completed. Note that the n-channel MOS-FETQp of the peripheral circuit is
Only the n-type semiconductor region 30 forming part of the LDD structure is completed.

Next, an interlayer insulating film 33 is deposited over the entire surface of the substrate 20. This interlayer insulating film 33 is used as an etching stopper layer when processing an electrode layer of an information storage capacitive element C of a memory cell, which will be described later. The interlayer insulating film 33 also serves as the lower electrode layer of the information storage capacitive element C and the memory cell selection MOS.
- It is formed to electrically isolate the gate electrode 27 (word line WL) of FETQs. Interlayer insulating film 33 is formed to increase the thickness of sidewall spacer 31 of n-channel MOS-FETQp.

The interlayer insulating film 33 is made of S10.
The gutter bottom is covered with a film and has a film thickness of about 130 to 180 [nm].

Next, as shown in FIG. 9, the memory cell selection MOS-
The interlayer insulating film 33 on one n-type semiconductor region (the side to which the lower electrode layer of the information storage capacitive element C is connected) 29 of the FETQs is removed to form connection holes 33A and 34, respectively. This connection hole 34 is connected to the side wall spacer 3
1. It is formed in a region defined by each sidewall spacer 33B deposited on the sidewall of the sidewall spacer 31 when the interlayer insulating film 33 is etched.

Next, as shown in FIG. 10, a polysilicon film 35A is deposited on the entire surface of the substrate 20, which will become the lower electrode layer of the information M product capacitor C of the memory cell. This polysilicon film 35A
A portion thereof is connected to the n-type semiconductor region 29 through each of the connection holes 33A and 34. This polysilicon film 35A is deposited by the CVD method and has a thickness of 150 to 250 [
It has a film thickness of about 100 nm. This polysilicon film 3
5A, an n-type impurity, such as P, which reduces the resistance value after deposition, is introduced by thermal diffusion. A large amount of this n-type impurity is diffused into the n-type semiconductor region 29 through the connection hole 34, and is introduced at a low impurity concentration so as not to diffuse into the channel forming region side of the memory cell selection MOS/FETQs.

Next, as shown in FIG.
A polysilicon film 35B is further deposited on top of A. This upper layer polysilicon film 35B is deposited by CVD method,
It has a film thickness of about 250 to 350 [nm]. After deposition, an n-type impurity such as P, which reduces the resistance value, is introduced into the upper polysilicon film 35B by thermal diffusion. This n-type impurity is introduced at a high impurity concentration in order to improve the amount of charge storage in the information storage capacitive element C.

Next, as shown in FIG. 12, the two-layer structure polysilicon films 35A and 35B are processed into a predetermined shape using photolithography technology and anisotropic etching technology, and the information storage capacitive element C is formed. A lower electrode layer 35 is formed.

Next, as shown in FIG. 13, a dielectric film 36 is deposited on the entire surface of the substrate 20. The dielectric film 36 is made of, for example, 5IsNa.
Film 36 A s SiO2 film 36B sequentially laminated 2
Formed in a layered structure. 513N4 film 36A is, for example, CV
It is deposited by method D and has an Ml of about 5 to 7 (T1m).When the 313N4 film 36A is deposited on the lower electrode layer 35 (polysilicon film) at a normal production level,
Since a very small amount of oxygen is involved, the 513N4 film 3
6 and the lower electrode layer 35 is a natural oxide film (not shown).
SiO2 film) is formed.

The upper layer of the dielectric film 36, the Sin film 36B, is shaped by applying a high pressure oxidation method to the lower layer 5isN< film 36A.
It has a film thickness of about 3.3 nm (nm).

Next, a polysilicon film (not shown) is deposited over the entire surface of the substrate 20. The polysilicon film was deposited by CVD method and
It has a film thickness of about 120 (nm). This polysilicon film contains n-type impurities that reduce the resistance value after deposition.
For example, P is introduced by a thermal diffusion method. Next, one n-type semiconductor region 2 of the memory cell selection layer MO3-FETQs
An etching mask (photoresist film) (not shown) is formed on the polysilicon film over the entire memory cell formation region except for the connection region between 9 and complementary data lines to be described later.

Thereafter, as shown in FIG. 14, the polysilicon film and dielectric film 36 are sequentially anisotropically etched using the etching mask to form the information storage capacitive element C.
An upper electrode layer 37 is formed. By forming this upper electrode layer 37, the information storage capacitive element C having a so-called stacked structure is substantially completed, and the memory cell M of the DRAM is completed.

After completing this memory cell M, the etching mask is removed.

Next, as shown in FIG. 15, the substrate 20 is subjected to thermal oxidation treatment to form an insulating film (Si02 film) 38 on the surface of the upper electrode layer 37 of the information storage capacitive element C. This insulating film 38 is formed in a step of oxidizing the etching residue (polysilicon film) remaining on the underlying surface (the surface of the interlayer insulating film 33) when the upper electrode layer 37 is patterned.

Next, in the formation region of the p-channel MOS-FET Qp of the peripheral circuit, the interlayer insulating film 33 formed in the above process is anisotropically etched, and as shown in FIG. Sidewall spacers 33C are formed on the sidewalls. This sidewall spacer 33G is formed in a self-aligned manner with respect to the gate electrode 27 of the p-channel MOS-, FETQp. Sidewall spacer 33C is a p-channel MOS-FET
The side wall spacer 31(7)'r'-) of Qp is formed to have a longer dimension in the longitudinal direction. The total dimension of the sidewall spacers 31.33C in the gate length direction is about 200 [nm3].

Next, an insulating film (not shown) is deposited over the entire surface of the substrate 20.

This insulating film is mainly used as a contamination prevention film when introducing impurities. This insulating film is composed of a Sin film deposited by a CVD method using, for example, inorganic silane gas and nitrogen oxide gas as source gases, and has a thin film thickness of about 10 (nm).

Next, in this embodiment, using the large current type ion implantation apparatus 1, as shown in FIG.
A p-type impurity 39p is introduced into the formation region of the OS-FETQp. When introducing the p-type impurity 39p, the sidewall spacers 31 and 33C are mainly used as impurity introduction masks.

Further, the region other than the formation region of the p-channel MOS-FET Qp is covered with an impurity introduction mask (photoresist film) not shown. , (or B), 50-70 (KeV)
It is introduced by ion implantation method with a certain amount of energy. that time,
The rotating disk 13 of the ion implanter 1 is rotated to 125 Orp.
Ion implantation is performed for about 10 minutes while rotating at a speed of m.

Thereafter, as shown in FIG. 18, the p-type impurity 39p is stretched and diffused by heat-treating the substrate 20, thereby forming a p-type semiconductor region 39. The above heat treatment is performed at a high temperature of, for example, 900 to 1000 [℃] for 20 to 20 minutes.
Do this for about 40 minutes.

By forming the p-type semiconductor region 39, the LD
P-channel MO3/FETQ of peripheral circuit with D structure
p is completed.

In this way, in the DRAM manufacturing method of this embodiment, the substrate 201. : 10'' (atoms/crl: 1) A step of ion-implanting impurities at a high concentration, that is, into the n4 type semiconductor region 32 of the n-channel MO3-FETQn of the peripheral circuit, and the p-channel MO3-FETQ of the peripheral circuit.
By using the ion implantation device 1 in the step of forming the p-type semiconductor region 39, contamination of the substrate 20 due to sputtering from the ion implantation device 1 can be reduced.

As a result, defects induced in the substrate 20 during ion implantation can be efficiently recovered by the subsequent low-temperature (approximately 900 to 1000 (t)) heat treatment. It is possible to prevent deterioration of the DRAM and improve the manufacturing yield of DRAM.

As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.

In the above embodiment, the substrate 20 has 10101sCatO/c.
I! ! ] Although the case where the application is applied to a large current type ion implantation device used in the process of introducing impurities at a high concentration of like,
It can also be applied to a medium current type ion implantation device used in a process of introducing impurities with a medium concentration of about 1012 to 10'3 (atoms/cat).

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.

By using an ion implanter structure in which at least the surface of the member provided on the ion beam path is made of high-purity silicon, it is possible to effectively prevent contamination of the substrate by sputtering from the ion implanter, and to prevent the substrate from being contaminated during ion implantation. Since the induced defects can be efficiently recovered by subsequent heat treatment, it is possible to prevent deterioration of the electrical characteristics of the element due to the defects and improve the manufacturing yield of semiconductor integrated circuit devices.

[Brief explanation of drawings]

FIG. 1 is a plan view taken along the line I--I in FIG. 2 showing a part of an ion implantation device according to an embodiment of the present invention, and FIG. 2 is a perspective view showing a part of this ion implantation device. FIG. 3 is a sectional view showing a part of an ion implantation device according to another embodiment of the present invention, FIG. 4 is a schematic front view of this ion implantation device, and FIGS. FIG. 2 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device using an injection device. 1... Ion implanter, 2... Ion source, 3.3a
, 3b... Extraction electrode, 4... Extraction slit, 5
... Mass spectrometry system, 6 ... Analyzer, 7 ... Analysis slit, 8 ... Liner, 9 ... Accelerator tube, 10 ...
- Accelerating electrode, 11... Converging lens, 12... Injection chamber, 13... Rotating disk, 14... Beam stopper, 15... Substrate holder, 16... Core material, 17
・・Thin film, 18 ・ ・・Slit, 20 ・
- Semiconductor substrate (wafer), 21...n-type well region, 22...p-type well region, 23...field insulating film, 24.25A...p-type channel stopper region, 25B, 30... p-type semiconductor region, 26...
Gate insulating film, 27...gate electrode (word line WL>
, 28.33... interlayer insulating film, 29... n-type semiconductor region, 29n, 32n... n-type impurity, 30p, 39
p...p type impurity, 31.33B, 33C...side wall spacer, 32.=n+ type semiconductor region, 33
A, 34... Connection hole, 35... Lower electrode layer, 35A
. 35B...Polysilicon film, 36...Dielectric film, 3
6A...5I3NJ membrane, 36B...5i02 membrane, 3
7... Upper electrode layer, 38... Insulating film, 39...p
°-shaped semiconductor region, ■, ion beam.

Claims (1)

[Scope of Claims] 1. An ion implantation device characterized in that at least the surface of a member provided on the path of an ion beam is made of high-purity silicon. 2. The ion implantation apparatus according to claim 1, wherein the silicon has a purity of 99.9999% or more. 3. The ion implantation apparatus according to claim 1, wherein the member is made of a conductive material and has a thin film of high purity silicon formed on its surface. 4. The ion implantation apparatus according to claim 1, wherein the member is made of high-purity silicon, and its resistance value is reduced by irradiation with neutrons. 5. The ion implantation apparatus according to claim 1, wherein at least a portion of the member that is irradiated with the ion beam is made of high-purity silicon. 6. A method of manufacturing a semiconductor integrated circuit device, comprising forming a semiconductor region having a predetermined impurity concentration by introducing impurities into a semiconductor substrate using the ion implantation apparatus according to any one of claims 1 to 5. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the semiconductor regions are a source region and a drain region of a MOS/FET.