JPH03269940A - Manufacture of ion implantation device and semiconductor integrated circuit device thereof - Google Patents

Abstract

PURPOSE:To prevent the contamination on a substrate by covering the path of an ion beam with a specified material. CONSTITUTION:The surface or the member itself of each of the members, which are provided on the ion beam path 1a inside an ion implantation device 1, that is, a lead slit 4, a lead electrode 3, a analysis slit 3, a liner 8, an accelerating electrode 10, a focusing lens 11, a slit 18, a substrate holder 15, and a beam stopper 14 are constituted of highly pure silicon. The substance which is created when the surface of these members are sputtered with ion beams Ia becomes the substance the same in composition as the substrate 20, and the pollution of the substrate can be avoided. Moreover, the content of the elements other than silicon contained in this substance is extremely small, so the contamination on the substrate 20 by the impurities such as heavy metal, etc., can also be avoided. This way, the contamination on the substrate by the sputtering of the ion implantation device can be avoided effectively, and the defects induced in the substrate in ion implantation can be restored efficiently by the later heat treatment, so the deterioration of the electric properties of the element resulting from these defects can be prevented, and the yield rate of the semiconductor integrated circuit can be improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to ion implantation technology used in the manufacturing process of semiconductor integrated circuit devices, and is an effective technology applied to cleaning ion implantation equipment in ↑1f. It is related to.

[Conventional technology]

In the manufacturing process of semiconductor integrated circuit devices, semiconductor regions (pn junctions) such as well regions, channel stopper regions, source and drain regions are formed by introducing impurities into the semiconductor substrate (wafer) using ion implantation technology. ing. The ion implantation method has the advantage that the impurity concentration of the substrate can be controlled more precisely than the thermal diffusion method because the dose of impurity ions can be measured. or.

Since the energy of the impurity ions can be controlled, this method has the advantage that the impurity profile of the substrate can be controlled more precisely than the thermal diffusion method.

Furthermore, the so-called S I M OX (Separate
on by Implanted Oxygen) technology,
In other words, in the ion implantation equipment used for the technology of forming SiO2 film by high-X oxygen implantation, in order to prevent contamination caused by sputter from the ion beam passage, the inner cylinder of the beam passage tube is Documents that disclose the installation of quartz tubes or quartz covers include Izumi et al., Nuclear, Instruments, and Merritts in Physics Research B37/38 (1989) 299-3C?3. , published by North Holland (nuclear Ins.
trument's and +ncthods
in physics RQsearch B3
7/38 (1989) 299303゜noth-11
alland).

[Problem to be solved by the invention]

However, since the ion implantation method introduces high-energy impurities into the substrate, there is a problem in that defects are easily induced in the substrate, and the electrical characteristics of the device deteriorate due to these defects. Therefore, after ion implantation, annealing treatment is essential to recover defects induced in the substrate and to electrically activate the implanted impurity ions.

However, in recent years megabit (Mbit) class memory LS
In VLSIs manufactured according to submicron design rules such as I (Si monolithic type), it is necessary to form an extremely shallow pn junction of about 0.1 to 0.2 μm in the active region of the substrate, and the process is difficult. Since low temperature is essential, the annealing process after ion implantation must also be performed at low temperature.Therefore, in the VLSI manufacturing process, contamination of the substrate during ion implantation, which hinders defect recovery, must be reduced as much as possible. , it is necessary to efficiently recover defects.

One of the causes of substrate contamination during ion implantation is sputtering from an ion implanter using an ion beam. this is,
When the ion beam generated from the ion source of the ion implantation device passes through the extraction electrode, analyzer, analysis slit, etc. inside the device, a portion of the ion beam collides with these, causing sputtering on the surface of the device. This is a phenomenon in which substances adhere to the surface of a substrate or are driven into the substrate by ions. Members such as extraction electrodes, analyzer inner walls, and analysis slits of the ion implanter are coated with graphite or aluminum, so if their surfaces are sputtered, the substrate will be contaminated with carbon or aluminum. Also.

For example, graphite has a purity of 99.99 to 99.99.
Since it is as low as about 999%, heavy metals such as Fe and Cu that are contained as impurities in graphite cannot be avoided.Especially in the case of sources, drains, and regions of MOS-FETs, about 10" [atoms/af?3] When forming a semiconductor region with a high impurity concentration, a large current type ion implantation device with a large beam current is used, so a large amount of contaminants are generated by sputtering, and contamination of the substrate becomes a serious problem.

Furthermore, a cover made of an insulating material such as quartz cannot prevent charge-up in that area.

When oxygen is sputtered and implanted into a Si substrate, etc.,
Knock-on phenomenon and other harmful effects cannot be avoided.

An object of the present invention is to provide a technique that can effectively prevent contamination of a substrate caused by sputtering of an ion implanter.

One object of the present invention is to provide an ion implantation apparatus that can perform ion implantation while stably cooling the temperature of a wafer to 0° C. or lower.

One object of the present invention is to provide an ion implantation apparatus that can effectively prevent wafer charge-up.

One object of the present invention is to provide an ion implantation apparatus that does not cause contamination from wafers, stoppers, etc.

One object of the present invention is to provide an ion implantation apparatus having a vacuum evacuation system capable of maintaining a high vacuum throughout the ion implantation path.

One object of the present invention is to provide an ion implantation apparatus suitable for multivalent ion implantation or molecular ion implantation.

One object of the present invention is to provide an ion implantation apparatus having a dew condensation prevention mechanism that can prevent dew condensation when taking out a wafer to the outside.

One object of the present invention is to provide an ion implantation apparatus that does not cause electrostatic damage to the wafer even if the electron shower fails.

One object of the present invention is to provide an ion implantation technique that allows an implanted layer to be defect-free even during low-temperature annealing at 900 to 800° C. or lower.

One object of the present invention is to provide an ion implantation technique that allows a deep implantation layer to be defect-free.

One object of the present invention is to provide a method for fabricating a semiconductor integrated circuit device suitable for forming a fine diffusion layer (doped layer).

One object of the present invention is to provide a high-throughput ion implantation technique.An object of the present invention is to provide an impurity doping technique that can form a fine and deep diffusion layer (doped Pa). One object of the present invention is to provide an ion implantation technique that is compatible with design rules of 0.5 to 0.3 μm and smaller.

One object of the present invention is to provide an ion implanter having an exhaust system that can maintain the degree of vacuum in the latter stage accelerator tube at approximately 5×10 Torr during implantation.

One object of the present invention is to provide an ion implantation device capable of implanting ions while maintaining the wafer temperature at 0° C. to −50° C. or lower.

One object of the present invention is to create a semiconductor integrated circuit bag having a shallow defect-free diffusion layer (doped, I!) of about 0.1 μm or less!
! Our goal is to provide a method for making and using products.

[Means to solve the problem]

A brief summary of one typical invention disclosed in this application is as follows.

One invention of the present application is an ion implantation device in which at least the surface of a member provided on the path of an ion beam is made of high-purity silicon.

[Effect]

According to the above-mentioned means, the material generated when the surface of the member provided on the path of the ion beam is sputtered is
Since the material (silicon) has the same composition as the substrate, it does not become a source of contamination of the substrate. Also, silicon has a purity of 99
．． Since the purity can be increased to 99999999% or more, contamination of the substrate by impurities such as heavy metals contained in the above substances is also avoided.

Furthermore, the outline of other 1'JJ methods for achieving the above object and their effects will be explained.

(1) By cooling the wafer temperature during implantation to 0° C. to 100° C. (and further 0° C.), defects occurring during implantation are reduced and crystal defects are prevented.

As for the cooling method, ■ Coolant cooled by a refrigerator is passed through the contact area on the back of the wafer, and the contact area is heated to about 0℃ to -120℃ (
Further, the wafer is cooled to about -200° C. 6 Furthermore, in order to improve heat conduction between the wafer and the cooling section, gas is introduced between the wafer and the cooling surface. ■As a cooling method for the wafer back surface contact area, the principle of a cryopump is applied and the cooling unit is used as a cold head. Thereby, the cooling section is cooled to -20°C to -120°C (further to about -200°C). In this case as well, gas is introduced between the wafer and the cooling surface to improve thermal conductivity.

It also prevents dew condensation when the wafer is taken out into the atmosphere after implantation. For this reason, ■After implantation in vacuum,
The wafer is heated using an infrared lamp to a temperature that does not cause condensation. ■After implantation, the wafer is transferred from the implantation chamber to the preliminary vacuum chamber and gradually returned to atmospheric pressure using dry heated nitrogen.

(2) The following functions will be added to the electronic 2-wire safety device to prevent electrostatic damage to devices on the wafer surface. In other words, in conventional electronic shower generators, if a problem occurs during implantation and the electron shower is cut off, electrons may not be supplied for a period of time (several tens of milliseconds to several tens of milliseconds).
c) There is a possibility that the device may be destroyed during this time. To prevent this, the electron shower (electron emission current) monitor and the ion source or extraction electrode power supply are electrically linked to prevent the electron shower from occurring during implantation. Even if a failure occurs in the generator, the ion beam is shut off at the same time as the failure occurs, thereby preventing device destruction.

(3) When the beam hits a wafer stopper or the like that holds the wafer, the material aluminum and impurities contained therein are sputtered and contaminate the wafer. To prevent this, 1. Eliminate the mechanical stopper and fix the wafer with an electrostatic chuck to prevent the ion beam from hitting anything other than the wafer. ■Improved purity of mechanical stopper (3N or 99.9
% or more) and improve the shape of the surface that is hit by the beam to prevent sputtered materials from flying onto the wafer.

(4) In order to prevent energy contamination during multivalent ion or molecular ion implantation, the ion implantation device is provided with the following functions. ■A beam filter is installed at the exit of the mass spectrometry tube to remove contaminant ions generated between the ion source and the mass spectrometry tube exit. ■A high vacuum pump is installed between the mass spectrometry tube and the second stage acceleration tube, and the degree of vacuum inside the second stage acceleration tube is adjusted from the mass spectrometry tube outlet to the second stage acceleration tube to (distance to the exit of the accelerator tube)). ■ High vacuum pumps are installed in two locations: between the mass spectrometry tube outlet and the post-acceleration tube, and on the exit side of the post-acceleration tube.
Aim to obtain the same degree of vacuum as in ① above.

(5) In order to prevent the introduction of contamination due to sputtering from each electrode in the ion path, each electrode, i.e., the extraction electrode of the ion source, the analysis slit of the mass spectrometer, the beam, the filter slit, At least the part of the trench (wafer, stopper, etc.) that is likely to be sputtered or the surface of that part is covered with a conductive material that does not act as contamination even if sputtered. The entire electrode plate may be made of such material (high purity).

That is, when the wafer to be processed is Si, it is sufficient to use appropriately doped Si in that portion.

For example, a disk cut out from a Si ingot with a resistivity of about 10Ω, which is grown by a pulling method using a 99.9999999% Si material and adding an appropriate single or several types of impurities, is processed. Used as the above electrode.

This makes it possible to form an ion path without charge-up and without contamination.

(6) Generally, in ion implantation, the beam is further deflected by about 30' after mass analysis in order to improve the purity of the ions. However, in the present invention, in order to efficiently implant a high-purity ion beam, the beam path is made as short as possible without effectively deflecting the entire beam (excluding the converging lens of the beam itself) after one analysis. The beam is made to be incident on the wafer to be processed.

Furthermore, in response to the miniaturization of devices, the beam is arranged to be incident perpendicularly to the surface of the wafer to be processed in order to minimize shadow effects.

〔Example〕

(1) Example 1 FIG. 4 shows the main parts of an ion implantation apparatus which is Example 2 of the present invention.

This ion implanter 1 is a large current type ion implanter that generates a beam current of 1 to 20 (mA) or more at maximum, and an ion source 2 provided at one end of the ion implanter 1 emits ions, for example, from a filament in a magnetic field. It has a mechanism that uses thermoelectrons to generate ions from gaseous elements. The ions generated by this ion source 2 are connected to the ion source 2 and the extraction 'W
! The ion implantation beam 1. is extracted from the extraction slit 4 by a voltage applied between the ion implantation beam 1. bawl.

Fj! to the above extraction electrode 3! IF! ! A mass spectrometry system 5 installed at the ion source 2 selects ion species necessary for injection from among the various ions generated by the ion source 2. and an analysis slit 7 placed at its focal point.

A liner 8 is attached to the side wall of the path through which the ion beam I. This prevents dissolution of the sidewalls and contamination of impurities due to irradiation.

The acceleration tube 9 provided adjacent to the mass spectrometry system 5 applies a predetermined energy to the ion species selected by the mass spectrometry system 5. This accelerating tube 9 has a multi-stage structure consisting of a plurality of accelerating electrodes 10, and has a structure in which ions are accelerated by an electric field formed between each accelerating electrode 10.

The ion beam (2), which has been given energy by the accelerating tube 9, is focused by a converging lens 11 and introduced into the implantation chamber 12 via the sliver 18. A rotating disk 13 is provided at the center of the implantation chamber 12, and a beam stopper 14 for converging the ion beam Is is provided behind the rotating disk 13.A substrate (wafer) ) 20 for fixing the substrate holder 15
are provided at predetermined intervals. That is, this ion implantation apparatus 11 employs a batch method in which ions are implanted into a plurality of substrates 20 at once. During ion implantation, the substrate holder 1 is moved vertically or horizontally while rotating at high speed.
The ion beam I is applied uniformly over the entire surface of the substrate 20 fixed on the substrate 5.
, is irradiated.

In this embodiment, among the members constituting the ion implantation apparatus 1, the members provided on the path (beam line) of the ion beam 11, namely, the extraction slit 4, the extraction electrode 31, the analysis slit, the liner 8, the acceleration Each surface or member of the electrode 10, converging lens 11, slit 18, substrate holder 15, and beam stopper 14 is made of high-purity silicon.

For example, the analysis slit 7 shown in FIGS. 1 and 2 has a structure in which a thin film 17 of high-purity silicon is adhered to the surface of a graphite core material 16 processed into a disk shape.

Although not shown, the drawer slit 4. Extraction electrode 3
, the liner 8, the accelerating electrode 10, the converging lens 11, the slit 18, the substrate holder 15, and the beam stopper 14 each have a core material 16 made of graphite or aluminum.
It has a structure in which a high purity silicon thin film 17 is deposited on the surface.

The thin film 17 is made of amorphous silicon deposited on the surface of the core material 16 by, for example, the CVD method,
It has a membrane thickness of about 100 μm.

This amorphous silicon is 99.99999999
% (so-called ten nines) or more. Amorphous silicon constituting the thin film 17 can also be deposited by sputtering. In this case, sputtering is performed using a single crystal silicon or polycrystal silicon target having a purity of ten nines or higher.

Each of the members provided on the path of the ion beam
It may be composed of low resistance silicon (doped silicon) having 0 to several 100 culms. Further, the thin film 17 may be made of not only the amorphous silicon but also silicon having a purity of ten nines or higher grown on the surface of the core material 16 by an epitaxial method.

A part of the member provided on the path of the ion beam Im may be made of silicon having a purity of ten nines or higher. In this case, since the member is insulating, at least its surface is made to have a low resistance by irradiation with a neutron beam or doping with impurities in order to prevent the adverse effects of charge-up.

Each of the members provided on the path of the ion beam [1] may be made of high-purity silicon only at the portions that are irradiated with the ion beam [1].

That is, the analysis slit 7 shown in FIGS. 1 and 2 is
A thin film 17 of high-purity silicon is coated on the entire surface of the graphite core 16. For example, as in the analysis slit 7 shown in FIG.
A thin film 17 of high-purity silicon may be deposited only on the portions that are irradiated.

In this way, the ion implantation apparatus 1 of this embodiment has an ion beam 1. An extraction slit 4, an extraction electrode 3, an analysis slit 7, a liner 8, an accelerating electrode 10, provided on the path of
Since the surfaces of each of the converging lens 11, slit 18, substrate holder 15, and beam stopper 14 were coated with silicon having a purity of ten nines or higher, when the surfaces of these members were sputtered with the ion beam 113, The substance generated in this process has the same composition as the substrate 20, and contamination of the substrate 20 is avoided.

Further, since the content of elements other than silicon contained in this substance is extremely small, contamination of the substrate 20 by impurities such as heavy metals is also avoided.

Next, the ion implantation bag mentioned above? An example of a method for manufacturing a semiconductor integrated circuit device using L1 will be described. This manufacturing method is D
R A M (Dynamic Random Ac
The memory cell selection MOS-FETQS and peripheral circuit devices that constitute the memory cells of
II This is applied to a method of manufacturing a certain n-channel MOS-FETQn and p-channel MOS-FETQP.

Below, the specific manufacturing method is shown in Figures 5 to 18.
This will be explained using figures (cross-sectional views of main parts shown for each manufacturing process). Note that this DRAM has a capacity of, for example, 16 megabits (Mb).
jt) and is manufactured according to the so-called 0.5 [μm] design rule, which sets the minimum processing dimension to 0.5 [μm].

FIG. 5 is a cross-sectional view of a main part of the semiconductor substrate (wafer) 20 in the middle of the manufacturing process of this DRAM.
The memory cell formation region (left side of the figure) of the substrate 20 made of silicon single crystal and the n-channel MOS-F of the peripheral circuit.
P on each main surface of the ETQn formation region (center of the figure)
A - shaped well region 22 is provided. This P-type well region 22 is, for example, 1012-10" (atoms
B (or B F,) with an impurity concentration of about /-) is 20
After introduction by an ion implantation method with an energy of about 30 (KeV), the substrate 20 is formed by heat-treating the substrate 20 in an atmosphere at a high temperature of about 1100 to 1300 [° C.].

An n-type well region 21 is provided on the main surface of the p-channel MOS-FET Qp forming region (right side in the figure) of the peripheral circuit device. This n''-type well region 21 is, for example, 1
P(
After introducing phosphorus (phosphorus) by an ion implantation method with an energy of about 120 to 130 (KeV), the substrate 20 is
It is formed by heat treatment in an atmosphere of about 000 ('C).

The main surface of each of the well regions 21 and 22 has a 400
A field insulating film 23 for element isolation having a film thickness of about 600 [nm] is provided. This field insulation [23] is formed by a selective oxidation method (LOCO8 method).

In the peripheral circuit young formation region, a P-type channel stopper region 24 is provided below the field insulating film 23 of the P-type well region 22 . The P-type channel stopper region 24 is formed, for example, on the main surface of the p-type well region 22 by LO''.
After introducing BF with an impurity concentration of about (at o m-s /aj) by ion implantation with an energy of about 50 to 70 [Kcv], a trace amount of oxygen (approximately 1% or less) is introduced.
In a nitrogen gas atmosphere containing
Heat treatment is carried out at a high temperature of about 1150 [°C] for about 30 to 40 [minutes], and then steam oxidation is performed for about 30 to 50 [minutes].
It is formed by oxidation of about 10 minutes. By this heat treatment, the impurity introduced into the main surface of the P-type well region 22 is stretched and diffused, and the p-type channel stopper region 24 is formed by substantially the same manufacturing process as the formation of the field insulating film 23.

A p-type channel stopper region 25A and a p-type semiconductor region 25B are already formed on the main surface of the memory cell formation region. P-type channel stopper region 25A is provided under field insulating film 23, and p-type semiconductor regions 2 and 5B are provided in the active region. p-type channel stopper region 2
5A and p-type semiconductor region 25B, for example, 10
``B with an impurity concentration of about 1013 [atoms/a#]
Form 7 can be obtained by introducing ion implantation with high energy of about 200 to 300 (K e V). P
The P-type channel stopper region 25A is formed by introducing the above-mentioned impurity through the field insulating film 23, and the P-type semiconductor region 25I3 is formed by introducing the above-mentioned impurity through the field insulating film 23.
It is formed at a deep position in the main surface of the P-type well region 22 by an amount corresponding to the film thickness of 3.3.

The active area of each well region 22.21 includes 12
Gate insulating film 26 having a film thickness of about 18 [nm]
is provided. This gate insulating film 26 is made of, for example, S
It is formed by steam oxidizing the substrate 20 at a high temperature of about OO to 1000 ('C).

On each of the field insulating film 23 and the gate insulating film 26 in the memory cell formation region, an MO8 for memory cell selection is provided.
- A gate electrode 27 of FETQs is provided. Gate electrode 2 of MO5-FET Qs for memory cell selection
7 is the gate M edge film 2 of the p-type well region 22 in the formation region of one peripheral circuit which also serves as a word line (WL).
Above 6.

A gate electrode 27 of an n-channel MOS-FETQn is provided, and a gate electrode 27 of a p-channel MO8-FETQρ is provided on the gate insulating film 26 of the no-type well region 21. These gate insulators 11g27 are made of a polysilicon film having a thickness of about 200 to 300 (nm), for example. An n-type impurity (P or As) is introduced into this polysilicon film to reduce the resistance value.

To form the gate electrode 27, for example, first, polysilicon is deposited on the entire surface of the substrate 20 by the CVD method.

After introducing n-type impurities into this polysilicon film by a thermal diffusion method, a SiO2 film (not shown) is formed on the surface by a thermal oxidation method, and then this Si is deposited.

A glabellar insulating film 28 having a thickness of, for example, about 250 to 350 (nm) is deposited on the entire surface of the film. This interlayer insulating film 28 is formed, for example, by a CVD method using inorganic silane gas and nitrogen oxide gas as source gases. Next, the gate electrode 27 is formed by anisotropically etching the glabella insulating film 28 and the polysilicon film using a photoresist mask (not shown). Note that the gate electrode 27 is made of a high melting point metal (Mo, Ti, Ta, W) film or a high melting point silicide (Mo Si z + Ti Si,, t
aS i,.

It may be composed of a single layer of WSi, ) film. Further, the gate electrode 27 may be formed of a composite film in which the above-mentioned high melting point metal film or high melting point metal silicide film is laminated on a polysilicon film.

Next, as shown in FIG. 6, an n-type impurity 29 is introduced into the main surface of the P-type well region 23 using the field insulating film 23 and the interlayer insulation 11i28 (gate electrode 27) as an impurity introduction mask. This n-type impurity 29n is introduced into the gate electrode 27 in an accidental matching manner. The D-type impurity 29n is, for example, 10” (at oms/cJ)
Using P (or A s ) with an impurity concentration of about 3
It is introduced by ion implantation with an energy of about 50 (K e V). Although not shown, n-type impurity 2
When introducing 9n, the main surface of the n-type well region 21 is covered with an impurity introduction mask (for example, a photoresist film).

Next, using the field insulation film 23 and the interlayer insulating film 28 (gate electrode 27) as an impurity introduction mask, a P-type impurity 30ρ is introduced into the main surface of the n-type well region 21.

This ρ type impurity 30p is introduced into the gate electrode 27 in a self-aligned manner.

The p-type impurity 30p is, for example, 10" (atoms/, f
B (or B F2) having an impurity concentration of about f1) is introduced by ion implantation with an energy of about 20 to 30 (KeV). Although not shown, when introducing the P-type impurity 30, the main surface of the P-type well region 22 is covered with an impurity introduction mask (photoresist film).

Next, as shown in FIG. 7, sidewall spacers 31 are formed on each sidewall of the gate electrode 27 and the glabellar insulating film 28 thereon. For example, the sidewall spacer is formed by depositing four Si films using inorganic silanka gas and nitrogen oxide gas as source gases by CVD method, and then
O, film thickness (for example, about 130 to 180 (nm))
It is formed by performing anisotropic etching such as RIE. The length of the sidewall spacer 31 in the gate length direction (channel length direction) is approximately 150 [n
m].

Next, in this embodiment, the large current type ion implantation device 1 is used to implant an impurity 32n in the n-channel MOS-FETQn type shadow region forming peripheral circuit. When introducing this n-type impurity 32, the sidewall spacer 31 is mainly used as an impurity introduction mask. Also, n-channel MOS
- The region of the FET Qn type hole-locking formation is covered with an impurity introduction mask (photoresist film) not shown. The n-type impurity 32n is, for example, 10” (,1toms/Ci)
Using As (or P) with an impurity concentration of about 70 to 9
It is introduced by an ion implantation method with an energy of about 0.0 (KeV). At that time, the rotating disk 13 of the ion implantation bag 5i1
Ion implantation was performed for about 10 minutes while rotating at a speed of 1250 rpm.

Next, as shown in FIG.
, P-type impurity 30p is diffused in the n-type semiconductor region 29 of the memory cell selection MO5/FETQs, and the n-type semiconductor region 29 of the n-channel MOS-FETQn of the peripheral circuit. N-medium semiconductor region 32, p-type semiconductor region 3 of P-channel MO5-FETQp of peripheral circuit
form each of the 0's. The heat treatment described above is, for example, 9
The process is carried out for about 20 to 40 [minutes] at a high temperature of about 0.00 to 1000°C.By forming the n-type semiconductor region 29, the memory cell selection MO8-FETQs of the memory cell is
is completed. Further, by forming the n-type semiconductor region 29 and the n+-type semiconductor region 32, the n-channel MO8-FETQn of the peripheral circuit having the LDD structure is completed.

Note that the p-channel MO8-FETQp of the peripheral circuit is L
Only the P-type semiconductor region 30 forming part of the DD structure is completed.

Next, Glabella 9rrA33 is deposited on the entire surface of the substrate 20. This layer-side insulating film 33 is used as an etching stopper layer when processing an electrode layer of an information storage capacitive element C of a memory cell, which will be described later. The glabella insulating film 33 also serves as the lower electrode layer of the information storage capacitive element C and the memory cell selection MO.
It is formed to electrically isolate the gate electrode 27 (word line WL) of the 8-FET QS. The interlayer insulating film 33 is formed to increase the thickness of the sidewall spacer 31 of the P-channel MO5-FET'Qp.

The glabellar insulating film 33 is made of, for example, Sin deposited by a CVD method using inorganic silane gas and nitrogen oxide gas as source gases.
It is composed of a film and has a film thickness of about 130-1.80 (nm).

Next, as shown in FIG. 9, the memory cell selection MO8-
The interlayer insulating film 33 on one n-type semiconductor region (the side to which the lower electrode layer of the information storage capacitive element C is connected) 29 of the FETQS is removed to form connection holes 33A and 34, respectively. This connection hole 34 is connected to the side wall spacer 311
It is formed in a region defined by each sidewall spacer 33B deposited on the side walls of the sidewall spacer 31 when the interlayer insulating film 33 is etched.

Next, as shown in FIG. 10, a polysilicon film 35A that will become the lower electrode layer of the information storage capacitor C of the memory cell is deposited on the entire surface of the substrate 20. This polysilicon film 35A
A portion thereof is connected to the n-type semiconductor region 29 through each of the connection holes 33A and 34. This polysilicon film 35A is deposited by the CVD method and has a density of 150-250 (n
It has a film thickness of about m). This polysilicon film 35
An n-type impurity such as P, which reduces the resistance value after deposition, is introduced into A by a thermal diffusion method. A large amount of this n-type impurity is diffused into the n-type semiconductor region 29 through the connection hole 34, and is prevented from being diffused toward the channel formation region side of the memory cell selection MO5-FET Qs.

Introduced with low impurity a degree.

Next, as shown in FIG.
A polysilicon film 35B is deposited on A. The upper layer of polysilicon 1ii35B is deposited by the CVD method.
It has a film thickness of about 50 to 350 [nm]. An n-type impurity such as P, which reduces the resistance value after deposition, is introduced into the upper polysilicon film 35B by thermal diffusion. This n-type impurity is introduced at a high impurity concentration in order to improve the amount of charge storage in the information storage capacitive element C.

Next, as shown in FIG. 12, the two-layered polysilicon films 35A and 35B are processed into a predetermined shape using photolithography technology and anisotropic etching technology, and the lower layer of the information storage capacitive element C is etched. An electrode layer 35 is formed.

Next, as shown in FIG. 13, a dielectric film 36 is deposited on the entire surface of the substrate 20. The dielectric film 36 is made of, for example, Si, N4
A two-layer structure is formed in which the film 36A and the 5in2 film 36B are sequentially laminated. Si, N4rIIA36A is, for example, CVD
When Si, N41F236A is deposited on the lower electrode layer 35 (polysilicon film) at a normal production level, it has a film thickness of about 5-5-7 (n). Since the entrainment of oxygen occurs, the Si, N4 film 36
Between the lower electrode layer 35 and the lower electrode layer 35 there is a natural oxide film (
S i O.

membrane) is formed.

The upper layer of the dielectric film 36, the Si film 36B, is formed by applying a high-pressure oxidation method to the lower layer Si and N4 film 36A.
It has a film thickness of about 3 (nm).

Next, a polysilicon film (not shown) is deposited over the entire surface of the substrate 20. The polysilicon film was deposited by CVD method and
It has a film thickness of about -120 (nm). After deposition, an n-type impurity such as P, which reduces the resistance value, is introduced into the polysilicon film by thermal diffusion. Subsequently, an etching mask (not shown) is applied over the polysilicon film over the entire memory cell formation region except for the connection region between one n-type semiconductor region 29 of the memory cell selection MO8-FETQs and a complementary data line to be described later. photoresist film) is formed.

Thereafter, as shown in FIG. 14, the polysilicon film and the dielectric film 36 are each subjected to first-order anisotropic etching using the etching mask to form the upper electrode layer 37 of the information storage capacitive element C. Form. On top of this, rl extreme W! 37
By forming this, the information storage capacitive element C having a so-called stacked structure is almost completed, and the memory cell M of the DRAM is completed.

After completing this memory cell M, the etching mask is removed.

Next, as shown in FIG. 15, the substrate 20 is subjected to thermal oxidation treatment to form an insulating film (SiO2 film) 38 on the surface of the upper electrode layer 37 of the information storage capacitive element C. This insulating film 38 is formed in a step of oxidizing the etching (polysilicon film) remaining on the underlying surface (the surface of the interlayer insulating film 33) when the upper electrode layer 37 is patterned.

Next, in the formation region of the p-channel MO8-FETQp of the peripheral circuit, the interlayer insulating film 33 formed in the above-described step is etched.

As shown in FIG. 16, the side wall spacer 3
A side wall spacer 33C is formed on the side wall of 1.

This sidewall spacer 33C is for p-channel O
It is formed in white and self-aligned with the gate electrode 27 of the 5-FET Qp. Sidewall spacer 33C is sidewall spacer 3 of P-channel MO5-FETQp.
1 in the gate length direction.

The total dimension of the sidewall spacers 31.33C in the gate length direction is about 200 (nm).

Next, an insulating film (not shown) is deposited on the entire surface of the substrate 20.

This insulating film is mainly used as a contamination prevention film when introducing impurities. This insulating film is made of S
It is composed of an iO2 film and has a thin film thickness of about 10 (nm).

Next, in this embodiment, a p-type impurity 39p is introduced into the formation region of the p-channel MO3-FETQp of the peripheral circuit, as shown in FIG. 17, using the large current type ion implantation device a1. When introducing the p-type impurity 39p, the sidewall spacers 31 and 33C are mainly used as impurity introduction masks.

Further, the region other than the formation region of the p-channel 05-FETQP is covered with an impurity introduction mask (not shown) (photoresist film → mask).The p-type impurity 39p is, for example,
Using an impurity concentration BF (or B) of about 50 to 70 (K e V), the impurity is introduced by ion implantation with an energy of about 50 to 70 (K e V). At this time, ion implantation is carried out for about 0 minutes while rotating the rotating disk 13 of the ion implanter 1 at a speed of LOOORPM.

Thereafter, as shown in FIG. 18, the substrate 20 is heat-treated to stretch and diffuse the P-type impurity 39p, thereby forming a P-type semiconductor region 39. The above heat treatment is performed at a high temperature of, for example, 900 to 1000 [℃] for 2
Do this for about 0 to 40 minutes. The p+ type semiconductor region 39
By forming this, a P-channel MO8-FETQp of a peripheral circuit having an LDD structure is completed.

In this way, in the DRAM manufacturing method of this embodiment,
A process of ion-implanting impurities at a high concentration of about 10" (a t o m s / ad) into the substrate 20, that is, the n+ decagonal semiconductor region 32 of the n-channel MO3-FET Qn of the peripheral circuit and the p-channel MO3- of the peripheral circuit. FET-
The p-decade semiconductor region 39t of Qp! By using the ion implantation device 1 in the forming process, the ion implantation device 1
It is possible to reduce contamination of the substrate 20 due to sputtering. the result.

Defects induced in the substrate 20 during ion implantation can be efficiently recovered by subsequent low U (approximately 900 to 1000 ('C)) heat treatment.
Prevents deterioration of electrical characteristics of S-FETQn, Qp and improves DR
The manufacturing yield of AM can be improved.

Although the invention made by the present inventor has been specifically explained based on Examples above, it is to be noted that the present invention is not limited to the above-mentioned Examples and can be modified in various ways without departing from the gist thereof. Not even.

In the above embodiment, the substrate 20 has l O” (atoms/
Although the case has been described in which the present invention is applied to a large current type ion implantation device used in the process of introducing impurities at a high concentration of about Like-
Furthermore, it can also be applied to a medium current type ion implantation device used in a process of introducing impurities with a medium concentration of about 1012 to 1013 atoms/d.

Among the inventions disclosed in this example, the effects obtained by typical ones are briefly explained below.

By using an ion implanter structure in which at least the surface of the member provided on the path of the ion beam is made of high-purity silicon, contamination of the substrate due to sputtering from the ion implanter can be effectively prevented, and the substrate can be This is because the defects induced in the process can be efficiently recovered by subsequent heat treatment.

Deterioration of the electrical characteristics of the element due to this defect can be prevented, and the manufacturing yield of semiconductor integrated circuit devices can be improved.

(2) Example 2 First, an outline of Example 2 of the present invention will be explained with reference to FIGS. 19 to 21.

FIG. 19 shows an overall schematic diagram of a single ion implantation device. Although this figure shows a batch processing type high current type ion implantation device, a single wafer type device is also similar.

(1) The wafer cooling mechanism includes a refrigerant 217 cooled by a refrigerator 2L5 on a rotation stage 218 on which a wafer 213 is placed.
The wafer 213 is heated to 0°C to 100°C.
(and further to about -200°C).

Also, helium gas is used instead of this refrigerant.

The rotating stage 21 uses the refrigerator 215 as a helium compressor.
8 is cooled by adiabatic expansion of helium. In order to reduce the thermal resistance between the wafer 213 and the rotation stage 218, cooling auxiliary gas 219 is sealed in the gap between the wafer 213 and the rotation stage 218.

(2) The electronic shower monitor 211 of the electronic shower generator 210 and the ion source power supply 201 or the extraction electrode power supply 204 are electrically linked, and the ion source power supply 201 or the extraction electrode power supply 204 is connected to the electronic shower generator 210 at the moment when the electronic shower falls below the set value. By cutting the electrode type @204, the ion beam 221 is stopped and electrostatic damage to the wafer 213 is prevented.

(3) In order to improve the purity of multivalent iheons and molecular ions, a beam filter slit electrode 206 is provided at the exit of the mass spectrometer 205, so that the ions generated between the ion source 202 and the exit of the mass spectrometer 205 Eliminate energy contamination. For this purpose, a method such as applying a voltage of 50% or more of the extraction voltage to the beam filter slit electrode 206 is used. In addition, in order to prevent energy contamination ions from forming between the exit of the mass spectrometer 205 and the exit of the post-acceleration tube 208, a mechanical try (oil-free), vacuum exhaust system 20
7,209 and evacuate this area.

(4) FIG. 20 shows a holding section for the wafer 213.

FIG. 20(A) is a front view, and FIG. 20(B) is a side view.

As can be seen from FIG. 20(B), the ion beam 22
1 hits the wafer stopper 220, its material, aluminum, and impurities contained therein are generated by sputtering.

It adheres to the wafer 213. This countermeasure is shown in FIG.

The second t@(A) is a case in which the electrostatic chuck mechanism is used to hold the rewafer and no metal is placed on the periphery 911 of the wafer 213. In FIG. 21(B), the shape of the wafer stopper 220 is reversely tapered, and the ion beam 2
The shape is such that even if the wafer 21 hits the wafer 213, sputtered material (secondary ion beam) 222 is unlikely to fly to the wafer 213. FIG. 21(C) shows a case where the generation of the secondary ion beam 222 is prevented by making the wafer stopper 220 needle-shaped and minimizing the area hit by the ion beam 221.

Furthermore, by making the wafer stopper 2200 of the same material as the electrodes in the beam path, it is possible to prevent harmful effects caused by sputtering.

With each of the above configurations, the following effects can be obtained.

That is, by cooling the wafer, the expansion and incomplete recovery of defects that occur during ion implantation can be suppressed, so that an implanted layer without crystal defects can be obtained by low-temperature annealing, and a deep submicron device can be realized. Furthermore, by electrically interlocking the electron shower and the ion source power source, electrostatic damage to the wafer can be eliminated even when the electron shower generator fails. Furthermore, by improving the purity of the wafer holding part to 11'IJ and improving the shape, metal contamination of the wafer can be prevented, junction leakage current can be reduced, and crystal defects can be prevented from growing, improving the yield of deep submicron devices. can be achieved. Furthermore, by improving the degree of vacuum from the beam filter and mass spectrometer tube to the outlet of the downstream coupling tube, energy contamination during multivalent ion implantation or molecular ion implantation can be prevented.
This can prevent variations in device characteristics and improve yield.

Furthermore, by making the electrodes or slits on the ion beam path from conductive Si material, contamination due to undesired sputtering effects is significantly reduced even during high current injection.

Furthermore, since the beam after mass spectrometry is not deflected and enters the wafer surface perpendicularly through the shortest path, high throughput and fine machinability can be ensured.

Next, the details of each part of this ion implantation device are shown in Figures 19 to 2.
This will be explained using Figure 1. 201 is an ion source power supply that supplies current to the filament of the ion source 202, the electron shower generator 210, and the like. 202 is an ion source such as a Freeman source, and 203 is a try roughing pump and a turbo molecular pump for exhausting gas etc. discharged from the ion source 202, etc., such as SD manufactured by Kashiyama Industries Co., Ltd. An oil-free vacuum exhaust system consisting of a series dry pump and a KDM series molecular drag pump, etc. 204 is an extraction electrode power supply, and when the electronic shower generator 210 breaks down, the electronic shower monitor can be used. Due to the action of 211, this power supply 204 becomes 0 (V
), and ion extraction stops. 205 is a mass spectrometry section (mass spectrometry tube) that includes an analysis magnet 201 for selecting desired ions from extracted ions;
A beam filter slit electrode 206 is provided at the exit of the mass spectrometer 205. Like other slit electrodes, an aperture through which the ion beam 221 passes is provided in the center of a disk made of doped single crystal Si, etc. Alternatively, as will be explained later, a predetermined voltage is applied to the electrode plate.

Slit for beam filter? l! By applying a voltage of 50% or more of the extraction voltage (vO) to the pole 206, only desired ions are selected with high purity during multivalent ion implantation or molecular ion implantation.

Reference numeral 206' denotes a slit electrode similar to the above for allowing only ions that fly to a predetermined position to pass through due to the action of the analysis magnet 205'. 207 is a mechanical dry vacuum evacuation system with the same configuration as 203, 208 is a post-acceleration section (post-acceleration tube) consisting of about 5 to 0 slit electrodes similar to the previous one, and 209 is a mechanical dry vacuum evacuation system similar to 207. A vacuum evacuation system, 210 is a wafer 21 which will be explained earlier or later.
An electronic shower generator 211 adds electrons to the ion beam 221 in order to prevent damage caused by the charge amplifier 211. The electronic shower generator 211 monitors the current of the electronic shower generator 210, and when the current decreases by a certain value from the set value, , a 47% T shower monitor for stopping ion emission from the ion source 202 and pasting the charge abutment on the wafer 213; The implantation chamber 213 is a wafer into which ions are implanted, that is, a Si wafer, which is the most important part of a semiconductor integrated circuit device. 214 is a cryo pump real gas system using the same dry pump as before as the initial roughing pump, and 207' has the same configuration as 203 for maintaining the mass spectrometry tube 205 in a high vacuum. Mechanical dry (oil free) vacuum exhaust system, 214'
214 is a cryo-vacuum exhaust system for the lock chamber, 21S is a refrigerator, and the refrigerant 217
The wafer 21 is cooled (including compression, cooling, liquefaction, etc.)
3 to room temperature, preferably from 0°C to -100°C (furthermore at -120°C).
00℃). 216 is a loading chamber, and when loading or unloading the wafer 213, the vacuum level or external pressure is adjusted to a predetermined level. 217 is a refrigerant such as N2 gas, He gas, ethylene glycol, liquid N2 or liquid He218
is a rotation stage that accommodates 20 to 30 wafers 213 and moves in parallel while rotating at high speed.

Reference numeral 219 denotes a cooling auxiliary gas sent into the gap between the wafer 213 and the stage 218.

220 is a doped Si wafer stopper for preventing the wafer 213 from flying out, 221 is an ion beam, and 222 is a secondary ion beam.

The details of each part will be further explained below.

FIG. 22 shows an example of a rotating stage and its cooling mechanism. In the figure, 213 is a wafer, 215 is a refrigerator, 2
17 is a refrigerant dedicated to ethylene glycol and its circulator;
218 is a rotation stage; 219 is a cooling auxiliary gas and its introduction path for improving heat transfer between the rotation stage 218 and the wafer 213; 220 is a wafer stopper (made of doped Si); 230- is a cooling gas introduction space; is a ○ ring. With such a cooling mechanism, the temperature of the implantation surface of the wafer can be maintained at a low temperature from room temperature to around 0.degree. C. or lower during large current implantation.

FIG. 23 is another example of a rotation stage and its cooling mechanism. In this example, He(
The stage is cooled to an extremely low temperature by adiabatic expansion of helium (helium), and the stage and wafer are brought into close contact to improve cooling efficiency. In the same figure, 213 is a wafer, 215
is a He compressor, 217 is He and its flow path, 2
18 is a cooling stage; 220 is a doped Si wafer;
The stopper 232 is an adiabatic expansion chamber of He.

FIG. 24 shows yet another example of the rotation stage. This example is a so-called electrostatic check, in which the wafer is attracted to a stage via an insulating sheet.

In the same figure, 213 is a wafer, 218 is a wafer cooling stage, and cooling 1a 41? has i.

220 is a disconnected line S, i is a wafer stopper, and 233 is a last mark on silicone rubber).

FIG. 25 shows details of the post-acceleration tube and injection chamber of the entire apparatus shown in FIG. 19. In the same figure, 20B is a rear-stage accelerator tube, and 209 is a direct-air first sight system consisting of a dry roughing pump and a turbo molecular pump, which improves the direct-airness of the ion path immediately before implantation. Is 212 an ion? It is the master and one of the concubines of the family. 213 is a wafer, 21
4 is a cryo pump vacuum evacuation system. 214' is the cryo-evacuation system of the load-lock chamber, which evacuates the wafer to a certain level of vacuum using a dry roughing pump, and then evacuates the wafer to the same level of vacuum as the main injection chamber using the cryo-pump. It will be installed in a room for 71 people.

2 (6 is the load-lock chamber, where wafers are introduced, especially by roughing and cryo-pumping).

The degree of vacuum is increased from atmospheric pressure to approximately the injection pressure. On the other hand, during wafer plowing 11, 1, dew condensation is prevented by blowing dry heated N2 gas onto the low temperature wafer to heat the entire wafer to 10° C. or higher and then exhausting it into the atmosphere. 218 is a rotating stage.

234 is a shroud for preventing condensation on the wafer surface (
Shroud), 235 is with the heated N2 gas,
or a wafer heating halogen lamp that independently heats the wafer to prevent dew condensation when ejecting the wafer; 236 is an automatic opening/closing door that separates the injection chamber from the load lock chamber; 237 is a door that separates the load lock chamber from the outside (atmosphere); Partitioning automatic opening/closing door, 24
1a to 241f are accelerating electrode groups having a rectangular opening at the center of a disk-shaped single crystal doped Si.

FIG. 26 shows the potential arrangement within the ion implanter.

In the figure, 202 is an ion source, 205 is a mass spectrometer tube, 205' is an analysis magnet, 206 is a beam filter slit electrode, and 206' is an analyzer electrode.
, 212 is an injection chamber, which is connected to ground potential.

221a to 221e are ion beam paths; 221a to 221e are ion beam paths;
1a is the front passage of the analyzer, 221b is the central passage of the analyzer, 221C is the rear passage of the analyzer, 221d is the passage between filters, 221e is the accelerator tube passage, 238 is a high voltage chamber (this potential is called a high voltage terminal or high voltage ground), V is the post-acceleration voltage, vo is the extraction voltage of the ion source (20 to 30 KV), and Vf is the filter voltage for blocking singly charged ions mixed in during multivalent ion implantation. When , ■. Apply a voltage slightly higher than half of the voltage. A voltage of V is applied to 206'.

FIG. 27 shows the potential distribution to the latter stage acceleration electrode group.

In the same figure, E1 to E6 are the potentials of each electrode, and 239 is V
, potential, 240 is a ground potential, 241 a to 241 f are accelerating electrode groups, and 242 a to 242 e are dividing resistors.

FIG. 28 shows the relationship between the wafer and the electron shower. In the figure, 213 is a wafer, which is generally connected to ground potential. 221 is an ion beam, 243 is an electron shower generator plate (same potential as the cathode), 244
is the same grid.

245 is the same cathode, and high-energy electrons (200
~300 eV) reacts with the Ar gas inside the electron shower and releases a large amount of energetic electrons (about 10 eV).

FIG. 29 is a schematic circuit diagram of an electronic shower generator.

In the same figure, V is the cathode (filament) voltage, V
c is a grid voltage, 244 is a grid, and 245 is a cathode (filament).

FIG. 30 shows the relationship between the emission current from the cathode and the grid voltage Va.

is the initial setting value of the emission current.

FIG. 31 is an overall view of the rotation stage. In the figure, the number of rotary stages 218 is the same or slightly larger than that of the rotary stage 218 so that a single lot of wafers, that is, 0 to 25 wafers can be processed at a time. 250 is a pillar part,
251 is a central rotor section.

FIG. 32 shows a state in which a wafer is placed on one of the one-rotation stages, viewed from the main surface (top surface) of the wafer. In the figure, the peripheral edge of the wafer 213 is located outside the base of the rotation stage 218, and the wafer stops 220a to 220
20c. Further, a refrigerant passage (not shown) is provided in the support portion 250.

FIG. 33 shows the relationship between the wafer and the Faraday cup. Faraday cup 252 consists of an ion collection cup (transverse magnetic field material) and an ammeter with one end grounded.

FIG. 34 is an example of an undesired reaction occurring within the ion path. In the figure, A is a residual gas molecule. The example shown here occurs during doubly charged ion implantation of phosphorus (P).

FIG. 35 is a sketch of a slit electrode plate made of doped Si single crystal. In the figure, 253 is an electrode plate, and 254 is a Freeman source rectangular ion.
It is a rectangular aperture that corresponds to the beam. The ion shown earlier
The source extraction electrode, the mass analyzer (mass analysis slit) electrode 206', the beam filter slit electrode 206, the latter-stage accelerating electrode group 241a to 241f, etc. have approximately this shape.

Figure 36 shows the detailed structure of the load lock chamber 216. In the same figure, 212 is the injection chamber, 214' is the cryo-vacuum exhaust system, 236 is the automatic opening/closing door between the load lock chamber and the injection chamber, and 237 is the load lock. There are automatically opening and closing doors between the chamber and the outside, through which wafers are loaded and unloaded.

255 is an opening/closing valve for separating the cryo vacuum evacuation system 214' from the load lock chamber 216, and 256 is a heating N2 supply device 257 for heating the wafer to around 10°C.
258 is an on-off valve for discharging the heated N2 gas from the load-lock chamber 216.

FIGS. 37(a) to 37(c) are schematic diagrams showing the movement of wafers and wafer cassettes in the load lock chamber. In the figure, 260b is a first wafer cassette, 260
a is a second wafer cassette, 213b is a wafer belonging to the first wafer group (loft), and 213a is a wafer belonging to the fifth wafer group.

FIG. 38 is an enlarged schematic sectional view showing details of the ion source and its vicinity. In the figure, 202 is an ion
The housing of the source, 202a is the extraction acceleration electrode (V11
= 2 to 30 KV), 202b is the deceleration electrode (or ground electrode), 202c is the ion source body (arc chamber or ion generation chamber), 203 is the vacuum exhaust system, 204 (vm) is the extraction electrode power source and accelerating voltage, 2
05 is the mass spectrometer tube, 207' is the vacuum exhaust system, vo is the ion extraction voltage (voltage applied to the arc chamber), ■
, is the post-acceleration voltage. Here, ■. is generally 20~
30 KV, Vl is -2 to 30 Kv, and the deceleration pole 202b is the high-voltage ground potential of the high-pressure vessel, that is, the subsequent acceleration potential V□. Note that 202a and 202b are collectively referred to as drawer@
, called a pole or extraction electrode group.

The configuration of each part has been explained above.
The operation will be explained according to FIG.

The ion beam 221 and ion implantation chamber 212 of the ion implantation apparatus shown in FIG.
・Exhaust to around Torr (standby state).

In this state, the wafer to be processed is exchanged.

As shown in FIGS. 36 and 37 (a) to (c), 25 cassettes (referred to as 10 cassettes) are replaced in units of cassettes. FIG. 37(a) shows the wafer 213a belonging to a new lot being introduced into the load lock chamber 216 through the automatic opening/closing door 237 after the loading of the wafer 213b is completed.

After that, as shown in FIG. 37(b), the wafer group 213
Until the ion implantation in b is completed (loading and unloading time = 2 minutes each, implantation processing time = about 5 minutes), the automatic opening/closing doors 236, 237, opening/closing valves 256, 258 are closed, and the opening/closing valve 255 is closed. 5×10 by vacuum evacuation system 214' in the order of dry roughing and cryopump.
It is exhausted to 5 to 5×10 Torr. Wafer group 2
When the ion implantation of wafers 13b is completed, the wafer group 213b is accommodated in the first cassette 260b through the automatic opening/closing door 236. On the other hand, the wafer li 213 a is placed in the injection chamber 21
It is set on a rotation stage 218 in 2. When the setting of the wafer group 213a is completed, the automatic opening/closing door 236 is closed and the opening/closing valve 256 is opened, and a N2 gas flow of 20° C. or higher is supplied from the dry N2 source to the load lock chamber 216.
N2 is supplied to the load lock chamber 216 by being discharged from the on-off valve 258 after reaching normal pressure.
A gas flow is formed, and the temperature of the cooled wafer 213b on the rotation stage 218 is increased to 10° C. or higher.

The heated wafer 213b is discharged to the outside through the automatic opening/closing door 237, as shown in FIG. 37(c).

The wafer 213 set on the rotation stage
～○℃～- in the condition shown in Figure 25 and Figures 31 to 33
Cooled to below 150°C. This allows the temperature of the implantation surface of the wafer to be controlled to about several tens of degrees to -120 degrees Celsius during implantation. As shown in Figure 22, the temperature is 0°C to 30°C.
In case of cooling at 11 degrees C, N is applied to the back side of the wafer 213.
It is effective to introduce a gas such as Z, He, Ar, etc. to improve heat conduction. If the temperature is even lower, the 22nd
In the figure, circulation of nitrogen (liquid) is used, or as in Figure 23, adiabatic expansion of helium is used, similar to a cryo pump.

In addition, when using an electrostatic chuck as shown in FIG. 24, it is necessary to interpose a nystomer (silicone rubber) 233 to insulate the wafer 213 and the rotation stage 218, so the thermal efficiency (cooling efficiency) is The refrigerant circulation mechanism shown in FIGS. 22 and 23 can be used, although it will be slightly lower.

During operation, when the wafer 213 is cooled to a predetermined temperature on the stage 218 which is maintained at a predetermined low temperature, the rotation stage 218 starts rotating five times as shown in FIG.
By performing a reciprocating parallel movement in the direction perpendicular to the rotation axis (period: approximately 10 seconds) while maintaining a rotational speed of 1000 r/pm, the ion beam with a cross section of 6° x 60 nxo uniformly licks the entire surface of the wafer. Perform the injection operation for about 5 minutes. The amount of ion implantation is monitored using the rotation stage 218.
This is done by receiving a beam passing backward through a gap or the like in a Faraday cup 252 as shown in FIG. On the other hand, the supply of coolant to the vicinity of the wafer 213 is as follows:
The cooling is carried out from the defroster 215 via the central rotor section 251 (FIG. 31) and the support section 250. These supplies are
This is also performed while the stage 218 is rotating, thereby keeping the surface temperature of the wafer 213 constant even when a large current is implanted.

Next, the operation of the beam line will be explained.

First, as shown in FIGS. 38 and 26, a predetermined gas or vapor that generates desired ions is supplied little by little to the main body 202c of the ion source 202.
Due to the action of the evacuation systems 203, 207', etc., the extraction acceleration/deceleration electrode group 202a.

The beam line from 202b to the mass spectrometer 205 is maintained at a high vacuum of approximately 5×10 Torr or higher (during ion implantation). Ions generated within the ion source body 202c are accelerated to various energies by the action of the acceleration/deceleration electrode groups 202a, 202b, etc., and fly toward the mass spectrometer 205. The implanted ion species that have passed through the analyzer front path 221a in this way, for example, P.
(adjacent positively charged ions) are deflected while passing through the analyzer central path 221b, and are deflected while passing through the analyzer rear path 221c.
It passes through the opening 254 (FIG. 35) of the mass spectrometry slit electrode 206' provided at the terminal end. The same normal ion species (P
++) is further an inter-filter path (length approximately 20 am) 22
1d and aperture 254 in beam filter slit electrode 206 to block abnormal ion species (e.g. P+).
(Fig. 35) and is set to have the desired ion energy through the post-acceleration tube path 221e (potential difference V).
As shown in FIG. 25, the rotating wafer 2
13.

Next, the operation of the beam filter slit electric current t4206 will be explained based on FIGS. 26, 34, and 38.

For example, considering the case of 10 P+ implants, the P2+ emitted from the ion source 202 will leave the residual gas in the analyzer front path 221a as shown in FIG.
Collision reaction with ion A produces -p+P,A. Of these, P and A are analyzed by the mass spectrometer 205 and do not come out behind the slit electrode 206', but for P, the difference in speed between P2+ and P++' before one reaction is due to the phase difference. As a result, the light passes through the slit electrode 206' regardless of the difference in mass-to-charge ratio (m/e). When these abnormal P ions reach the second stage acceleration tube 208, they are implanted into the wafer 213 in a state where they are only accelerated to an energy considerably lower than the desired energy, resulting in so-called energy contamination.

The beam filter slit electrode 206 is provided for the purpose of removing these abnormal ion species before they reach the second stage acceleration tube 208. The beam filter slit electrode 206 is a doped single crystal Si electrode 1i as shown in FIG.
The normal beam is provided within the beam path so that its main surface is substantially orthogonal to the beam path so that the normal beam exactly coincides with the central aperture 254. The potential (with reference to the voltage ground potential) vt is set to a voltage slightly higher than half of V when P+ is a normal species and P+ (generated by the reaction shown earlier than Pz+) is an abnormal species. . By this,
Fast P? cannot cross this potential mountain, but p'' (due to pz+) is slow, so
Unable to overcome this mountain of potential, the beam
It cannot invade behind the filter slit electrode 206. By doing so, it is possible to implant divalent and even trivalent ions, which often generate abnormal ion species, with high purity.

Such a beam filter slit electrode 206 also prevents energy generated after the mass spectrometer 205 (inter-filter path 221d or acceleration tube path 221e).
It is difficult to completely remove contamination. For example, if a collision reaction like the one shown in FIG. Therefore, in order to eliminate energy contamination caused by these reactions, the beam filter slit electrode 206 and the acceleration tube paths 221d and 22
The degree of vacuum at 1e is 1X10-5T at the time of implantation.
It is effective to connect an exhaust port of a vacuum evacuation system near the path to evacuate (even during implantation) so that the pressure can be maintained at 5×10 Torr or higher, preferably 5×10 Torr or higher. The exhaust system provided for this purpose is the vacuum exhaust system 207, 207' shown in FIG.

Furthermore, together with the beam filter slit electrode, the vacuum exhaust system 207' is connected to the analyzer front passage 22a (
At the time of implantation, the vacuum level of the beam line (Fig. 26) and its vicinity should be set to 1X10 Torr, preferably 5
By maintaining a high vacuum of ×10 Torr or more, the occurrence of undesired reactions itself is reduced and the occurrence of energy contamination is prevented.

Next, based on FIG. 9, FIG. 25, and FIGS. 28 to 30, the charge-up prevention electronic shower generator 210 is
(hereinafter abbreviated as "E-generator") and its monitoring mechanism will be explained.

As shown in FIG. 28, electrons generated by the E-generator 10 in conjunction with the generation of the implantation ion beam 22 fall onto the wafer 213 together with the ion beam 221, thereby preventing charge-up of various parts of the wafer 213. It is supposed to be done. However, although the initial setting value (emissions) of the E-generator 210 is supposed to be kept constant, it may change or stop due to some reason. In such a case, unless the extraction of ions from the ion source 202 is stopped within a very short period of time, it is impossible to prevent the elements on the wafer 213 or the oxide film that is the material of the elements from being destroyed.

Therefore, in the present invention, the electronic shower monitor 211
- Monitor the emission current 8 of the generator 210, and when I3 falls below 90% of the set value 8°,
A power-down signal is sent to the ion source power supply 201 by the action of the microcomputer that constitutes the monitor 211.
transfer the extraction voltage to a predetermined potential (i.e.,
the ion beam 221
Stop the generation of that thing.

Next, we will discuss the specific ion implantation process and this Example 2, which will be described later.
The relationship between this and the description up to this point will be explained.

Although all of the various variations shown in this example are applicable to each of the above-mentioned injection processes, specific examples of particularly favorable combinations will be shown below.

Beam filter slit electrodes are particularly effective in multiply charged ion implantation, but are also effective in other cases as a method of removing unwanted ions.

Cooling the wafer during implantation is effective in all steps, but is particularly effective in promoting amorphization and preventing the formation of a transition layer between the amorphous layer and the normal layer. Therefore, by making the thickness of such a transition layer as thin as possible,
This is effective when it is desired to easily and completely recover defects caused by annealing.

Therefore, it is particularly effective for the ion implantation process for forming the source and drain of each FET, which will be described later, and for variations thereof. In this case, the temperature of the top surface of the wafer during implantation is maintained at -150'C1 or less, preferably 0°C or less, from room temperature. Particularly at concentrations where amorphization is not complete, it is desirable to keep the temperature at -50°C to 100°C or lower.

In addition, when implanting Ge in pre-amorphous implantation and then implanting an impurity that is relatively difficult to become amorphous, such as B+, it is possible to
By performing the primary B+ implantation while holding the wafer at 0'C (furthermore, about -200C), it is possible to almost completely suppress the remaining defects after annealing.

In addition, in each ion implantation process, if the wafer is cooled, the temperature of the 7 nitride after implantation should be 900°C.
It can be carried out at low temperatures of ~800°C.

In addition, when referring to "the surface temperature or upper surface temperature of a wafer (taking Si single crystal as an example)" in Mizuharu IS.

It corresponds to the macroscopic average temperature of a layered region several micrometers from the interface of an oxide film or the like on the top surface of a Si single crystal where defects due to implantation occur.

Next, the ion implanter of this example! An example of a method for manufacturing a semiconductor integrated circuit device using the following will be described. This manufacturing method is based on DRAM (Dynamic Random A).
MO5-FETQs for memory cell selection which constitutes the memory cell of (ccessMe+aory), n-channel MOS-FETQn which constitutes the peripheral circuit, p-channel MOS
This is applied to a method for manufacturing FETQP.

Below, the specific manufacturing method is shown in Figures 5 to 18.
This will be explained using figures (cross-sectional views of main parts shown for each manufacturing process). Note that this DRAM has a capacity of, for example, 16 megabits (Mb).
It has a capacity of 0.5 [μm] with a minimum processing size of 0.5 [μm]! Manufactured according to measurement rules.

FIG. 5 is a cross-sectional view of a main part of a semiconductor substrate (a single crystal wafer with a resistivity of .OMEGA.-am (100)) at an intermediate stage in the manufacturing process of this DRAM.

Memory cell formation region (left side of the figure) of substrate 20 made of p-type silicon single crystal and n-channel MOS of peripheral circuitry
A p-type well region 22 is provided on each main surface of the -FETQn formation region (center of the figure). This P type polygonal region 22 is, for example, 5 x 1012Catoi
After introducing di- or trivalent B ions with an impurity concentration of about 300-400 (KeV) (implantation current 30 μA), the substrate 2
It is formed by heat treating o in an atmosphere at a high temperature of about 1100 to 1300 ('C). An n-type well region 21 is provided on the main surface of the peripheral circuit P-channel MOS-FET (to the right of the p-type region formed).

This n-type well region 21 is, for example, 2×10” (at
2 of P (phosphorus) with an impurity concentration of +mos/d]
Alternatively, after introducing trivalent ions by an ion implantation method with an energy of about 400 to 900 [KeV] (injection current 3, ○μA), the substrate 20 is heat-treated in an atmosphere at a high temperature of about 1100 to 1300 ('C). It is formed by

The main surface of each of the well regions 21 and 22 has a 400
A field insulating film 23 for element isolation having a film thickness of about 600 nm:l is provided. This field insulating film 23 is formed by a selective oxidation method (LOCO3 method).

In the peripheral circuit formation region, a p-type channel stopper region 24 is provided below the field insulating film 23 of the p-type well region 22. The p-type channel stopper region 24 is formed, for example, on the main surface of the p-type well region 22 by 3×
After introducing BF with an impurity concentration of about 10" [atoms/cj] by an ion implantation method (implantation current 3.0 μA) with an energy of about 50 to 70 [K e V],
The substrate 20 is heat-treated at a high temperature of about 1050 to 1150° C. for about 30 to 40 [minutes] in a nitrogen gas atmosphere containing a trace amount of oxygen (approximately 50% or less), and then heated to a temperature of about 30 to 40 minutes by steam oxidation. It is formed by oxidizing for about 50 [minutes]. Through this heat treatment, the p-type nitride region 2
The impurity introduced into the main surface of 2 is stretched and diffused, and p-type channel stopper region 24 is formed by substantially the same manufacturing process as that for forming field insulating film 23.

A p-type channel stopper region 25A and a p-type semiconductor region 25B are provided on the main surface of the memory cell formation region.

P-type channel stopper region 25A is provided under field insulating film 23, and P-type semiconductor region 25B is provided in the active region.

p-type channel stopper region 25A, p-type semiconductor region 25
Each of B is, for example, I X 1013 [atoms
/j] at an impurity concentration of 200 to 300 (K
It is formed by introducing high energy ion implantation (implantation current: 20 μA) such as eV). The P-type channel stopper region 25A is formed by introducing the above-described impurity through the field insulating film 23,
P-type semiconductor region 25B is formed at a deep position in the main surface of p-type well region 22 by an amount corresponding to the film thickness of field insulating film 23.

Each active area in well area 22.21 contains 12
~18 (Gate having a film thickness of about hml!! Edge film 2
6 is provided. This gate insulating film 26 is formed by steam oxidizing the substrate 20 at a high temperature of about 800 to 1000 ('C), for example.

On each of the field insulating film 23 and gate insulating film 26 in the memory cell formation region, MO3 for memory cell selection is provided.
- A gate electrode 27 of FETQs is provided. The gate electrode 27 of MO5-FETQs for memory cell selection is
In the formation region of the 0 peripheral circuit, which also serves as the word line (WL), the gate of the P'''' type sea urchin region 22 is disconnected! #Membrane 26
A gate electrode 27 of an n-channel MO3-FET Qn is provided on top of the n''l-type well region 2.
The single insulating film 26 is provided with a gate electrode 27 of the P-channel MO3-FETQp. These gate insulating films 27 are made of a polysilicon film having a thickness of about 200 to 300 (nm), for example. This polysilicon film is doped with n-type impurities (P or A) to reduce resistance.
s) has been introduced.

To form the gate electrode 27, for example, first a polysilicon film is deposited on the entire surface of the substrate 20 by CVD method, n-type impurities are introduced into this polysilicon film by thermal diffusion method, and then a 5i02 film (not shown) is deposited on the surface of the polysilicon film. is formed by a thermal oxidation method, and then a film of, for example, 250 to 3
Interlayer line JllIII2 having a film thickness of about 50 (nm)
Deposit 8. This interlayer insulating film 28 is formed by a CVD method using, for example, inorganic silane gas and nitrogen oxide gas as source gases. Next, the gate electrode 27 is formed by anisotropically etching the interlayer insulating film 28 and the polysilicon film using a photoresist mask (not shown). Note that the gate electrode 27 is made of a high melting point metal (MO,
T
Si,.

It may be composed of a single layer of WSi, ) film. Further, the gate electrode 27 may be formed of a composite film in which the above-mentioned high melting point metal film or high melting point metal silicide film is deposited on a polysilicon film.

Next, as shown in FIG. 6, using the field insulating film 23 and the interlayer wA edge film 28 (gate electrode 27) as an impurity introduction mask, an n-type impurity 29n is introduced into the main surface of the p-type well region 22. . This n-type impurity 29n is introduced into the gate electrode 27 in a self-aligned manner. The n-type impurity 29n is, for example, I
P (or As) tt with an impurity concentration of about 30 to 50 (KeV) is used and introduced by an ion implantation method (injection current of 20 to 30 μA) with an energy of about 30 to 50 (KeV). Although not shown.

When introducing this n-type impurity 29n, the main surface of the n-type well region 21 is covered with an impurity introduction mask (for example, a photoresist film).

Next, using the field insulating film 23 and the interlayer insulating film 28 (gate electrode @27) as an impurity introduction mask, n-1
A P-type impurity 30p is introduced into the main surface of the well region 21. This p-type impurity 30p is introduced in a self-aligned manner with respect to the gate voltage @27.

The p-type impurity 30p is, for example, IXI○” (atoms
/alf] using an ion implantation method (implantation current: 10 μA) with an energy of about 80 (KeV). Although not shown, when introducing the P-type impurity 30, the main surface of the p-type well region 22 is covered with an impurity introduction mask (
coated with a photoresist film).

Next, as shown in FIG. 7, the gate electrode 27. Sidewall spacers 31 are formed on each sidewall of the interlayer insulating film 28 thereon. The sidewall spacer 31 is made of, for example, a Si film deposited by CVD using inorganic silane gas and nitrogen oxide gas as source gases.
It is formed by performing anisotropic etching such as RIE to a film thickness corresponding to, for example, 130 to 180 nmE (approximately 130 to 180 nmE). The length is approximately 150 (
nm).

Next, in this embodiment, an n-type impurity 32n is introduced into the n-channel MOS-FETQn formation region of the peripheral circuit using the large current type ion implantation device 1.

When introducing this n-type impurity 32n, the sidewall spacer 31 is mainly used as an impurity introduction mask.

Further, the region other than the n-channel 'vl OS-FET Qn formation region is already covered with an impurity introduction mask (photoresist II, not shown).The n-type impurity 32n is
For example, 5 x 10” (atones/csi
) using As (or P) with an impurity concentration of about 70~
The ions are introduced using an ion implantation method with an energy of about 90 (Key) (injection current: 20 μA). At this time, ion implantation is performed for about 10 minutes while rotating the rotating disk 13 of the ion implantation bag electrician at a speed of 11,000 rpm.

Next, as shown in 8th riA, by heat-treating the substrate 1, the above-mentioned n-type impurity 29n and n-type impurity 32 are added.
The n-type and p-type impurities 30p are each stretched and diffused to form the n-type semiconductor region 29 of the memory cell selection MOS/FETQS, the n-type semiconductor region 29 of the n-channel MOS-FETQn of the peripheral circuit, and the n-type semiconductor region 32, p-type semiconductor region 30 of p-channel MO8-FETQp in peripheral circuit
form each of them. The above heat treatment is 1 e.g. 90
20 to 40 minutes at a high temperature of 0 to 1000 ("C)"
Do it to some degree. By forming the n-type semiconductor region 29, the memory cell selection MOS-FET
Qs is completed. Further, by forming the n-type semiconductor region 29 and the n+-type semiconductor region 32, an n-channel MOS-FETQn of the peripheral circuit having an LDD structure is completed. In addition, peripheral circuit (7) P channel MO3-F
ETQpLt, only the p-type semiconductor region 30 forming part of the LDD structure is completed.

Next, an interlayer insulating film 33 is deposited over the entire surface of the substrate 2o. This interlayer insulating film 33 is used as an etching stopper layer when processing the electrode layer of the information storage capacitive element C of the memory cell, which will be described later. MO5- for layer and memory cell selection
The 0 interlayer insulating film 33 formed to electrically isolate the gate electrode 27 (word, 11WL) of the FETQs is formed to increase the film thickness of the sidewall spacer 31 of the p-channel MO3-FETQp. .

The interlayer insulating film 33 is made of, for example, Sin deposited by a CVD method using inorganic silane gas and nitrogen oxide gas as source gases.
It is composed of a film and has a film thickness of about 130 to L80 [nm].

Next, as shown in FIG. 9, the memory cell selection MO8-
The interlayer insulating film 33 on one n-type semiconductor region (the side to which the lower electrode layer of the information storage capacitive element C is connected) 29 of the FETQS is removed to form connection holes 33A and 34, respectively. This connection hole 34 is connected to the side wall spacer 3
1. It is formed in a region defined by each sidewall spacer 33B deposited on the sidewall of the sidewall spacer 31 when the interlayer insulating film 33 is etched.

Next, as shown in FIG. 10, a polysilicon film 35A that will become the lower electrode layer of the information storage capacitor C of the memory cell is deposited on the entire surface of the substrate 20. This polysilicon 1135
A is the connection hole 33A.

34 through each of the n-type semiconductor regions 29.
Connect to. This polysilicon film 35-A is deposited by the CVD method and has a film thickness of about 150 to 250 nm.This polysilicon film 35-A is doped with n-type impurities to reduce the resistance value after deposition. 1. For example, P is introduced by a thermal diffusion method. This n-type impurity is introduced into the connection hole 34.
A large amount of impurity is diffused into the n-type semiconductor region 29 through the channel, and the impurity concentration is introduced at a low concentration so as not to diffuse into the channel forming region side of the memory cell selection M○5-FETQS.

Next, as shown in 1113g, a polysilicon film 35B is further deposited on the polysilicon film 35A.

This upper layer polysilicon film 35B is deposited by the CVD method and has a film thickness of about 250 to 350 nm.The upper layer polysilicon film 35B is doped with n-type impurities to reduce the resistance value after deposition. For example, P is introduced by a thermal diffusion method.This n-type impurity is introduced at a high impurity concentration in order to improve the amount of charge storage in the information storage capacitive element C.

Next, as shown in FIG. 12, the two-layered polysilicon films 35A and 35B are processed into a predetermined shape using photolithography technology and anisotropic etching technology, and the lower layer of the information storage capacitive element C is etched. An electrode layer 35 is formed.

Next, as shown in FIG. 13, a dielectric film 36 is deposited on the entire surface of the substrate 20. The 7m'4 body membrane 36 is made of, for example, Si.
A two-layer structure is formed by sequentially laminating a 3N4 film 36A and a SiO2 film 36B. The Si, N, and film 36A are deposited by, for example, a CVD method, and have a thickness of about 5 to 7 nm. When the Si3N film 36A is deposited on the lower electrode layer 35 (polysilicon film) at a normal production level,
Since a very small amount of oxygen is involved, Si, N, and film 3
6 and the lower electrode layer 35 is a natural oxide film (not shown).
A Sin2 film) is formed.

The Si○2 film 36B on the upper layer of the dielectric film 36 is formed by applying a high pressure oxidation method to the lower Si, N, film 36A.
It has a film thickness of about 3 (nml).

Next, a polysilicon film (not shown) is deposited on the entire surface of the substrate 20. The polysilicon film was deposited by CVD method, and
The polysilicon film has a film thickness of about 0 to 120 nm (nm:l). After deposition, an n-type impurity such as P, which reduces the resistance value, is introduced by thermal diffusion into the polysilicon film. An etching mask (photoresist film) (not shown) is applied on the polysilicon film over the entire memory cell formation region except for the connection region between one n-type semiconductor region 29 of the selection M○5-FETQs and a complementary data line to be described later. form.

Thereafter, as shown in FIG. 14, the polysilicon film and the dielectric film 36 are sequentially anisotropically etched using the etching mask.

The upper electrode layer 37 of the information storage capacitive element C is formed. By forming this upper electrode layer 37, a so-called stacked structure information storage capacitor C is almost completed, and the DRA
M memory cells M are completed.

After completing this memory cell M, the etching mask is removed.

Next, as shown in FIG. 15, the substrate 20 is subjected to thermal oxidation treatment to form an insulating film (SiO, film) 38 on the surface of the upper electrode layer 37 of the information storage capacitive element C. This insulating film 38 is formed in a step of oxidizing the etching residue (polysilicon film) remaining on the underlying surface (the surface of the interlayer insulating film 33) when the upper M electrode layer 37 is patterned.

Next, in the formation region of the P-channel MOS-FET Qp of the peripheral circuit, the interlayer insulating film 33 formed in the above process is subjected to anisotropic etching.

As shown in FIG. 16, the side wall spacer 3
A side wall spacer 33C is formed on the side wall of 1.

This sidewall spacer 33C is a p-channel MO
It is formed in a self-aligned manner along the gate electrode 27 of the S-FETQp. Sidewall spacer 33C is sidewall spacer 3 of p-channel MOS-FETQp.
1 is formed so that the dimension in the gate length direction is increased.

The total dimension of the sidewall spacers 31.33C in the gate length direction is about 200 (nm).

Next, # (not shown) is applied to the entire surface of the substrate 20! Deposit the lamina. This insulating film is mainly used as a contamination prevention film when introducing impurities. This insulating film is composed of a 5 in 2 film deposited by CVD using, for example, inorganic silane gas and nitrogen oxide gas as source gases, and has a thin film thickness of about 10 (nm).

Next, in this embodiment, using the large current type ion implantation apparatus 1, as shown in FIG.
A P-type impurity 39p is introduced into the formation region of the OS-FETQp. When introducing the p-type impurity 39p, the sidewall spacers 31 and 33C are mainly used as impurity introduction masks. Also, p-channel MOS-FETQp
The regions other than the formation region are covered with an impurity introduction mask (photoresist film), not shown. The above p-type impurity 3
9p is, for example, 3 x 10'' (ato s/d
) using BP (or B) with an impurity concentration of about

The ions are introduced by ion implantation with an energy of about 80 (Key) (injection current: 20 mA). At that time, the ion implanter 1
Ion implantation was carried out for about 10 minutes while rotating the rotating disk 3 at a speed of 1100 Orp.

Thereafter, as shown in FIG. 18, the substrate 2o is heat-treated to stretch and diffuse the p-type impurity 39p, thereby forming a P-type semiconductor region 39. The above heat treatment is performed at a high temperature of, for example, 900 to 1000 [℃] for 20 minutes.
Do this for about 40 minutes. By forming the P+ type semiconductor region 39, the p
Channel MO5-FETQp is completed.

Note that the 39P ion implantation process may be performed as follows. In this case, defects etc. can be completely recovered even with heat treatment at 900° C. to 800° C., which is lower than the above annealing. That is, first, 5×101014 (at.

/J] and an energy of 10 to 20 KeV in the same manner as the above BF, and after making the implanted area sufficiently amorphous, B (upper value boron ions) was implanted at 2 x 10
” (atoms/al) impurity concentration.

Implant with an energy of 2-5 KeV and post-process as before. This kind of advance input of Gee etc.
This will be called amorphization ion implantation. Furthermore, B+ can be directly produced without any such amorphous treatment.
When implanting (monovalent boron ions), the injection current is 2
0 mA, impurity concentration 2 x 10'' (atom
s/cj), the energy is 2 to 5 KeV, and the wafer implantation temperature at the time of implantation is cooled to around -100° C. to facilitate amorphization, and the same procedure as in BF2 may be performed.

As described above, in the DRAM manufacturing method of this embodiment, the step of ion-implanting impurity at a high concentration of about 10'' (atoms/aj) into the substrate 20, that is, the step of ion-implanting impurities at a high concentration of about 10'' (atoms/aj), that is, the n@ type semiconductor of the n-channel MO5-FET Qp in the peripheral circuit. Area 32
By using the ion implantation bag W1 in the step of forming the P-shaped semiconductor region 39 of the p-channel M○S-FETQp of the peripheral circuit, contamination of the substrate 20 by sputtering of the ion implantation device 1 can be reduced. I can do it. As a result, defects induced in the substrate 20 during ion implantation can be efficiently recovered by subsequent low-temperature (approximately 900 to 1000 degrees Celsius) heat treatment. prevent deterioration of
As long as the manufacturing yield of DRAM can be improved, the invention made by the present inventor has been specifically explained based on the actual flow, but the present invention is not limited to the above embodiments, and the gist thereof will be explained below. It goes without saying that various changes can be made without departing from the above.

In the above embodiment, the substrate 20 has a thickness of 10" [:atoS/
Although the case where the present invention is applied to a large current type ion implantation device used in the process of introducing impurities at a high concentration of about Like, 10
It can also be applied to a medium current type ion implantation device used in a process of introducing impurities with a medium concentration of about 12 to 1013 [:atoms/cxi].

Among the inventions disclosed in this example, the effects obtained by typical ones are as follows.

By using an ion implanter structure in which at least the surface of the member provided on the ion beam path is made of high-purity silicon, it is possible to effectively prevent contamination of the substrate by sputtering from the ion implanter, and to prevent the substrate from being contaminated during ion implantation. Since the induced defects can be efficiently recovered by subsequent heat treatment, deterioration of the electrical characteristics of the element due to the defects can be prevented and the manufacturing yield of semiconductor integrated circuit devices can be improved.

A brief explanation of the effects obtained by one typical invention among the inventions disclosed in this example is as follows.

(1) In the ion implantation apparatus, (1) Coolant cooled by a refrigerator is passed through the contact area on the back surface of the wafer to cool the contact area. Furthermore, gas is introduced between the wafer and the cooling surface to improve heat conduction between the wafer and the cooling section. ■As a cooling method for the contact area on the back of the wafer, the principle of a cryopump is applied and the cooling unit is used as a cold head. In this case as well, gas is introduced between the wafer and the cooling surface to improve thermal conductivity.

As a result, the wafer temperature during ion implantation can be adjusted from 0°C to -
Since it can be cooled to 100° C., defects generated during implantation can be reduced and crystal defects can be prevented.

The temperature during implantation of the wafer may be further increased to -100°C as necessary.
The temperature may be lowered to about -250°C or lower.

(2) In the ion implanter, (1) After implantation in vacuum, heat the wafer using an infrared lamp to a temperature that does not cause dew condensation. ■After implantation, the wafer is transferred from the implantation chamber to the preliminary vacuum chamber and gradually returned to atmospheric pressure using dry heated nitrogen. Thereby, dew condensation can be prevented when the wafer after implantation is taken out from the ion implantation apparatus into atmospheric pressure.

(3) In the ion implanter, the electron shower (electron emission current) monitor is electrically linked to the ion source or the extraction T-type power supply, so that even if the electron shower generator malfunctions during implantation, there will be no malfunction. At the same time, it blocks the ion beam. This can prevent electrostatic damage to devices on the wafer surface.

(4) Eliminating the mechanical wafer stopper in the ion implanter and fixing the wafer with an electrostatic chuck to prevent the ion source from hitting anything other than the wafer. ■Improve the purity of the mechanical stopper (more than 3N) and improve the shape of the surface that the beam hits to prevent sputtered materials from flying around. This prevents the beam from hitting the wafer stopper that holds the wafer and sputtering aluminum or the impurities contained in it, thereby preventing contamination of the wafer by the secondary ion beam. I can do it.

(5) In the ion implanter, (1) a beam filter is installed at the exit of the mass spectrometry tube to remove contaminant ions generated between the ion source and the mass spectrometry tube exit; ■A high vacuum pump is installed between the mass spectrometry tube and the second stage acceleration tube, and the degree of vacuum inside the second stage acceleration tube is adjusted from the mass spectrometry tube outlet to the second stage acceleration tube to Distance at acceleration exit]

(2) High vacuum pumps are installed at two locations between the mass spectrometry tube outlet and the post-acceleration tube and on the exit side of the post-acceleration tube to obtain the same degree of vacuum as in (2) above. Thereby, energy contamination during implantation of multiply charged ions or molecular ions can be prevented.

(6) To prevent introduction of contamination due to sputtering from each electrode in the ion path.

Each electrode, i.e., the extraction electrode of an ion source, the analysis slit of a mass spectrometer, the beam, the filter, the slit, the post-acceleration electrode, etc., or the surface of such a part may be sputtered and contaminated. Cover it with conductive material to prevent it from working. The entire electrode plate may be made of such material (high purity).

That is, when the wafer to be processed is Si, appropriately doped Si may be used in that portion.

For example, from a Si ingot (high-purity doped Si single crystal) with a resistivity of about 10Ω, which is grown by a pulling method by adding an appropriate single or several kinds of impurities to a 99.9999999% Si material, The cut out disk is processed and used as the electrode.

This makes it possible to form an ion path without charge-up and contamination.

(7) Generally, in ion implantation, the beam is further deflected by about 30' after mass analysis in order to improve the purity of the ions. However, in the present invention, in order to efficiently implant a high-purity ion beam, the beam path is made as short as possible without effectively deflecting the entire beam after analysis (excluding the focusing lens within the beam itself). The beam is then made incident on the wafer to be processed.

Furthermore, in response to the miniaturization of devices, the beam is arranged to be incident on the surface of the wafer to be processed in order to minimize shadow effects.

Note that in the present invention, since a Si electrode is used, carbon, oxygen, alkali metals, etc. can be easily removed compared to quartz or the like. However, this does not negate or eliminate the effectiveness of using quartz or the like as part of the ion beam path.

〔Effect of the invention〕

A brief explanation of typical effects obtained by the invention disclosed in this application is as follows.

By using an ion implanter structure in which at least the surface of a member provided on the path of the ion beam is coated with high-purity silicon, contamination of the substrate by sputtering from the ion implanter can be effectively prevented.

Defects induced in the substrate during ion implantation can be efficiently recovered by subsequent heat treatment5, thereby preventing deterioration of the electrical characteristics of the device due to these defects and improving the manufacturing yield of semiconductor integrated circuit devices. I can do it.

[Brief explanation of drawings]

1 is a cross-sectional view taken along the line I-I of the ion implantation device according to the first embodiment of the present invention; FIG. 2 is a perspective view showing a part of the ion implantation device; FIG. FIG. 4 is a cross-sectional view showing a part of an ion implantation device which is another example of the first embodiment of the present invention, and FIG. 4 is a schematic front view of this ion implantation device. 5 to 18 are sectional views of essential parts of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device using this ion implantation apparatus (Embodiment 2). FIG. 19 is an overall view of an ion implantation apparatus according to a second embodiment of the present invention, FIG. 20 is a wafer holding section of this ion implantation apparatus, (A) is a front view, (B) is a side view, The 21st @ is a separate wafer holding part of this ion implantation apparatus, (A) is a diagram showing a state in which a wafer is held without a stopper by an electrostatic chuck method, and (B) is a wafer stopper with an improved shape. , (C) is a diagram showing a separate stopper, FIG. 22 is a sectional view schematically showing the chuck part of the rotation stage of this ion implantation device, and FIG. 23 is a diagram of the rotation stage of this ion implantation device. FIG. FIG. 24 is a cross-sectional view schematically showing still another example of the rotation stage of this ion implantation apparatus. FIG. 25 is a cross-sectional view schematically showing the detailed structure of the implantation chamber and its vicinity of this ion implantation apparatus. FIG. 26 is a cross-sectional view schematically showing the potential relationship of each part of the ion implantation device, FIG. 27 is a circuit diagram of the latter-stage accelerating electrode group of this ion implantation device, and FIG. 28 is an electronic diagram of this ion implantation device. A sectional view schematically showing a part of the shower. 29 is a circuit diagram of a part of the electronic shower shown in FIG. 28, FIG. 30 is a graph showing the relationship between the emission current and gate voltage of the electronic shower shown in FIG. 28, and FIG. 32 is an enlarged front view of the wafer placement section at the tip of the rotation stage shown in FIG. 31, and FIG. FIG. 3 is a diagram showing desired interactions or reactions between ions and between ions and molecules at the rotary stage shown in FIG. Figure 35 shows a drawer provided along the ion beam path of this ion implanter! A sketch of each main part such as poles, deceleration electrodes, analyzer slits, beam filters, and post-acceleration electrode group. Figure 36 is a cross-sectional diagram schematically showing details of the load-lock chamber and dew condensation prevention device of this ion implanter. 37A to 37C are diagrams schematically showing the wafer processing situation in the load lock chamber shown in FIG. 36. FIG. 38 is a cross-sectional view showing the detailed structure of the ion source and its vicinity of this ion implantation apparatus, as well as the potential relationship of each part. 1... Ion implanter, 2... Ion source, 3.3a
. 3b... Extracting electrode, 4... Extracting slit, 5...
... Mass spectrometry system, 6 ... Analyzer, 7 ... Analysis slit, 8 ... Liner, 9 ... Accelerator tube, 10 ...
Accelerating electrode, 11--Converging lens, 12--Injection chamber, 13--Rotating disk, 4--Beam stopper, 15--Substrate holder, 16--Core material, 17-
... Thin film, 18... Slit, 2o... Semiconductor substrate (wafer), 2 upper... n''', shaped well region, 22.
...P-type well region, 23...field insulating film,
24,2SA...p-type channel stopper region, 25B
, 30... P-type semiconductor region, 26... gate insulating film, 27 gate electrode (word line WL). 28.33... Interlayer insulating film, 29... N-type semiconductor region. 29n, 32n-n type impurity, 30p, 39P-...p
type impurity + 31.33B, 33C...side wall spacer, 32...n+ type semiconductor region, 33A. 34... Connection hole, 35... Lower electrode layer, 35A, 3
5B...Polysilicon film, 36...Dielectric film, 36
A...SiN, film, 36B...Sin, film, 37.
...Upper electrode layer, 38...Insulating film, 39...P'''
shaped semiconductor region, ■. ...Ion beam.

Claims (1)

[Scope of Claims] 1. An ion implantation device characterized in that at least the surface of a member provided on the path of an ion beam is made of high-purity silicon. 2. The ion implantation apparatus according to claim 1, wherein the silicon has a purity of 99.9999% or more. 3. The ion implantation apparatus according to claim 1, wherein the member is made of a conductive material and has a thin film of high purity silicon formed on its surface. 4. The ion implantation apparatus according to claim 1, wherein the member is made of high-purity silicon, and its resistance value is reduced by irradiation with neutrons. 5. The ion implantation apparatus according to claim 1, wherein at least a portion of the member that is irradiated with the ion beam is made of high-purity silicon. 6. A method for manufacturing a semiconductor integrated circuit device, characterized in that a semiconductor region having a predetermined impurity concentration is formed by introducing impurities into a semiconductor substrate using the ion implantation apparatus according to claim 1. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the semiconductor regions are a source region and a drain region of a MOS/FET. 8. A method for manufacturing a semiconductor integrated circuit device, comprising forming a semiconductor region having a predetermined impurity concentration by introducing impurities into a semiconductor substrate using the ion implantation apparatus according to claim 2. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein the semiconductor regions are a source region and a drain region of a MOS/FET. 10. A method for manufacturing a semiconductor integrated circuit device, comprising forming a semiconductor region having a predetermined impurity concentration by introducing impurities into a semiconductor substrate using the ion implantation apparatus according to claim 3. 11. The method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein the semiconductor region is a source region and a drain region of a MOS/FET. 12. A method for manufacturing a semiconductor integrated circuit device, comprising forming a semiconductor region having a predetermined impurity concentration by introducing impurities into a semiconductor substrate using the ion implantation apparatus according to claim 4. 13. The method of manufacturing a semiconductor integrated circuit device according to claim 12, wherein the semiconductor region is a source region and a drain region of a MOS/FET. 14. A method for manufacturing a semiconductor integrated circuit device, comprising forming a semiconductor region having a predetermined impurity concentration by introducing impurities into a semiconductor substrate using the ion implantation apparatus according to claim 5. 15. The method of manufacturing a semiconductor integrated circuit device according to claim 14, wherein the semiconductor region is a source region and a drain region of a MOS/FET. 16. Ion implantation device consisting of the following configuration: (a) Ion generation unit that generates ions for ion implantation; (b) Extracts the generated ions and accelerates or decelerates them to apply a predetermined energy to a constant level. (c) a plate-shaped extraction electrode set to a predetermined potential and having a first slit in the center for the ions to pass through, which is provided near the ion generating section in order to cause the ions to travel in the direction; (c) the slit; Mass spectrometry means for selecting a desired ion from the ions by causing the ions traveling through to enter a predetermined magnetic field; (d) passing through all or part of the mass spectrometry means; An analysis slit plate set at a desired potential to selectively allow desired ions from among the ions passed through a second slit provided in the center; (e) ions passed through the second slit; (f) A post-acceleration electrode that has a third slit in its center for the ions to pass through and is set at a predetermined potential in order to impart the desired implantation energy to the ion; (f) pass through the third slit; (g) an implantation chamber for accommodating a plurality of wafers to be processed into which ions are to be implanted; A wafer holding means that holds the wafer facing the ion beam and rotates at high speed; and a wafer holding means that holds the wafer facing the ion beam and rotates at high speed. The part where sputtering occurs is made of high purity Si. 17. The ion bombardment according to claim 16, wherein the ion beam that has passed through the third slit of the latter acceleration electrode is then directly incident on the wafer to be processed without being deflected as a substantially entire beam. Including device. 18. At least a part of the plate-shaped electrode, at least a part of which is made of high-purity Si, is made conductive so that no charge or build-up occurs in the plate-shaped electrode during ion implantation. Ion implantation device. 19. The ion implantation apparatus according to claim 18, wherein the ion beam passing through the third slit is arranged so as to be incident substantially perpendicularly to the implantation surface of the wafer. 20. The ion implantation apparatus according to claim 19, wherein the maximum intensity of the ion beam is 10 mA or more. 21. The ion implantation apparatus according to claim 20, wherein the ion beam path after the extraction electrode can be maintained at a high vacuum of 1×10^-^5 Torr or more during the ion implantation operation. 22. The ion implantation apparatus according to claim 18, wherein the at least partially conductive plate-shaped electrode is made of a high-purity Si single crystal doped to provide conductivity. 23. The ion implantation apparatus according to claim 21, wherein the contact surface of the wafer holding means with the wafer can be cooled to at least −20° C. or lower during ion implantation. 24. A semiconductor integrated circuit device, wherein the wafer holding means of the ion implantation apparatus according to claim 16 holds at least one wafer whose surface or a layer near its surface is made of Si, and implants desired ions while rotating the wafer. Production method. 25. A semiconductor integrated circuit device in which the wafer holding means of the ion implantation apparatus according to claim 17 holds at least one wafer whose surface or a layer near its surface is made of Si, and implants desired ions while rotating the wafer. manufacturing method. 26. A semiconductor integrated circuit device in which the wafer holding means of the ion implantation apparatus according to claim 18 holds at least one wafer whose surface or a layer near the surface is made of Si and implants desired ions while rotating the wafer. manufacturing method. 27. A method for manufacturing a semiconductor integrated circuit device, wherein the wafer holding means of the ion implantation apparatus according to claim 19 holds at least one wafer whose layer near the surface is made of Si, and implants desired ions while rotating the wafer. . 28. At least one wafer whose surface or a layer near the surface is made of Si is held in the wafer holding means of the ion implantation apparatus according to claim 20, and desired ions are applied at a current value of 10 mA or more while rotating the wafer. A method for manufacturing a semiconductor integrated circuit device using injection. 29. The wafer holding means of the ion implantation apparatus according to claim 21 holds at least one wafer whose surface or a layer near the surface is made of Si, and while rotating the wafer, the path of the ion beam after the extraction electrode is maintained. A method for manufacturing a semiconductor integrated circuit device, in which desired ions are implanted while maintaining a high vacuum of 1×10^-^5 Torr or more during an ion implantation operation. 30. A semiconductor integrated circuit device in which the wafer holding means of the ion implantation apparatus according to claim 22 holds at least one wafer whose surface or a layer near its surface is made of Si, and implants desired ions while rotating the wafer. manufacturing method. 31. The wafer holding means of the ion implantation apparatus according to claim 23 holds at least one wafer whose surface or a layer near the surface is made of Si, and while rotating, the wafer on the wafer holding means is ionized. A method for manufacturing a semiconductor integrated circuit device, in which desired ions are implanted while being cooled to at least −20° C. or lower during implantation.