JPH0337304B2 - - Google Patents

Info

Publication number
JPH0337304B2
JPH0337304B2 JP60241158A JP24115885A JPH0337304B2 JP H0337304 B2 JPH0337304 B2 JP H0337304B2 JP 60241158 A JP60241158 A JP 60241158A JP 24115885 A JP24115885 A JP 24115885A JP H0337304 B2 JPH0337304 B2 JP H0337304B2
Authority
JP
Japan
Prior art keywords
wiring board
multilayer wiring
integrated circuit
hybrid integrated
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60241158A
Other languages
Japanese (ja)
Other versions
JPS62101052A (en
Inventor
Yoshitaka Fukuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP60241158A priority Critical patent/JPS62101052A/en
Publication of JPS62101052A publication Critical patent/JPS62101052A/en
Publication of JPH0337304B2 publication Critical patent/JPH0337304B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】 ［発明の技術分野］ 本発明の混成集積回路装置の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a hybrid integrated circuit device.

［発明の技術的背景とその問題点］ 従来から混成集積回路装置の製造方法として、
第３図の工程図に示す方法が知られている。[Technical background of the invention and its problems] Conventionally, as a method of manufacturing a hybrid integrated circuit device,
A method shown in the process diagram of FIG. 3 is known.

この方法では、アルミナ等のセラミツクス多層
配線基板を形成する第１の工程と、この多層配線
基板上のシールリングパターン（気密封止用の金
属製キヤツプを装着するための導体パターン）上
にフラツクスを用いて予備半田し洗浄する第２の
工程と、チツプ部品を多層配線基板の所定位置に
接着剤によりマウントし、ボンデイングする第３
の工程と、電気的機能検査を行う第４の工程と、
第２の工程で形成された予備半田上に金属製キヤ
ツプを装着しリフローする第５の工程と、前記金
属製キヤツプに設けられたガス穴を不活性雰囲気
中で半田で塞ぎ、気密封止する第６の工程とを順
次たどることにより混成集積回路が製造されてい
た。 This method involves the first step of forming a ceramic multilayer wiring board made of alumina, etc., and applying flux on the seal ring pattern (conductor pattern for attaching a metal cap for airtight sealing) on this multilayer wiring board. The second step is to pre-solder and clean the chip using a multi-layer wiring board, and the third step is to mount the chip components in a predetermined position on the multilayer wiring board using an adhesive and bond them.
a fourth step of performing an electrical function test;
A fifth step of attaching a metal cap onto the preliminary solder formed in the second step and reflowing it, and closing the gas hole provided in the metal cap with solder in an inert atmosphere to seal it airtight. A hybrid integrated circuit has been manufactured by sequentially following the sixth step.

ところでこの方法では、チツプ部品をマウント
する際に使用する接着剤を硬化するため、多層配
線基板を加熱する必要がある。例えばエポキシ系
接着剤では150〜160℃で１〜３時間の加熱が必要
である。またチツプ部品と多層配線基板との電気
的接続を形成するためのワイヤーボンデイングを
するにも基板を120〜150℃に加熱する必要があ
る。さらに電気的機能検査の工程でも混成集積回
路装置の消費電力が大きいものである場合には発
熱が生じる。 However, in this method, it is necessary to heat the multilayer wiring board in order to cure the adhesive used when mounting the chip components. For example, epoxy adhesives require heating at 150 to 160°C for 1 to 3 hours. Furthermore, it is necessary to heat the board to 120 to 150°C in order to perform wire bonding to form electrical connections between chip components and the multilayer wiring board. Furthermore, even in the process of electrical function testing, heat is generated if the hybrid integrated circuit device consumes a large amount of power.

このように従来の方法では、加熱や発熱によつ
て基板の温度がかなり上昇し、そのため予備半田
層が酸化されて気密封止不良をまねき、歩留りの
低下をきたしていた。また高温ではシールリング
パターンと半田とが拡散反応をおこすため接合部
分の強度が不十分となつて混成集積回路装置の信
頼性が低下するという問題があつた。 As described above, in the conventional method, the temperature of the substrate rises considerably due to heating and heat generation, and as a result, the preliminary solder layer is oxidized, leading to poor hermetic sealing and lowering the yield. Furthermore, at high temperatures, a diffusion reaction occurs between the seal ring pattern and the solder, resulting in insufficient strength of the joint, resulting in a problem in that the reliability of the hybrid integrated circuit device decreases.

［発明の目的］ 本発明はこのような問題を解消するためなされ
たもので、気密封止不良が生じることがなく、信
頼性の高い混成集積回路装置を歩留りよく製造す
る方法を提供することを目的とする。[Object of the Invention] The present invention has been made to solve these problems, and an object of the present invention is to provide a method for manufacturing a highly reliable hybrid integrated circuit device with a high yield without causing hermetic sealing failure. purpose.

［発明の概要］ すなわち本発明の混成集積回路装置の製造方法
は、多層配線基板上にチツプ部品をマウント、ボ
ンデイングし、電気的機能検査後にチツプ部品全
体を気密封止して混成集積回路装置を製造するに
あたり、前記チツプ部品のマウント、ボンデイン
グ工程および電気的機能検査の工程終了後に気密
封止のための半田層を多層配線基板上に形成し、
次いで、この半田層上に金属製キヤツプをかぶせ
て半田リフローし、金属製キヤツプを基板上に固
定して気密封止することを特徴とする。[Summary of the Invention] That is, the method for manufacturing a hybrid integrated circuit device of the present invention involves mounting and bonding chip components on a multilayer wiring board, and after an electrical function test, hermetically sealing the entire chip component to manufacture the hybrid integrated circuit device. During manufacturing, a solder layer for hermetic sealing is formed on the multilayer wiring board after the mounting of the chip component, the bonding process, and the electrical function testing process are completed,
Next, a metal cap is placed over the solder layer, solder reflow is performed, and the metal cap is fixed onto the substrate for airtight sealing.

［発明の実施例］ 次に本発明の実施例について図面を用いて説明
する。[Embodiments of the Invention] Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明方法の一実施例を示す工程図、
第２図は本発明方法により製造された混成集積回
路装置の断面図である。 FIG. 1 is a process diagram showing an embodiment of the method of the present invention;
FIG. 2 is a sectional view of a hybrid integrated circuit device manufactured by the method of the present invention.

この実施例では、まず多層配線基板１を形成し
（第１の工程）、この多層配線基板１上のダイボン
デイングパツド２にエポキシ系接着剤３を介して
ICチツプ等のチツプ部品４をマウントするとと
もにチツプ部品４と多層配線基板１上のワイヤー
ボンデイングパツド５とをAuやAl線等のワイヤ
６によりボンデイングする（第２の工程）。 In this embodiment, a multilayer wiring board 1 is first formed (first step), and an epoxy adhesive 3 is applied to a die bonding pad 2 on the multilayer wiring board 1.
A chip component 4 such as an IC chip is mounted, and the chip component 4 and the wire bonding pad 5 on the multilayer wiring board 1 are bonded using a wire 6 such as Au or Al wire (second step).

次いで電気的機能検査を行い（第３の工程）、
その後に多層配線基板１にメタライズ形成された
シールリング７（金属製キヤツプ取付け用の導体
パターン）の上にSn／Pb（63／67）の共晶半田が
設けられる（第４の工程）。次にこの半田層８上
に金属製キヤツプ９をかぶせ、半田リフローして
金属製キヤツプ９を多層配線基板１上に固定し
（第５の工程）、次いで金属製キヤツプ９に設けら
れたガス穴１０を窒素ガスあるいはHeガス等の
不活性雰囲気中でフラツクスレス半田１１で塞
ぎ、気密封止する（第６の工程）。なお図中符号
１２はコンデンサーあるいはレジスター等の受動
チツプ部品である。 Next, conduct an electrical function test (third step),
Thereafter, Sn/Pb (63/67) eutectic solder is provided on the seal ring 7 (conductor pattern for attaching a metal cap) metallized on the multilayer wiring board 1 (fourth step). Next, a metal cap 9 is placed on the solder layer 8, and the metal cap 9 is fixed on the multilayer wiring board 1 by solder reflow (fifth step). 10 is closed with fluxless solder 11 in an inert atmosphere such as nitrogen gas or He gas, and hermetically sealed (sixth step). Note that the reference numeral 12 in the figure is a passive chip component such as a capacitor or a resistor.

このようにして製造した混成集積回路装置は、
従来の半田層を、チツプ部品をマウントする前に
形成し製造した混成集積回路装置に比べて熱履歴
が少ないので半田の酸化や拡散がなく機密性に優
れたものとなる。 The hybrid integrated circuit device manufactured in this way is
Compared to conventional hybrid integrated circuit devices in which a solder layer is formed before chip components are mounted, there is less heat history, so there is no solder oxidation or diffusion, resulting in excellent airtightness.

［発明の効果］ 以上説明したように本発明方法によれば、製造
過程において気密封止用の半田層が酸化すること
がないので、気密封止不良が発生せず、歩留りが
向上する。また多層配線基板上の導体パターンで
あるシールリングと半田との拡散も生じないの
で、混成集積回路装置の信頼性が向上し、動作寿
命が伸びるという利点がある。[Effects of the Invention] As explained above, according to the method of the present invention, the solder layer for hermetic sealing is not oxidized during the manufacturing process, so no hermetic sealing failure occurs and the yield is improved. Further, since the solder does not diffuse into the seal ring, which is a conductor pattern on the multilayer wiring board, there is an advantage that the reliability of the hybrid integrated circuit device is improved and the operating life is extended.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明方法の一実施例を示す工程図、
第２図は本発明方法により製造された混成集積回
路装置の断面図、第３図は従来方法を示す工程図
である。 １……多層配線基板、３……接着剤、４……チ
ツプ部品、７……シールリング、８……半田、９
……金属製キヤツプ。 FIG. 1 is a process diagram showing an embodiment of the method of the present invention;
FIG. 2 is a sectional view of a hybrid integrated circuit device manufactured by the method of the present invention, and FIG. 3 is a process diagram showing a conventional method. 1... Multilayer wiring board, 3... Adhesive, 4... Chip parts, 7... Seal ring, 8... Solder, 9
...Metal cap.

Claims (1)

【特許請求の範囲】[Claims] １ 多層配線基板上にチツプ部品をマウント、ボ
ンデイングし、電気的機能検査後にチツプ部品全
体を気密封止して混成集積回路装置を製造するに
あたり、前記チツプ部品のマウント、ボンデイン
グ工程および電気的機能検査の工程終了後に気密
封止のための半田層を多層配線基板上に形成し、
次いで、この半田層上に金属製キヤツプをかぶせ
て半田リフローし、金属製キヤツプを基板上に固
定して気密封止することを特徴とする混成集積回
路装置の製造方法。1. When manufacturing a hybrid integrated circuit device by mounting and bonding chip components on a multilayer wiring board and hermetically sealing the entire chip component after an electrical function test, the mounting, bonding process and electrical function test of the chip component are carried out. After completing the process, a solder layer is formed on the multilayer wiring board for airtight sealing.
A method for manufacturing a hybrid integrated circuit device, comprising: then covering the solder layer with a metal cap, performing solder reflow, and fixing the metal cap onto the substrate for airtight sealing.
JP60241158A 1985-10-28 1985-10-28 Manufacture of hybrid integrated circuit device Granted JPS62101052A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60241158A JPS62101052A (en) 1985-10-28 1985-10-28 Manufacture of hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60241158A JPS62101052A (en) 1985-10-28 1985-10-28 Manufacture of hybrid integrated circuit device

Publications (2)

Publication Number Publication Date
JPS62101052A JPS62101052A (en) 1987-05-11
JPH0337304B2 true JPH0337304B2 (en) 1991-06-05

Family

ID=17070123

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60241158A Granted JPS62101052A (en) 1985-10-28 1985-10-28 Manufacture of hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS62101052A (en)

Also Published As

Publication number Publication date
JPS62101052A (en) 1987-05-11

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