JPS59144146A - Manufacture of hybrid integrated circuit device - Google Patents
Manufacture of hybrid integrated circuit deviceInfo
- Publication number
- JPS59144146A JPS59144146A JP1941883A JP1941883A JPS59144146A JP S59144146 A JPS59144146 A JP S59144146A JP 1941883 A JP1941883 A JP 1941883A JP 1941883 A JP1941883 A JP 1941883A JP S59144146 A JPS59144146 A JP S59144146A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor chip
- resin
- wiring conductor
- conductors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Die Bonding (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、絶縁基板に半導体チップや電子回路部品を
装着した混成集積回路装置の製造方法の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a method for manufacturing a hybrid integrated circuit device in which a semiconductor chip and electronic circuit components are mounted on an insulating substrate.
近年、半導体素子や積層チップコンデンサ等の電子回路
部品が小形化され、絶縁基板上にこれらの部品を実装し
た混成集積回路装置(以下rH工0jと略称する)が多
量に使用されてきた。最近、さらに、HICを小形化す
るため、半導体装置製造業者が、半導体チップ単体を絶
縁基板上に実装したHIOを量産し、あらゆる分野に使
用されるようになった。BACKGROUND ART In recent years, electronic circuit components such as semiconductor elements and multilayer chip capacitors have been miniaturized, and hybrid integrated circuit devices (hereinafter abbreviated as rH-0j) in which these components are mounted on an insulating substrate have been used in large quantities. Recently, in order to further downsize HICs, semiconductor device manufacturers have mass-produced HIOs in which a single semiconductor chip is mounted on an insulating substrate, and these have come to be used in all fields.
従来のHICの製造方法を、第1図及び第2図について
説明する。第1図はHICのチップコンデンサ装着前の
状態の断面図である。絶縁基板(1)上に配線導体(2
)が形成されである。この配線導体(2)上のダイパッ
ド部に半導体チップ(3)を固着樹脂(4)でグイボン
ドし、後樹脂を硬化させる。続いて、金線又はアルミ線
等の金属細線(5)で半導体チップ(3)と対応する配
線導体(2)とをワイヤボンドにより接続する。次に、
半導体チップ(3)部を保護樹脂(6)で覆い、約12
5℃の温度で数時間加熱処理し硬化させて封止する。A conventional HIC manufacturing method will be explained with reference to FIGS. 1 and 2. FIG. 1 is a sectional view of the HIC before the chip capacitor is attached. Wiring conductor (2) on insulating substrate (1)
) is formed. A semiconductor chip (3) is firmly bonded to the die pad portion on this wiring conductor (2) with a fixing resin (4), and then the resin is cured. Subsequently, the semiconductor chip (3) and the corresponding wiring conductor (2) are connected by wire bonding using a thin metal wire (5) such as a gold wire or an aluminum wire. next,
Cover the semiconductor chip (3) with the protective resin (6) and
Heat treatment is performed at a temperature of 5° C. for several hours to harden and seal.
ついで、第2図に断面図で示すように、積層チップコン
デンサ(以下「チップコンデンサ」と略称する)(7)
などの電子回路部品を配線導体(2)上に当て、絶縁基
板+1j上に仮付樹脂(8)で接着し、樹脂を加熱硬化
させる。この状態の装置を溶融はんだ槽に浸漬し、チッ
プコンデンサ(7)を配線導体(2)にはんだ付けし、
HICを完成していた。(9)は接合はんだである。Next, as shown in the cross-sectional view in Fig. 2, a multilayer chip capacitor (hereinafter abbreviated as "chip capacitor") (7)
An electronic circuit component such as the above is placed on the wiring conductor (2) and adhered onto the insulating substrate +1j with a temporary bonding resin (8), and the resin is heated and cured. The device in this state is immersed in a molten solder bath, the chip capacitor (7) is soldered to the wiring conductor (2),
He had completed HIC. (9) is a joining solder.
上記従来の製造方法では、固着樹脂(4)、保護樹脂(
6)及び仮付樹脂(8)をそれぞれ加熱硬化させる各工
程で、それぞれ、100°C以上の温度で約1時間以上
宛加熱する必要がある。このため、多大な時間を要して
おり、長時間の加熱により、配線導体(2)の表面が酸
化し、チップコンデンサ(7)のはんだ付けのとき、接
合はんだ(9)のぬれが悪くはんだ付は不良を生じてい
た。In the above conventional manufacturing method, the fixing resin (4), the protective resin (
In each step of heating and curing 6) and tacking resin (8), it is necessary to heat each of them at a temperature of 100° C. or more for about 1 hour or more. This takes a lot of time, and the surface of the wiring conductor (2) oxidizes due to long-term heating, resulting in poor wetting of the joining solder (9) when soldering the chip capacitor (7). The attachment was defective.
また、従来の方法では、保護樹脂(6)で覆い加熱硬化
後、チップコンデンサ(7)をはんだ付けし、H’IO
の特性検査をするが、半導体チップ(3)が不良の場合
、既に硬化した保護樹脂(6)で封止された半導体チッ
プ(3)を良品に取換えることはできなく、このHIC
は不良品となっていた。なお、HICは上記第1図、第
2図では簡単のため半導体チップ(3)は1個のみを示
しているが、実際には高密度実装を要求され、半導体チ
ップ(3)は多数個が絶縁基板+l+上に実装されてお
り、不良半導体チップの取替えができないことは、製品
の歩留りを低下し大きな問題となっていた。In addition, in the conventional method, the chip capacitor (7) is soldered after being covered with a protective resin (6) and cured by heating, and the H'IO
However, if the semiconductor chip (3) is defective, the semiconductor chip (3) sealed with the hardened protective resin (6) cannot be replaced with a good one, and this HIC
was a defective product. In the HIC, only one semiconductor chip (3) is shown for simplicity in Figures 1 and 2 above, but in reality, high-density packaging is required, and a large number of semiconductor chips (3) are required. Since the semiconductor chips are mounted on an insulating substrate +l+, the fact that defective semiconductor chips cannot be replaced has been a major problem, lowering the yield of products.
この発明は、上記従来の方法の欠点を改良するためにな
されたもので、絶縁基板上の配線導体に、半導体チップ
と電子回路部品を固着樹脂で固着し、上記半導体チップ
をワイヤボンド後、中間特性検査をし不良半導体チップ
は良品に取替えるようにし、後、半導体チップ部を保護
樹脂で封止し、電子部品をはんだ浸漬によりはんだ接合
し、製作工程数を減少して所要時間を短縮し、歩留りを
向上して価格を低減した、混成集積回路装置の製造方法
を提供することを目的としている。This invention was made in order to improve the drawbacks of the above-mentioned conventional methods. A semiconductor chip and an electronic circuit component are fixed to a wiring conductor on an insulating substrate with a bonding resin, and after the semiconductor chip is wire-bonded, an intermediate Characteristics are inspected and defective semiconductor chips are replaced with non-defective ones. Afterwards, the semiconductor chip is sealed with a protective resin and the electronic components are soldered together using solder immersion, reducing the number of manufacturing steps and the required time. It is an object of the present invention to provide a method for manufacturing a hybrid integrated circuit device that improves yield and reduces cost.
以下、この発明の一実施例によるHICの製造方法を、
第3図及び第4図により説明する。まず、第3図に断面
図で示すように、絶縁基板(1)上に形成しである配線
導体(2)のダイパッド部上に、半導体チップ(3)を
導電性の固着樹脂(4)で接着するととモニ、チップコ
ンデンサ(7)を配線導体(2)上ニ固Xf樹脂(4)
で接着し、双方の固着樹脂(4)をともに加熱硬化する
。続いて、半導体チップ(3)を対応する配線導体(2
)に金属細線(3)でワイヤボンドする。その後、HI
Cの中間特性検査をし、良品のものは、第4図で示す次
工程に送る。ここで、半導体チップ(3)部を保護樹脂
(5)で覆い、約ユ25°Cの温度で加熱硬化させて封
止する。この状態の装置を溶融はんだ檜に浸漬し、チッ
プコンデンサ(7)を配線導体(2)にはんだ付けし、
HICを完成する。Hereinafter, a method for manufacturing HIC according to an embodiment of the present invention will be described.
This will be explained with reference to FIGS. 3 and 4. First, as shown in the cross-sectional view in Fig. 3, a semiconductor chip (3) is placed on a die pad part of a wiring conductor (2) formed on an insulating substrate (1) using a conductive adhesive resin (4). Once glued, place the chip capacitor (7) on the wiring conductor (2) and glue it with Xf resin (4).
and heat-cure both adhesive resins (4). Next, the semiconductor chip (3) is connected to the corresponding wiring conductor (2).
) with a thin metal wire (3). After that, H.I.
The intermediate characteristics of C are inspected, and those that are good are sent to the next process shown in FIG. Here, the semiconductor chip (3) portion is covered with a protective resin (5) and sealed by heating and curing at a temperature of about 25°C. The device in this state is immersed in molten solder, the chip capacitor (7) is soldered to the wiring conductor (2),
Complete HIC.
一方、HICの中間特性検査で不良の半導体チップ(3
)は良品に取替えて装着し、再特性検査をして良品を確
認し、上記と同様に次工程に送り、保護樹脂(5)によ
る封止とその後の工程処理をする。On the other hand, the semiconductor chips (3
) is replaced with a non-defective product, installed, re-inspected for characteristics to confirm that it is non-defective, and sent to the next process in the same manner as above, sealed with protective resin (5) and processed in the subsequent process.
なお、上記実施例では、半導体チップ(3)をダイボン
ドする固着樹脂(4)は、導電性の場合を示したが、絶
縁性の場合にも適用できるものである。この場合は特性
検査には、チップコンデンサ(7)等電子回路部品の電
極部は配線導体(2)に測定共で電気接融するなどして
行なう。In the above embodiment, the adhesive resin (4) to which the semiconductor chip (3) is die-bonded is conductive, but it can also be applied to an insulating resin. In this case, the characteristic test is performed by electrically welding the electrode portion of the electronic circuit component such as the chip capacitor (7) to the wiring conductor (2) during measurement.
また、上記実施例では、電子回路部品としてテップコン
デンサ(6)を装着した場合を示したが、これに限らず
他の種の電子回路部品を装着した場合にも適用できるも
のである。Further, in the above embodiment, a case was shown in which a TEP capacitor (6) was installed as an electronic circuit component, but the present invention is not limited to this and can be applied to cases in which other types of electronic circuit components are installed.
〔発明の効果〕
以上のように、この発明の製造方法によれば、絶縁基板
上の配線導体に、半導体チップと電子回路部品とをそれ
ぞれ固着樹脂で同時工程で固着処理し、上記半導体チッ
プをワイヤボンド後、中間特性検査をし、不良の半導体
チップや電子回路部品のあるときは良品と取替え再装着
するようにし、半導体チップ部を保護樹脂で封止し、電
子回路部品をはんだ浸漬によりはんだ接合するようにし
たので、製作工程数を減少し所要時間を短縮し、製品の
歩留りを向上し、価格が低減され、信頼度の高い混成集
積回路装置が得られる。[Effects of the Invention] As described above, according to the manufacturing method of the present invention, a semiconductor chip and an electronic circuit component are fixed to a wiring conductor on an insulating substrate in the same process with a fixing resin, and the semiconductor chip is After wire bonding, conduct an intermediate characteristic test. If there is a defective semiconductor chip or electronic circuit component, replace it with a good one and reinstall it. The semiconductor chip part is sealed with a protective resin, and the electronic circuit component is soldered by dipping in solder. By bonding, the number of manufacturing steps is reduced, the required time is shortened, the yield of the product is improved, the cost is reduced, and a highly reliable hybrid integrated circuit device can be obtained.
第1図は従来の製造方法による混成集積回路装置のチッ
プコンデンサ装着前の状態を示す概要断面図、第2図は
第1図の状態から構成される装置を示す概要断面図、第
3図はこの発明の一実施例の製造方法による混成集積回
路装置の半導体チップ部の樹脂封止前の状態を示す概要
断面図、第4図は第3図の状態から構成される装置を示
す概要断面図である。
図において、1・・・絶縁基板、2・・・配線導体、3
・・・半導体チップ、4.・・・固着樹脂、5・・・金
属細線、6・・・保護樹脂、7・・・電子回路部品をな
す積層チップコンデンサ、9・・・接合はんだ。
なお、図中同一符号は同−又は相当部分を示す。
代理人 葛 野 信 −(外1名)
第1図
第2図
第3図
第4図Fig. 1 is a schematic cross-sectional view showing the state of a hybrid integrated circuit device manufactured by a conventional manufacturing method before chip capacitors are mounted, Fig. 2 is a schematic cross-sectional view showing the device constructed from the state shown in Fig. 1, and Fig. 3 is A schematic sectional view showing a state before resin sealing of a semiconductor chip portion of a hybrid integrated circuit device according to a manufacturing method according to an embodiment of the present invention, and FIG. 4 is a schematic sectional view showing a device constructed from the state shown in FIG. 3. It is. In the figure, 1... Insulated substrate, 2... Wiring conductor, 3
...semiconductor chip, 4. . . . Fixed resin, 5. Thin metal wire, 6. Protective resin, 7. Multilayer chip capacitor forming an electronic circuit component, 9. Bonding solder. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Shin Kuzuno - (1 other person) Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
導体チップを固着樹脂でダイボンドするとともに、同一
工程で電子回路部品を上記配線導体上に固着樹脂で仮付
けし、上記半導体チップとこれに対応する上記配線導体
とを金属細線でワイヤボンドし、この状態で中間の特性
検査をし、上記半導体チップに不良品があれば良品に取
替えて装着し、上記半導体チップ部を保護樹脂で封止し
、この保護樹脂を硬化処理後、上記電子回路部品をはん
だ浸漬によりはんだ接合する混成集積回路装置の製造方
法。A semiconductor chip is die-bonded with adhesive resin onto the die pad portion of the wiring conductor formed on the insulating substrate, and in the same process, electronic circuit components are temporarily attached onto the wiring conductor with adhesive resin to correspond to the semiconductor chip. The above wiring conductor is wire-bonded with a thin metal wire, and in this state, an intermediate characteristic test is performed, and if the above semiconductor chip is defective, it is replaced with a good one and installed, and the above semiconductor chip part is sealed with a protective resin. . A method for manufacturing a hybrid integrated circuit device, which comprises curing the protective resin and then soldering the electronic circuit components by solder dipping.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1941883A JPS59144146A (en) | 1983-02-07 | 1983-02-07 | Manufacture of hybrid integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1941883A JPS59144146A (en) | 1983-02-07 | 1983-02-07 | Manufacture of hybrid integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59144146A true JPS59144146A (en) | 1984-08-18 |
Family
ID=11998708
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1941883A Pending JPS59144146A (en) | 1983-02-07 | 1983-02-07 | Manufacture of hybrid integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59144146A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59204298A (en) * | 1983-05-06 | 1984-11-19 | 松下電器産業株式会社 | Method of forming printed circuit board |
US5164328A (en) * | 1990-06-25 | 1992-11-17 | Motorola, Inc. | Method of bump bonding and sealing an accelerometer chip onto an integrated circuit chip |
-
1983
- 1983-02-07 JP JP1941883A patent/JPS59144146A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59204298A (en) * | 1983-05-06 | 1984-11-19 | 松下電器産業株式会社 | Method of forming printed circuit board |
US5164328A (en) * | 1990-06-25 | 1992-11-17 | Motorola, Inc. | Method of bump bonding and sealing an accelerometer chip onto an integrated circuit chip |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS59144146A (en) | Manufacture of hybrid integrated circuit device | |
JPH0551179B2 (en) | ||
KR102371636B1 (en) | Method for fabricating semiconductor having double-sided substrate | |
JPH0888248A (en) | Face-down bonding method and connecting material using thereof | |
JPH0574829A (en) | Manufacture of semiconductor integrated circuit device | |
JPS6313337A (en) | Process of mounting semiconductor element | |
JP2004253529A (en) | Semiconductor device and its manufacturing method | |
JPH1116939A (en) | Semiconductor device and manufacture thereof | |
JPH04237149A (en) | Manufacture and bonding method for electronic chip component | |
JP2841822B2 (en) | Manufacturing method of hybrid integrated circuit | |
JPH04326747A (en) | Mounting method for component | |
JP2822987B2 (en) | Electronic circuit package assembly and method of manufacturing the same | |
JPS63174340A (en) | Semiconductor device | |
JPH04252041A (en) | Manufacture of hybrid integrated circuit | |
JPH07263487A (en) | Manufacture of semiconductor device | |
JP2678111B2 (en) | How to remove the semiconductor device | |
JPH01134888A (en) | Manufacture of hybrid ic device | |
JPS624331A (en) | Wire bonding method | |
JPH0337305B2 (en) | ||
KR20000007226A (en) | Semiconductor package | |
JPS6342530Y2 (en) | ||
JPH07273235A (en) | Semiconductor device and its manufacture | |
JPH09306951A (en) | Manufacturing semiconductor device | |
JPS62101052A (en) | Manufacture of hybrid integrated circuit device | |
KR19980048271A (en) | Manufacturing method of lead-on chip package using liquid adhesive |