JPH0336957U

JPH0336957U -

Info

Publication number: JPH0336957U
Application number: JP1989097664U
Authority: JP
Priority date: 1989-08-22
Filing date: 1989-08-22
Publication date: 1991-04-10

Description

[Brief explanation of drawings]

第１図はこの考案の一実施例を示すブロツク図
、第２図は第１図の動作を説明するためのタイム
チヤート、第３図Ａ，ＢはＦ／Ｖ変換の出力特性
図および補償出力特性図、第４図は従来のＦ／Ｖ
変換回路を示すブロツク図、第５図は第４図の動
作波形図である。１２……波形整形回路、１３，１５……第１、
第２パルス幅変換回路、１６……フイルタ増幅回
路、１７……アナログスイツチ、１８……アナロ
グメモリ、１９……メモリ増幅回路、２０……出
力増幅回路、２２……補償増幅回路。 Fig. 1 is a block diagram showing an embodiment of this invention, Fig. 2 is a time chart for explaining the operation of Fig. 1, and Figs. 3 A and B are output characteristic diagrams of F/V conversion and compensation output. Characteristic diagram, Figure 4 is the conventional F/V
FIG. 5 is a block diagram showing the conversion circuit, and FIG. 5 is an operating waveform diagram of FIG. 4. 12... waveform shaping circuit, 13, 15... first,
2nd pulse width conversion circuit, 16... Filter amplifier circuit, 17... Analog switch, 18... Analog memory, 19... Memory amplifier circuit, 20... Output amplifier circuit, 22... Compensation amplifier circuit.

Claims

[Claims for Utility Model Registration] (1) A first device that receives a pulse signal detected by a speed detector and obtains an output signal whose pulse width is converted to an output in synchronization with the rise or fall of the pulse signal. a pulse width conversion circuit; a second pulse width conversion circuit to which the output signal of the first pulse width conversion circuit is supplied and which obtains at its output a pulse width output signal time-shifted from the first pulse width output signal; This second
A filter amplification circuit is supplied with the output signal of the second pulse width conversion circuit and obtains an average value output signal having ripples in its output, and the output signal from the second pulse width conversion circuit passes through the output signal of this filter amplification circuit. The analog switch is controlled by the output signal of the first pulse width conversion circuit immediately before the pulse width conversion circuit, and the analog switch is equipped with an analog memory that stores the obtained output signal, and a memory amplification circuit that outputs the stored signal of this analog memory. Features F/V conversion circuit. (2) The F according to claim 1, wherein the memory amplifier circuit is provided with a compensation amplifier circuit that compensates for a non-linear output signal and sends out a linear output signal.
/V conversion circuit.